JP2595717B2 - Inverter output current effective value detection circuit - Google Patents

Inverter output current effective value detection circuit

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Publication number
JP2595717B2
JP2595717B2 JP1152558A JP15255889A JP2595717B2 JP 2595717 B2 JP2595717 B2 JP 2595717B2 JP 1152558 A JP1152558 A JP 1152558A JP 15255889 A JP15255889 A JP 15255889A JP 2595717 B2 JP2595717 B2 JP 2595717B2
Authority
JP
Japan
Prior art keywords
inverter
circuit
input
signal
effective value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1152558A
Other languages
Japanese (ja)
Other versions
JPH0317564A (en
Inventor
吉弘 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP1152558A priority Critical patent/JP2595717B2/en
Publication of JPH0317564A publication Critical patent/JPH0317564A/en
Application granted granted Critical
Publication of JP2595717B2 publication Critical patent/JP2595717B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、電圧形インバータにおいてその直流電源
側からの入力電流によりその出力交流電流の実効値を近
似演算するインバータ出力電流実効値検出回路に関す
る。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter output current effective value detection circuit that approximates an effective value of an output AC current by an input current from a DC power supply side in a voltage type inverter. .

〔従来の技術〕[Conventional technology]

従来この種のインバータの交流出力電流の実効値検出
は、第4図の回路図に例示する如く、交流変流器による
前記交流出力電流の検出信号を入力とする専用の実効値
検出回路により行うものが知られている。
Conventionally, the effective value of the AC output current of this type of inverter is detected by a dedicated effective value detection circuit which receives the detection signal of the AC output current by an AC current transformer as shown in the circuit diagram of FIG. Things are known.

因に、第4図において、1は電圧形トランジスタ式イ
ンバータ、2は該インバータによって駆動されるモー
タ、Ciは前記インバータの直流電源となる直流中間回路
の出力側コンデンサ、7は前記の直流中間回路とインバ
ータ1との間の符号Aにて図示するDCリンク部を通過す
るインバータ入力電流の検出信号Saとその設定信号Sas
とを比較し該信号SaがSasよりも大となる前記入力電流
の過電流状態において出力を発するコンパレータ、8は
PWM基準信号を受け前記インバータ1の各スイッチング
トランジスタに対する制御信号を出力するベース駆動回
路、9は前記コンパレータ7の出力信号等の異常検出信
号を受け前記ベース駆動回路8に対する動作停止指令を
出力する保護回路、10は前記インバータ1の出力側にお
ける符号B図示部を通過するインバータ出力電流の交流
変流器による検出信号Sbを入力とし前記インバータ出力
電流の実効値検出信号Sbeを出力する実効値検出回路で
ある。
In this connection, in FIG. 4, the voltage-transistor type inverter 1, the motor 2 driven by the inverter, C i is the output side capacitor of the DC intermediate circuit comprising a DC power supply of the inverter, the DC link 7 Inverter input current detection signal Sa and its setting signal S as passing through the DC link section shown by reference character A between the circuit and the inverter 1
Comparator generates an output in the overcurrent state of the input current becomes larger than compared with the signal S a is S the as the door, the 8
A base drive circuit that receives a PWM reference signal and outputs a control signal to each switching transistor of the inverter 1; a protection 9 that receives an abnormality detection signal such as an output signal of the comparator 7 and outputs an operation stop command to the base drive circuit 8; circuit, 10 is the effective value of outputting the effective value detection signal S bE of the detection signal S b and input the inverter output current by the AC current transformer of the inverter output current passing through the code B shown section at the output of the inverter 1 It is a detection circuit.

また第5図の図(イ)と図(ロ)とはそれぞれ前記の
インバータ入力電流及び出力電流の電流波形図であり、
図示の如く、前記入力電流はパルス状波形となりまた前
記出力電流は正弦波に高調波の重畳した波形となる。
FIGS. 5A and 5B are current waveform diagrams of the inverter input current and output current, respectively.
As shown in the figure, the input current has a pulse-like waveform, and the output current has a waveform in which harmonics are superimposed on a sine wave.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

しかしながら上記の如き従来方式によるインバータ出
力電流の実効値検出においてはその周波数が変動し且つ
高調波成分を含む前記インバータ出力電流を検出する変
流器と専用の実効値検出回路とを必要としていた。
However, the conventional method of detecting the effective value of the inverter output current as described above requires a current transformer for detecting the inverter output current whose frequency fluctuates and contains a harmonic component and a dedicated effective value detection circuit.

上記に鑑み本発明は前記の変流器と実効値検出回路と
を共に不要となし前記インバータの入力電流検出信号よ
りその出力電流の実効値の近似値を演算出力するインバ
ータ出力電流実効値検出回路の提供を目的とするもので
ある。
In view of the above, the present invention eliminates the need for both the current transformer and the effective value detection circuit, and calculates and outputs an approximate value of the effective value of the output current from the input current detection signal of the inverter. The purpose is to provide.

〔課題を解決するための手段〕[Means for solving the problem]

上記目的を達成するために、本発明のインバータ出力
電流実効値検出回路は、電圧形インバータの出力電流実
効値検出回路であって、その直流電源より流入する前記
インバータの入力電流の検出回路と、該検出回路の出力
信号を入力としそのピーク値を充電するピーク充電回路
と、該ピーク充電回路の出力信号を入力とし長短複数の
時定数による減衰プログラムに従ってその入力信号を減
衰させたものをその出力信号となす入力減衰回路と、前
記ピーク充電回路の出力信号が前記インバータ入力電流
検出回路の出力信号より大となる期間を検出すると共に
該検出期間において所定のプログラムに従った時間信号
を出力し該時間信号に従って前記入力減衰回路の減衰プ
ログラムを進行させるタイマ回路とを設け、前記入力減
衰回路の出力信号として得られた前記インバータ入力電
流検出信号のピーク値の包絡軌跡を以って前記インバー
タの出力電流実効値の検出信号となすものである。
In order to achieve the above object, an inverter output current effective value detection circuit of the present invention is an output current effective value detection circuit of a voltage type inverter, and a detection circuit of the inverter input current flowing from the DC power supply, A peak charging circuit that receives the output signal of the detection circuit as an input and charges the peak value thereof, and outputs the signal obtained by attenuating the input signal according to an attenuation program with a plurality of long and short time constants using the output signal of the peak charging circuit as an input. An input attenuating circuit serving as a signal, and detecting a period in which the output signal of the peak charging circuit is larger than the output signal of the inverter input current detecting circuit, and outputting a time signal according to a predetermined program in the detecting period. A timer circuit for advancing an attenuation program of the input attenuation circuit according to a time signal, and an output signal of the input attenuation circuit; Envelope trajectory of the peak value of the inverter input current detection signal was collected using those formed by the detection signal of the output current effective value of the inverter drives out.

〔作用〕[Action]

インバータにおける電力損失と該インバータの出力電
力における高調波分を省略すれば、その直流中間回路に
より与えられる直流電圧と第5図の図(イ)の如きパル
ス状電流との積として与えられる前記インバータの入力
電力は、前記第5図の図(ロ)の如き交流電流の実効値
と該交流電流に対し負荷回路定数によって決定される位
相差を有する交流電圧の実効値と前記位相差に対応する
力率と負荷相数により決定される定数との積として与え
られる前記インバータの出力電力と等しくなる。従っ
て、前記の如きパルス状のインバータ入力電流のピーク
値は前記の如きインバータ出力電流の基本波の実効値に
比例するものとなる。
If the power loss in the inverter and the harmonic component in the output power of the inverter are omitted, the inverter is given as a product of the DC voltage given by the DC intermediate circuit and the pulsed current as shown in FIG. 5 corresponds to the effective value of the AC current and the effective value of the AC voltage having a phase difference determined by the load circuit constant and the phase difference as shown in FIG. 5 (b). It is equal to the output power of the inverter given as the product of the power factor and a constant determined by the number of load phases. Therefore, the peak value of the pulse-like inverter input current as described above is proportional to the effective value of the fundamental wave of the inverter output current as described above.

本発明は上記に従い、前記の如きパルス状のインバー
タ入力電流の各ピーク値の包絡軌跡を演算検出し、該検
出軌跡を以ってインバータ出力電流の実効値変動軌跡と
して近似するものであり、前記包絡軌跡の作成は前記入
力電流の各ピーク値間を複数の減衰時定数を有する減衰
曲線にて接続することにより行うものであり、このため
前記入力電流のピーク値を検出するピーク充電回路と前
記の減衰曲線に従いその入力信号を減衰させる入力減衰
回路と該減衰回路を所定の時間プログラムで駆動進行さ
せるタイマ回路とを設けるものである。
According to the present invention, the envelope trajectory of each peak value of the pulse-like inverter input current is calculated and detected as described above, and the detected trajectory is approximated as an effective value variation trajectory of the inverter output current. The creation of the envelope locus is performed by connecting each peak value of the input current with an attenuation curve having a plurality of attenuation time constants. Therefore, a peak charging circuit for detecting the peak value of the input current and the peak charging circuit And a timer circuit for driving and advancing the attenuating circuit according to a predetermined time program.

なお前記タイマ回路による前記時間プログラムの進行
速度は前記の入力電流パルスの繰返し周期に関連し最も
近似度の高い包絡軌跡が得られるように適当に決定され
る。
The progress speed of the time program by the timer circuit is appropriately determined so as to obtain an envelope locus having the highest degree of approximation in relation to the repetition period of the input current pulse.

〔実施例〕〔Example〕

以下この発明の実施例を図面により説明する。第1図
はこの発明の実施例を示す回路図、第2図は第1図回路
各部の動作波形図である。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is an operation waveform diagram of each circuit in FIG.

なお、第1図においては、前記第4図の場合と同一機
能の構成要素及び同一性格の信号に対しては同一の表示
符号を附している。
In FIG. 1, components having the same functions and signals having the same character as those in FIG. 4 are denoted by the same reference numerals.

第1図は前記インバータ入力電流の各パルスピーク値
間を接続する前記の減衰曲線を長短2種類の時定数τ
とτとに対応する2組の曲線により構成した場合を示
すものであり、図示の3は図示A部のDCリンク部を通過
するインバータ1の入力電流の検出信号Saを入力としそ
のピーク値を充電するピーク充電回路である。またコン
デンサCpと抵抗R1とR2と時定数切替スイッチ6とから成
る回路は、該スイッチにより切替えられる長時間時定数
τ(τ=R1Cp)と短時間時定数τ(τ=R2Cp
とにそれぞれ対応する減衰特性をもつ2組の曲線より成
る減衰曲線を作成し該曲線に従って前記充電回路の出力
信号を減衰させ、前記インバータ出力電流の実効値に対
応する前記信号Saのピーク値包絡信号Sbeを出力する入
力減衰回路となる。また4のコンパレータは前記信号Sa
とSbeとの大小を比較し該信号SaがSbeに等しいか或いは
所定の偏差以内にある場合に信号S1を出力し、5のタイ
マーは前記信号S1の印加中その限時動作を中止しその消
滅時点より期間T後に信号S2を出力し、該信号S2により
前記切替スイッチ6をその常時閉側bより開側aへ切替
えて前記時定数τをτへ変更するものである。
FIG. 1 shows the above-mentioned attenuation curve connecting between the pulse peak values of the inverter input current by using two types of long and short time constants τ 1.
And it shows the case of constituting the two sets of curves corresponding to the tau 2, the peak and 3 of illustration and inputs the detection signal S a of the input current of the inverter 1 through the DC link section of an A portion It is a peak charging circuit that charges a value. The circuit comprising the capacitor C p resistor R 1 and R 2 and time constant switching switch 6 which is long time constant tau 1 is switched by the switch (tau 1 = R 1 C p) a short time constant tau 22 = R 2 C p )
A damping curve composed of two sets of curves each having a damping characteristic corresponding thereto, attenuating an output signal of the charging circuit according to the curve, and a peak value of the signal Sa corresponding to an effective value of the inverter output current. the input attenuation circuit for outputting an envelope signal S bE. The comparator of 4 is the signal S a
The large and small compared to the signal S a and S BE outputs the signals S 1 when there within or equal a predetermined deviation S BE, 5 timers that time limit operation during the application of the signals S 1 those discontinued outputs a signal S 2 from the annihilation time after a period T, to change the selector switch 6 by the signal S 2 that the time constant tau 1 is switched constantly from the closed side b to the open-side a to tau 2 It is.

第2図は第1図における上記の如き動作に対応する各
部動作波形図であり、図(イ)と図(ロ)と図(ハ)と
はそれぞれ前記信号S2/SbeとS1とS2とを示すものであ
る。なお図(イ)に示す包絡軌跡Sbeのインバータ出力
電流実効値に対する近似度が不足する場合には、前記時
定数τとτとを更にτ,τ,τ…の如く細分
し、更に時定数切替えに対応する時間TをT1,T2,T3
の如く適当に細分すればよいことになる。
Figure 2 is a respective units operation waveform diagram corresponding to the above such operation in the first view, FIG and (b) FIG and (b) FIG and (c) and the signal S 2 / S BE and S 1, respectively It illustrates the S 2. When the degree of approximation of the envelope trajectory S be shown in FIG. 3A to the effective value of the inverter output current is insufficient, the time constants τ 1 and τ 2 are further subdivided into τ 1 , τ 2 , τ 3 . Then, the time T corresponding to the time constant switching is set to T 1 , T 2 , T 3 .
It is only necessary to subdivide appropriately.

また前記インバータ入力電流の取電部は、第1図に示
すA部からインバータ主回路のフリーホイールダイオー
ドの接続点変更を行った第3図のインバータ主回路図の
C部に変更しても第1図における場合と同様の結果を得
ることができる。
In addition, the inverter input current collecting part may be changed from the part A shown in FIG. 1 to the part C of the inverter main circuit diagram in FIG. 3 in which the connection point of the freewheel diode of the inverter main circuit is changed. The same result as in FIG. 1 can be obtained.

〔発明の効果〕〔The invention's effect〕

本発明によれば、パルス状波形となる電圧形インバー
タ入力電流の各波ピーク値間を適当な減衰特性を有する
曲線により接続して前記各波ピーク値の包絡軌跡を演算
し、該演算値より前記インバータの出力電流実効値を得
ることにより、該出力電流実効値を検出するための交流
変流器と専用の実効値検出回路とが不要となり、インバ
ータ装置構成の簡易化と低廉化とが可能となる。
According to the present invention, the waveform peak values of the voltage-type inverter input current having a pulse-like waveform are connected by a curve having an appropriate attenuation characteristic to calculate an envelope locus of the respective wave peak values. Obtaining the output current effective value of the inverter eliminates the need for an AC current transformer for detecting the output current effective value and a dedicated effective value detection circuit, thereby simplifying the configuration of the inverter device and reducing the cost. Becomes

【図面の簡単な説明】[Brief description of the drawings]

第1図はこの発明の実施例を示す回路図、第2図は第1
図回路各部の動作波形図、第3図はこの発明の第2の実
施例を示すインバータ主回路図、第4図は従来技術の実
施例を示す回路図、第5図は一般的な電圧形インバータ
における入力電流と出力電流との電流波形図である。 1……(電圧形トランジスタ式)インバータ、2……モ
ータ、3……ピーク充電回路、4……コンパレータ、5
……タイマ、6……時定数切替スイッチ、7……コンパ
レータ、8……ベース駆動回路、9……保護回路、10…
…実効値検出回路、Ci,Cp……コンデンサ、R1,R2……
抵抗。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is an operation waveform diagram of each part of the circuit, FIG. 3 is an inverter main circuit diagram showing a second embodiment of the present invention, FIG. 4 is a circuit diagram showing a prior art embodiment, and FIG. FIG. 4 is a current waveform diagram of an input current and an output current in an inverter. 1 ... (voltage-source transistor type) inverter 2 ... motor 3 ... peak charging circuit 4 ... comparator 5
... Timer, 6 Time constant changeover switch, 7 Comparator, 8 Base drive circuit, 9 Protection circuit, 10
… Effective value detection circuit, C i , C p …… Capacitor, R 1 , R 2 ……
resistance.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】電圧形インバータの出力電流実効値検出回
路であって、その直流電源より流入する前記インバータ
の入力電流の検出回路と、該検出回路の出力信号を入力
としそのピーク値を充電するピーク充電回路と、該ピー
ク充電回路の出力信号を入力とし長短複数の時定数によ
る減衰プログラムに従ってその入力信号を減衰させたも
のをその出力信号となす入力減衰回路と、前記ピーク充
電回路の出力信号が前記インバータ入力電流検出回路の
出力信号より大となる期間を検出すると共に該検出期間
において所定のプログラムに従った時間信号を出力し該
時間信号に従って前記入力減衰回路の減衰プログラムを
進行させるタイマ回路とを設け、前記入力減衰回路の出
力信号として得られた前記インバータ入力電流検出信号
のピーク値の包絡軌跡を以って前記インバータの出力電
流実効値の検出信号となすことを特徴とするインバータ
出力電流実効値検出回路。
1. An output current effective value detection circuit for a voltage type inverter, comprising: a detection circuit for detecting an input current of the inverter flowing from a DC power supply; and an output signal of the detection circuit as an input to charge a peak value thereof. A peak charging circuit, an input attenuating circuit which receives the output signal of the peak charging circuit as an input, attenuates the input signal in accordance with an attenuation program with a plurality of long and short time constants, and forms an output signal thereof, and an output signal of the peak charging circuit A timer circuit for detecting a period in which the output signal of the inverter input current detection circuit is larger than the above, outputting a time signal according to a predetermined program in the detection period, and executing an attenuation program of the input attenuation circuit according to the time signal. And an envelope of a peak value of the inverter input current detection signal obtained as an output signal of the input attenuation circuit. Inverter output current effective value detection circuit, characterized in that forming the marks and a detection signal of the output current effective value of the inverter I following.
JP1152558A 1989-06-15 1989-06-15 Inverter output current effective value detection circuit Expired - Lifetime JP2595717B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1152558A JP2595717B2 (en) 1989-06-15 1989-06-15 Inverter output current effective value detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1152558A JP2595717B2 (en) 1989-06-15 1989-06-15 Inverter output current effective value detection circuit

Publications (2)

Publication Number Publication Date
JPH0317564A JPH0317564A (en) 1991-01-25
JP2595717B2 true JP2595717B2 (en) 1997-04-02

Family

ID=15543102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1152558A Expired - Lifetime JP2595717B2 (en) 1989-06-15 1989-06-15 Inverter output current effective value detection circuit

Country Status (1)

Country Link
JP (1) JP2595717B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4631575B2 (en) * 2005-07-20 2011-02-16 パナソニック株式会社 Inverter device

Also Published As

Publication number Publication date
JPH0317564A (en) 1991-01-25

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