JP2593118B2 - repeater - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal waveform shaper (hereinafter, referred to as a repeater) for correcting waveform distortion of a transmission line or apparatus for performing data communication.

[0002]

2. Description of the Related Art Generally, in high-speed serial communication using an HDLC signal, in order to realize long-distance transmission or multi-unit communication, waveforms such as temporal distortion and amplitude distortion occurring in a transmission line itself and a transmitting / receiving element are generally used. In order to correct the distortion, a signal waveform shaper (hereinafter, referred to as a repeater) is used.

One of the methods is to correct only the amplitude direction without correcting the waveform distortion in the time direction. This is an application that does not care about temporal waveform distortion, that is, 100 KBPS (NR
It is used for relatively low-speed communication up to Z). This application is mainly for media conversion, such as RS232C-RS485 conversion and RS232C-optical fiber conversion.

[0004] Although this circuit is extremely simple, it cannot correct waveform distortion in the time direction.
Z) Since it cannot be used as a repeater for high-speed communication, a method of demodulating data using a DPLL, receiving a data packet, re-creating the packet using a microprocessor or the like, modulating the data packet, and transmitting the data packet is used for this purpose. is there.

[0005] This method is a method used in general-purpose LANs and the like, which is close to "complete" in that it can cope with different communication speeds. However, there is a drawback that a delay of several ms to several tens of ms occurs depending on the size of. or,
The circuit scale becomes extremely large.

In order to eliminate this drawback, a FIFO is used while demodulating data using a DPLL (digital PLL).
Has been proposed to absorb and modulate the frequency deviation and transmit the modulated signal. According to this method, a delay of 4 to 5 data bits until the DPLL is locked, and a FIFO for adjustment.
Since only a delay of the number of data bits stored in
Only a delay of a few hundred μs.

[0007]

SUMMARY OF THE INVENTION However, DPLL
If there is no mechanism to generate the preamble that is lost before locking, the preamble will decrease,
There is a problem that the circuit scale becomes large, and even if the delay in one stage is not so large, the value becomes large when connected in multiple stages.

The present invention has been made in view of such a situation, and has a function of correcting both time distortion and amplitude distortion so as to be compatible with high-speed communication, has a small delay between input and output, and has a very small scale. It is intended to provide a repeater which can be constituted by a circuit.

[0009]

In order to solve such a problem, the present invention has two or more ports, selects a port to which data has been previously input as an input, and uses a signal change point as a reference. It is determined whether the signals 1, 0 and the data format are normal or abnormal. If the data format is normal, the data is output to all ports not selected as inputs through a deviation absorption FIFO at a normal timing. If it is abnormal, the operation is terminated by judging the end of the data, and the operation returns to the input waiting state by monitoring the disappearance of the data on the signal line and the timer time.

[0010]

When the amplitude and the format of the signal are normal with respect to the change point of the signal, the deviation is absorbed and output, and when the data format is abnormal, the process returns to the input wait state.

[0011]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a plurality of types of data are supplied to an input determination / port selection unit 1 where the presence or absence of an input is determined.
Select and control the input port. The presence or absence of an input is determined based on the presence or absence of a level, the presence or absence of a carrier, the presence or absence of an H or L level input, and the like. The input port is selected on a first-come, first-served basis. In the case of the same port, the selection is made based on the priority assigned to each port. After the selection, the selection is continued until a return signal is input.

The selected data from the input determination / port selection is supplied to a data determination / reproduction unit, which determines whether or not the data format is abnormal based on a data change point. Play the data. At this time, a beard-like noise that has entered the data is removed as needed. At this time, such as conversion from Manchester to NRZ code,
No data format conversion is performed.

The data is determined, for example, when the signal is in a Manchester code, FM0 code, or FM1 code format and has a baud rate of 16 bits.
In the case of using a double sampling clock, for example, if the number of clocks from one change point to the next change point is 1-3, it is ignored as noise, and if it is 4-12, it is recognized as a half-width pulse of baud rate, and data is reproduced. If it is 20, it is recognized as a pulse of the full width of the baud rate and data is reproduced, and if it is 21 or more, it is recognized as an abnormal data format. However, the numbers and determination methods given here are merely examples, and there are many variations. The point is to judge whether the data format is normal or abnormal, and what kind of data is based on the time width from the data change point to the change point.

If the signal is in the HDLC format and the NRZI code format, if the change from the data change point to the next change point is more than the 7-bit width of the signal speed, it is determined as an abnormal data format.

When the input judging / port selecting section 1 detects an input while the apparatus is in an input waiting state, an input port is selected by first-come-first-served and priority control. The data discriminating / reproducing unit 2 receives the selected data of the port selected from the input discriminating / port selecting unit 1, reproduces the data if the data format is not an abnormal data format, and sends out the data to the FIFO unit 3 if the data format is abnormal. If the operation stops.

The FIFO section 3 secures a time necessary for waveform shaping and adjusts a deviation between a signal frequency and an output clock, and temporarily stores data. When the adjustment data accumulates, the transmission control unit 4 causes the output selection unit 5 to start outputting. When an abnormal data format detection signal is received from the data discriminating / reproducing unit 2, the transmission control unit 4 transmits all the data accumulated in itself. , EOF (end of frame), the transmission of data is stopped, and the transmission control unit 4 also stops operating.

When a certain time elapses after the data transmission is stopped or a certain time elapses after the data on the signal line disappears,
Alternatively, each part is initialized after a certain time after the detection of abnormal data, and returns to the initial state.

The output selector 5 selects a port to output,
The data is output to the port, and the transmission control unit 4 stores the data for adjustment in the FIFO unit 3 and then starts the output. After the abnormal data format exists, all the data in the FIFO unit 3 is transmitted, and the EOF (end of frame) is transmitted. A series of controls such as sending is performed.

After the detection and transmission of abnormal data, the return control unit 6 stops the operation of each unit and stops accepting new data. However, after the end of transmission or after the end of transmission, or after the disappearance of data on the signal line, Each unit is initialized by the time or the time after the detection of the abnormal data format, and is returned to the input receiving (waiting) state.

In the device configured as described above, when the device is in a reception waiting state, the input determination / port selection unit 1 selects and receives one of two or more ports in the order of data arrival. It is determined whether the data is 1 or 0 or has an abnormal data format according to the above-described criterion based on the change point of the received data.

If the data format is determined to be normal, the data is reproduced in the time direction by the data discriminating / reproducing unit 2 and then supplied to the output selecting unit through the FIFO unit 3 for absorbing one or more bits of deviation. Is output to an empty port, that is, a port not selected. If the data format is abnormal, stop data input and
Transmit all the data stored inside IFO3, transmit data of 0 bits or more indicating abnormal transmission such as abnormal data,
After waiting for data disappearance on the transmission path and waiting for time, the state transits to the reception waiting state.

As described above, conventionally, a gate array of 4
Although the number of gates is more than 100 to 500, in the present invention, about 200 to 300 gates are sufficient, and the circuit scale is reduced. In the case of 1 Mbps and Manchester coding data communication, there is a delay of at least about 6 μs in the prior art, but according to the present invention, it is only about 2 μs. The delay to output has been reduced. This has the effect of greatly improving the number of stages used and the high-speed responsiveness of the network, and the reduction of the circuit scale leads to a significant reduction in cost and simplification of assembly.

[0023]

According to the present invention, the normal or abnormal state of data is judged at the data change point. If the state is normal, a signal whose timing is adjusted is output. Therefore, there is an effect that economy is good.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input determination / port selection part 2 Data determination / reproduction part 3 FIFO part 4 Transmission control part 5 Output selection part 6 Return control part

Claims (1)

(57) [Claims] 1. A device having two or more ports, selecting a port to which data has been previously input as an input, and judging the normal / abnormal of the signal format and the data format based on a change point of the signal. An input determination port selector for output, an output selector for adjusting the timing to normal if the data format is normal, and outputting to all ports not selected as input, and determining the end of data if the data format is abnormal, send And a return control unit for returning to an input waiting state by monitoring the disappearance of data on the signal line, the timer time, and the like.