JP2592878B2 - General-purpose programmable counter, timer and address registration module - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a general-purpose programmable module that forms a timing or address registration (register) function for a replacement board of a test equipment. In particular, the present invention allows microcomputer programmable time base generators and data for counting timers, arbitrary function generators, real-time digitizers and pinned electronic stimulus response generators to enter and exit memory in the instrument in a regular manner. Regarding the address register module.

BACKGROUND ART Electronic equipment used for automatic inspection equipment must have an accurate and accurate time base generator and accumulator. In addition, the time base generator must be programmable in various modes and must be useful in instruments such as counting timers, random number generators and real time digitizers to ensure some flexibility in the testing procedure.
Further, for such devices, the device is directly operated,
A computer or microcomputer that accumulates data generated by the device is required.

The interface between the time base generator of a conventional device and the memory of a computer required a huge amount of logic circuitry to operate the device and form the complex functions required to interface well with a microcomputer. Such a logic circuit usually requires many integrated circuit ICs. The design cost is high for each special circuit, and of course the hard wire cost is high. Also, such circuits require a relatively large circuit board area, further increasing costs. The power consumption tends to be high, and therefore an excessive amount of heat is generated. With this amount of heat, reliability did not improve as expected,
It is difficult to detect accidental failures and it takes time to repair.

DISCLOSURE OF THE INVENTION In accordance with the present invention, a programmable device useful as a counter / timer, time reference generator and memory address control or registration is provided. The apparatus comprises means for receiving a clock input signal and computer input means for forming an input from a computer. The processing means processes at least one clock input signal and input from the computer to form at least one output. The control means controls the processing means according to further input from the computer to determine a destination of the generated output. The output selection means selects at least one output provided for use outside the device.

Output selection means including at least one switch selects at least one output in response to additional input from the computer. This switch has circuitry useful for directly addressing the memory.

The processing means includes a counter responsive to the clock input signal. Of course, means for preloading the counter according to the input from the computer are also formed.
The register stores the count value in the counter.

The computer input means includes interactive data means for receiving and transmitting data. Of course, it also has an input data buffer for storing the data loaded into the counter. Further, the computer input means includes an instruction buffer or register for storing further input from the computer.

A register and a counter form the output to the output selection means.

If the frequency of the clock is high, a programmable prescaler may be formed to divide the frequency into a frequency suitable for use by the counter. The prescaler can be programmed according to input from a computer.

In order to easily and effectively carry out the present invention, the following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a general-purpose programmable counting / timer address registration module according to the present invention, FIG. 2A is a partial schematic diagram of the output switch of FIG. 1, and FIG. 2B is the output of FIG. FIG. 2C is a schematic diagram of an additional portion of the output switch of FIG. 1, FIG. 2D is a schematic diagram of the remaining portion of the output switch of FIG. 1, and FIG. 1, FIG. 4 is a schematic diagram of the input data buffer of FIG. 1, FIG. 5 is a schematic diagram of the primary counter of FIG. 1, and FIG. 6 is a pointer of FIG. Schematic diagram of latch and external start controller, No.
FIG. 7A is a partial schematic diagram of the prescaler and controller of FIG. 1,
FIG. 7B is a schematic diagram of the rest of the prescaler and controller of FIG. 1, FIG. 8 is a schematic diagram of the input control section of the input and clock controller of FIG. 1, and FIG. 9 is the input and clock diagram of FIG. FIG. 10 is a schematic diagram of the clock control unit of the clock controller, FIG. 10 is a schematic diagram of the counter of FIG. 1 using three modules, and FIG.
FIG. 1 is a schematic diagram of the random number generator using three modules, FIG. 12 is a schematic diagram of the real-time digitizer of FIG. 1 using three modules, and FIG. 13 is a diagram using two modules. FIG. 2 is a schematic diagram of the digital word generator of FIG. 1.

BEST MODE FOR CARRYING OUT THE INVENTION The apparatus of the present invention is constructed by depositing two layers of metal wiring on a gate array of the type commonly marketed by the semiconductor manufacturer of Applied Microcircuits of San Diego, California. Preferably. The resulting semiconductor chip is sealed in a 100-pin grid array (package with a grid of pins). Such a grid array according to the present invention has a size of 31.75 × 31.75 mm on a circuit board.
^It occupies an area of ² and a height of about 5.08 mm, but can be replaced with about 60 to 70 conventional integrated circuits in applications where the gate circuit is fully utilized.

For the purpose of understanding the drawings, input / output circuits having pin designation symbols in the form of five characters are indicated by bold lines when connected to the outside of the device 20 and by thin lines when connected internally.

For the purposes of a better understanding of FIGS. 1 to 9, the following table specifies the symbols representing the various buses of the device according to the invention. Bus designation symbol Address bus 22 ADDR Internal data bus 36 DBUS Programmable bus 45 MBUS Load bus 55 LBUS Count bus 60 CBUS Latch bus 64 PBUS Status bus 72 SBUS The following symbols used in Figs. Have been.

E / E Conversion from ECL to ECL (operation) T / E Conversion from TTL to ECL S Output cell FF Flip-flop H High-speed gate 1.2 Gate delay time (nanosecond) 1.3 etc. The reference means ECL logic 0.

Referring to the block diagram of FIG. 1, the device 20 of the present invention has a microcomputer (not shown) and interconnections for various functions. The address function formed by the data on the 12-bit address bus 22
Each use of the device 20 allows the microcomputer to allocate an area of memory. The data on the address bus 22 includes an input and clock controller 24 and FIG.
It is supplied to an 8 to 1 switch (multiplexer) 26 of the output switch 28 in FIGS. 2C and 2D. Address bus
3 least significant bits of 22 (0th, 1st and 2nd bits)
Up to this point, the device 20 is used to specify three internal registers to be loaded or read as described later.

By means of a conventional 8-bit or 16-bit bidirectional tri-state (three-state) data bus 30 for high precision, data from a designated area of the microcomputer memory is requested to the device 20; Data from 20 may be provided to the memory. Therefore, at the end of the data bus 30, a tri-state bidirectional receiving / driving circuit 32
(FIGS. 2A, 2B, 2C and 2D) are each connected and in communication with the device 20. Data from the output of the switch 26 is supplied to the input of the receiving / driving circuit 32 via the internal bus 34, and then is sent to the data bus 30 to be supplied to the microcomputer. On the other hand, the data appearing on the data bus 30 is sent to the 8-bit internal data bus 36 and distributed to the selection register in the device 20. The direct operation of the receive / drive circuit 32 is determined by the input and control signals supplied to the bus 38 from the clock controller 24. Of course, bus 38 also provides control signals to 8: 1 switch 26 and 2: 1 switch 40 (FIGS. 2A, 2B, 2C and 2D) of output switch 28. .

The data on the internal data bus 36 includes an instruction buffer 42, an input data buffer 44, a prescaler and a controller 48 (7th A
(FIG. 7B and FIG. 7B).

Of course, the buses necessary for interconnecting the microcomputer 20 with the device 20 include a chip selection function, a clear function for unconditional clearing for initialization of counters and registers at the time of power supply, reading and writing, as described later. A control bus 50 that provides input to the input and clock controller 24 for embedded and other functions. Of course, it is necessary that the timing function of the device 20 be synchronized with an external clock (not shown). As a result, as input to ECL compatible input prescaler and a controller 48 of the prescaler 49 is supplied with a clock signal of 100 MHz _Z, the TTL input is supplied with a frequency lower than 100 MHz _Z as will be described later. Prescaler 49, Bus 52
Are programmed to form the various time references by the signals on the programming bus 45 from the control register 46 in accordance with the inputs appearing on and the command signals from the clock controller 24. Of course, the bus 52 is connected to the input and clock controller 24.
Is supplied to the instruction buffer 42. Pulses from prescaler 49 are provided to input and clock controller 24 by line 51.

The data from the device 20 is transmitted from each output of the 2-to-1 switch 40 to the 12-bit ECL output bus 5 without passing through the data bus 30.
It is supplied directly to the microcomputer memory by means of a 6 or 12 bit TTL output bus 58. This switch 40 is connected to a first group of inputs connected to the address bus 22 via buses 56 and 58, or to an input bus connected to a counting bus 60 having data corresponding to the count of the primary counter 54. From the second group of. The primary counter 54 may preload data transferred from the input data buffer 44 to the load bus 55.

Either of the eight input groups connected to the eight-to-one switch 26 can be controlled by a control signal on bus 38 to transmit bidirectional data from bus 34 via tri-state receive / drive circuit 32. Can be placed on bus 30. The count bus 60 and the address bus 22 are connected to the first and second inputs of the 8-to-1 switch 26, similarly to these inputs of the 2-to-1 switch 40.

The output of the pointer latch 62 is supplied to the third input of the switch 26 via the latch bus 64. This pointer latch 62, when directed by a control signal on line 66 from an external activation controller 68, as shown in FIG.
The count value supplied from the primary counter to the count bus 60 is stored. This control signal is synchronized with the clock by a clock pulse provided from input and clock controller 24 to external start-up controller 68 via line 70.

The fourth input of the switch 26 is supplied with data from the instruction buffer 42 via the status bus 72. Of course, the data on status bus 72 is also provided to input and clock controller 24 to indicate the status of certain select signals, some of which
Although it is unnecessary for the operation, it plays a role of facilitating the determination by the automatic inspection device whether or not the device 20 has functioned favorably.

The other input of the switch 26 is connected to a counting status bus 74, which starts with the primary counter 54 and supplies status data indicating the status of the counter 54. Of course, counting status bus 74
Supplies status data to the input and clock controller 24,
It is connected to the outside of the device 20 via a series of pins 76 and provides the signals on bus 74 directly.

An additional input of the switch 26 is data from the programming bus 45, as already noted and described in more detail below.

FIG. 2A, FIG.
Please refer to FIG. 2B, FIG. 2C and FIG. 2D. Each bit of address bus 22 is connected to one of receivers 80A-80L. Each output of the receivers 80A to 80L is supplied to each of the drivers 81A to 81L. The outputs of the drivers 81A to 81L are supplied to first inputs of the switches 40A to 40L, each of which constitutes a two-to-one switch 40 (FIG. 1). The second inputs of these switches 40A to 40L are connected to the corresponding bits of the counting bus 60. The selection input S of each of the switches 40A to 40L is connected to bit 3A of the status bus 72 and the corresponding line (SBUS3). Thus, the state of the bit on the status bus 72 determines whether the contents of the address bus 22 or the contents of the counting bus 60 are provided to the aggregate output of switches 40A-40L.

The outputs of these switching units 40A to 40L are connected to ECL drivers 82A to 82A, respectively.
Connected to 82L input. The outputs of drivers 82A-82L collectively form the bits of ECL output bus 56. Each inverted output of switches 40A-40L is connected to each input of inverters 84A-84L, each forming an input for each TTL driver 86A-86L. The outputs of the drivers 86A-8L collectively comprise the bits of the TTL output bus 58.

Each inverter / driver 88A, 88C (Fig. 2A) and 88E (2B
FIG. 3 forms three bits from the least significant bit of the address bus 22. These inverters / drivers 88A, 88C and 88E
Are output as IA0, IA1 and IA2. An additional inverter 88E '(FIG. 2B) is connected to the inverting output of input buffer 80E to provide an output IA2N (or A2, the inverse logic of A2).
To form These outputs IA0, IA1, IA2 and IA2N are used to select internal registers, as noted above and in more detail below. A series of sixteen 4-to-1 switches 26A-26H and 26A'-26H '(FIGS. 2A, 2B, 2C and 2D) collectively
A one-to-one switch 26 (FIG. 1) is constructed. Switch 26A-26H
And 26A 'to 26H' each have four data inputs I0, I1, I2
And I3. The presence of a logic H or L at the data select inputs SO and S1 indicates that the four data inputs I0, I1, I2 and
Determine which of I3 appears at data output Y. Such an output is not output until the optimal enable signal is present at enable input EN.

The switches 26A-26H and 26A'-26H 'are operated in pairs,
Therefore, two 8's are connected to the tristate bidirectional data bus 30.
Allows a byte of bits to be present. Especially IA2
In order to secure the logic state, the first group of switches 26A-2A
6H possible input is connected. On the other hand, the second group of switches
Possible inputs 26A'-26H 'are connected to IA2N. Thus, a first group or first group of switches is possible, but never both groups. Further, the data output Y of each set of switches 26A and 26A ', 26B and 26B' is connected to each OR gate.
Connected to 90A ~ 90H. It is noted that these OR gates 90A to 90H are simple OR connection gates and improve the operation speed. The respective outputs of the RO gates 90A to 90H are connected to the respective inputs of the input buffers 92A to 92H of the receivers / drivers 32A to 32H collectively forming the receiver / drive circuit 32.

Outputs of the buffers 92A to 92H are connected to respective drivers 94A to 94H of the reception / drivers 32A to 32H. The drivers 94A-94H each have a control input. When the output enable signal OUTEN is applied to each control input, the drivers 94A to 94H supply data to the tristate bidirectional data bus 30.

The outputs of the drivers 94A-94H are, of course, also supplied to the receivers 96A-96H of the receiver / driver 32. These receivers 96A
The outputs of .about.96H are sequentially supplied to the drivers 98A to 98H. The outputs of drivers 98A-98H provide eight bits of data to internal data bus 36. When drivers 94A-94H are enabled by OUTEN, a bidirectional tri-state bus
30 and the data supplied to the internal data bus 36 are derived from the outputs of the first group of switches 26A-26H, or
Data from OR gates 90A-90H derived from outputs 26A'-26H '. When the drivers 94A-94H are inhibited by OUTEN, the tri-state outputs of the drivers 94A-94H are released. Thus, the data on the bidirectional tri-state data bus 30 appears at the inputs of the receivers 96A-96H and, of course, appears on the internal data bus 36 as the aforementioned 8-bit data.

The outputs of the drivers 81A-81L representing the 12-bit address bus 22 are applied to one I0 input of switches 26A-26M and 26A'-26M '. Referring to FIG. 2A, the least significant bit or 0 bit, A0, is applied to the I0 input of switch 26A. The least significant bits of the count bus 60, latch bus 64 and status bus 72 are applied to I1, I2 and I3 of switch 26A, respectively. The eighth bit A8 of the address bus 22 is applied by driver 81B to input I0 of switch 26A '. Counting bus 6
0, the eighth bit of latch bus 64 and state bus 72 are applied to I1, I2 and I3 of switch 26A ', respectively.

The second lower bit or one bit, A1 of the address bus 22, is applied by the driver 81C to the I0 input of the switch 26B. Corresponding bits on the count bus 60, latch bus 64 and status bus 72 are applied to I1, I2 and I3 of switch 26B, respectively.
The ninth bit A9 of the address bus 22 is applied to the input I0 of the switch 26B 'by the driver 81D. The corresponding bits of the count bus 60, the latch bus 64, and the status bus 72 are switches.
26B 'is applied to I1, I2 and I3.

The selection input S0 of the switches 26A, 26A '26B and 26B' is
Although connected to the output of 1A, switches 26A, 26A'26B and
The selection input S1 of 26B 'is connected to the output of the driver 81C. Thus, the logic values of bits A0 and A1 on address bus 22 determine which inputs of switches 26A, 26A '26B and 26B' appear at the Y output.

The outputs of switches 26A-26H and 26A'-26H 'are each determined according to the following table.

Selection input output S0 S1Y 0 0I0 0 1I1 1 0I2 1 1I3 Therefore, the values of bits A0 and A1 select the corresponding bit logical values of the four buses of address bus 22, count bus 60, latch bus 64 and status bus 72. , Switches 26A, 26A'26B and 26
It is shown in the output of B '. However, the logical values of IA2 and IA2N determine the bytes whose bits are actually selected. For example,
Least significant bit (0th bit) or 8th bit of the selected bus
The logical value of any of the bits appears at the output of driver 94A and becomes the least significant bit of internal data bus 36, if OUTE
If N is at the optimal logic level, it will be the least significant bit of the bidirectional tristate data bus 30. In a similar manner, the logical value of the first or ninth bit of the selected bus appears at driver 94B and becomes the second lower bit of internal data bus 36, if OUTEN is at the optimum logical level. For example, it becomes the second lower bit of the bidirectional tristate data bus 30.

Referring to FIG. 2B, the second bit of the same four buses is provided as an input to switch 26C, while the tenth or (hex) A bit is provided as an input to switch 26C '. I have. The third bit on the same bus is provided as an input to switch 26D, while the eleventh or B-th bit is provided as an input to switch 26D '. Switches 26C, 26C ', 26D and 26
The selection input S0 of D 'is controlled by the value of IA0, while the selection input S1 of these switches is controlled by the value of IA1. Thus, a logical value of either 2 or 10 bits appears as bit 2 of internal data bus 36 and, if desired, as bit 2 of bus 30. The logical value of either the third or eleventh bit appears as bit 3 of internal data bus 36.

Referring to FIG. 2C, address bus 22, counting bus 60,
Bit 4 inputs of latch bus 64 and status bus 72 are provided to inputs I0, I1, I2 and I3 of switch 26E, respectively. The 0th bit of the programming bus 45 is supplied to the I0 input of the switch 26E ', and the twelfth or Cth bit of the counting bus 60 is connected to the switch 26E'.
It is supplied to the I1 input of E '. The output of the trigger flip-flop (FIG. 6) is supplied to the I2 input of the switch 26E ', while the I3 input is grounded.

Bit 5 lines of the address bus 22, the counting bus 60, the latch bus 64, and the status bus 72 are connected to the inputs I0, I1, I
2 and I3. The first bit of the programming bus 45 is supplied to the I0 input of the switch 26F 'and the counting bus 6
The thirteenth or Dth bit of 0 is provided to the I1 input of switch 26F '. The I2 input of this switch 26F 'is supplied with the end of the count output of the flip-flop associated with the primary counter 54 (FIG. 5), while the I3 input is grounded.

The select input S0 of switches 26E, 26E ', 26F and 26F' is controlled by the logic value of IA0, while select input S1 is controlled by the logic level of IA1. As described above, IA2 and IA2
The logical value of N controls which output of switches 26E and 26E 'appears as the output of driver 94E and which of switches 26F and 26F' appears as the output of driver 94F.

Referring to FIG. 2D, bit 6 inputs of the address bus 22, the count bus 60, the latch bus 64, and the status bus 72 are each a switch.
26G inputs I0, I1, I2 and I3. Bit 2 of the programming bus 45 is provided to the I0 input of switch 26G ', and the fifteenth or E-th bit of counting bus 60 is connected to switch 26G'.
Is supplied to the I1 input. The I2 input of the switch 26G 'is supplied with the logically inverted value of the highest count output of the primary counter 54 (FIG. 5), while the I3 input is grounded.

Bit 7 lines of the address bus 22, the counting bus 60, the latch bus 64 and the status bus 72 are connected to the inputs I0, I1, I
2 and I3. Bit 3 of the programming bus 45 is provided to the I0 input of the switch 26H 'and the counting bus 60
The 16th or F-th bit of is supplied to its I1 input.
The signal TCNT from the primary counter 54 (FIG. 5) is input to the I2 input.
L1 is supplied while the I3 input is grounded.

The select input S0 of the switches 26G, 26G ', 26H and 26H' is controlled by the logic value of IA0, while the select input S1 is controlled by the logic level of IA1. As described above, IA2 and IA2
The operation based on the value of N is described above.

Referring to FIG. 3, instruction buffer 42 has a series of flip-flops 100A-100H, each receiving data from bits 0-7 of internal data bus 36 at a D input.
These flip-flops 100A to 100H are all reset by the signal RESET4 from the input and clock controller 24 (FIG. 8), and input and signal from the clock and clock controller 24 (FIG. 8) by the method of each gate 102A to 102H. Clocked by CPMODL. The Q outputs of these flip-flops 100A-100H are applied to status bus 72 as bits 0-7. Of course, flip-flops 100A, 100B, 100E, 100F, 100G and 10
A QN of 0H (ie) is also provided through device 20 '. The QN output of flip-flop 100D is formed as an input of OR gate 104. The OR gate 104 has the second and third inputs grounded. The output of the OR gate 104 is connected to the input of a driver 106 that generates a signal SBUS3B that is logically the same as SBUS3A. This driver may form two outputs instead of one to increase the additional fan-out capability (drive power).

Of course, instruction buffer 42 has four flip-flops 100A'-100D 'each receiving data from bits 0-3 of internal data bus 36 at the D input. These flip-flops 100A 'to 100D' are all reset by the signal RESET4 from the input and clock controller 24 (FIG. 8), and the input and clock controller 24 (FIG. 8) is operated by the method of each gate 102A 'to 102D'. ) Is clocked by the signal CPMODH. The Q outputs of these flip-flops 100A'-100D 'are applied to status bus 72 as bits 8-11.
The QN output is provided as well. The significance of CPMODL and CPMODH is described below with respect to FIG.

The programming of the device 20 is accomplished via the status bus 72 since the data on the bus 72, which is distributed over the internal data bus 36 and used directly, controls the operation of the various blocks of FIG. The following table shows how the various bits of status bus 72 were utilized.

Referring to FIG. 4, input data buffer 44 has eight sets of flip-flops 108A, 108A 'to 108H, 108H'. Bits 0-7 of internal data bus 36 are connected to the D inputs of each set of flip-flops. These flip-flops 108A to 108H are reset by the signal RESET1,
Flip-flops 108A'-108H 'are reset by input and signal RESET2 from clock controller 24 (FIG. 8).
The flip-flops 108A to 108H are connected to the gates 110A to 110A.
In the manner of 0H, the clock is clocked by the signal CPDATL, but the flip-flops 108A'-108H 'are gated 110A'-110H'.
Clocked by the signal CPDATH from the input and clock controller 24 (FIG. 8) in the manner described above.

Q output of flip-flops 108A to 108H is load bus 55
Appearing as bits 0-7 above, flip-flop 10
The Q outputs of 8A 'to 108H' are output on bits 8 to F on the load bus 55.
Appear as.

Referring to FIG. 5, primary counter 54 is composed of four 4-bit up counters 54A to 54D. Road bus 55
Are connected to the D0 to D3 inputs of the counter 54A, respectively. Bits 4-7 are connected to corresponding inputs of counter 54B, bits 8-11 are connected to that of counter 54C, and bits 12-15 are connected to that of counter 54D. Accordingly, the counter 54 is a 16-bit up counter that can be pre-loaded with data on the load bus 55.

The Q0N-Q3N outputs of counter 54A are the sources of bits 0-3 of counting bus 60. The Q0N-Q3N outputs of counter 54B are the sources of bits 4-7 of counting bus 60. Q0N of counter 54C
The .about.Q3N output is the source of bits 8-B of counting bus 60, while the Q0N-Q3N output of counter 54D is the source of bits C-F of counting bus 60.

Counters 54A and 54B have an input and clock controller 24.
Clocked by signal CPC1 from FIG. 9 (FIG. 9), counters 54C and 54D are clocked by signal CPC2 from a similar control.

External enable signal ENT formed by control bus 50 line
Is enabled by a logic L and supplied to the input of the ECL comparator 112. The output of the comparator 112 is supplied to the input of the driver 114. The output of the driver 114 is, in turn, the first of the NAND gates 116.
Supplied to input. The NAND gate 116 has a second input connected to the bit 9 line (SBUS8) of the status bus 72, a third input grounded, and an output connected to a first input of the OR gate 118. The second input of the OR gate 118 is connected to the output of the NAND gate 120. NAND gate 120 is 2
Inputs are grounded and the third input is SBUS8 opposite logic
Connected to S8N. Therefore, SBUS8N is logical L or SBU
When S8 and ENT are logic low, the output of OR gate 118 will be logic high, thus providing an actuation signal to countable input CE of counter 54A. Thereafter, the counter 54A counts up in response to the clock pulse CPC1 to allow individual testing of the counter 54A without interaction with other counters. For example, ENT indicates that the preferred count is counter 5
After a check to determine if it is contained within 4A is performed by the microcomputer, counter 54A may be counted for a predetermined period of CPC1 pulses.

When the counter 54A has the count value of 15, the top count output TC becomes logic H, and the TCN output connected to the input of the NAND gate 122 becomes logic L. This NAND gate 122
The second input is grounded and the third input is SBUS9, the status bus 7
The output is connected to one input of the OR gate 124. The second input of the OR gate 124 is connected to the output of the NAND gate 126. The NAND gate 126 has two inputs grounded, but a third input connected to SBUS9N. The output of the OR gate 124 is connected to the countable input CE of the counter 54B. Therefore, the counter 54B
Means that SBUS9N is at logic L or the counter 54A indicates a full count, the TCN output of the counter 54A is at logic L,
Counts the pulse of CPC1 when becomes a logical L. This allows testing of the counter 54B individually or in conjunction with the counter 54A.

Bit 11 of the status bus 72, SBUSA, is the NAND gate 128
Is connected to one input. This gate 128 is
Inputs are connected to the TCN output of each counter 54A and 54B. The output of the NAND gate 128 is connected to the input of the OR gate 130. The other input of OR gate 130 has NAND gate 1
32 outputs are connected. This NAND gate 132
Inputs are grounded, but a third input is connected to SBUSAN. The output of OR gate 130 is connected to the countable input of counter 54C. Thus, when SBUSAN is at logic L, or when the TCN outputs of counters 54A and 54B and SBUSA are all at logic L, counter 54C may be tested by counting the pulses of CPC2.

Of course, the TCN output of counters 54A and 54B is
4 are supplied to two inputs. This NOR gate 134
The other two inputs are grounded and the output is a NAND gate 136
Is connected to one input. The NAND gate 136 has the second input connected to the TCN output of the counter 54C, and the third input connected to the third input.
SBUSB, the bit 12 line of status bus 72 is connected,
The output is connected to the input of OR gate 138. The output of the NAND gate 140 is connected to the other input of the OR gate 138. NAND gate 140 has two inputs grounded, but a third input connected to SBUSBN. On the other hand, the output of the OR gate 138 is connected to the countable input CE of the counter 54D. Therefore, the counter 5D is such that SBUSBN is L,
Alternatively, when the TCN output of the counters 54A, 54B and 54C and SBUSB are all L, the pulses of CPC2 are counted. Thus, counter 54D can be tested individually or in conjunction with counters 54A, 54B and 54C.

The test arrangement described above allows full testing of the counter 54 with 65 clock pulses.

Counter 54A has Q1N, Q2N and Q3N outputs with AND gates
Connected to inputs of three inversions of 142, Q0N output is OR gate
Connected to one input of 144. The other two inputs of the OR gate 144 are grounded. Therefore, the NAND gate 142
Becomes H when the counter 54A has a count value of 14 or has a count value one less than the top count.

The inverted output YN of the NAND gate 142 is connected to the input of the inverted OR gate 146. The OR gate 146 has the other three inputs connected to the TCN outputs of the counters 54B, 54C and 54D. Accordingly, the inverted output TCNTL1 of the OR gate 146 indicates that the counter 54A has a count value of 14, and the counters 54B, 54C, and 54D
Is H when is a count value of 15. This TCNTL1 is an internal pre-top count signal that indicates to other parts of the device 20 that the counter 54 is one step before the top count state. This TCNTL1 is connected to one input of the OR gate 148. OR gate 148 has its other input grounded and its output connected to the output cell or input of driver 150.
This driver 150 forms a pre-top count output PRETC outside the device 20 when TCNTL1 transitions from L to H.

The TCN output of the counters 54A-54D is
154 inputs. The inverted output of OR gate 152 is
It becomes H only when all the counters 54A to 54D reach the top count of 15, and is connected to the input of the OR gate 156. This OR gate 156 has its other input grounded and its output connected to a driver 158 which forms the external output TC1 of the device 20. Of course, the output of the OR gate 152 is connected to one input of the OR gate 160. The other input of the OR gate 160 is grounded, and the inverted output is connected to the input of the driver 162. This driver 162 produces an L output when the counter 54 is at the top count.

Of course, the output of the OR gate 152 is
Can be supplied to any part inside. Furthermore, this output TCNT
Is applied to the two-to-one switch 164 as the output I0. The output of switch 164 is connected to the D input of flip-flop 166. The flip-flop 166 has a Q output connected to I1 and a selection input S1 of the switch 164, and has an O output connected to a clock input.
The output of the R gate 168 is connected. This OR gate 168
Has one input grounded, while the other input is connected to CPC2. The flip-flop 166 becomes H at a standstill, and the switch 164 causes the D input of the flip-flop 166 to be at a logic H.

The clock pulse applied to the OR gate 168 changes the state of the Q output of the flip-flop 166.
Whenever the output of gate 152 goes high, there will be another logic high signal applied to the D input of flip-flop 166 by way of switch 164. Only when the output of the OR gate 152 is L, when the clock pulse CPC2 is applied to the OR gate 168,
A logic L signal is provided to the D input of flip-flop 166 by way of switch 164. This causes the Q output of flip-flop 166 to go to the L state, thus forming a count end output EOCFF in the first clock pulse CPC2 after reaching the top count.

Of course, the output of the flip-flop 166 is connected to one input of the OR gate 170. The OR gate 170 has the other input grounded and the inverted output connected to the output cell or driver 172. When the Q output of flip-flop 166 goes from H to L, an output EOC is formed external to device 20 when the end of the counting state occurs.

The output of OR gate 154 is connected to one input of NAND gate 174. This NAND gate 174 has its other input grounded and its third input connected to the bit 5 line of status bus 72, ie, SBUS4.
Are connected, and the output is connected to one input of the OR gate 176. The other input of OR gate 176 is connected to the output of NAND gate 178. The NAND gate 178 has a first input grounded, a second input connected to SBUS4N, and a third input connected to the input and line EXLD from the clock controller 24 (FIG. 9).
It is connected to the.

The output of OR gate 176 is connected to the preloadable inputs of counters 54A-54D. This output is output when the counter 54 is at the top count and SBUS4 is low, or
When both N and EXLD are L, the state becomes H state. When one of these two status-enabled sets occurs, the data on load bus 55 is loaded into counters 54A-54D. Thereafter, the optimal clock pulse causes the counter 54 to count up from its count value.

Input signal RESET8 resets counters 54A and 54B. Another input signal RESET9 resets counters 54C and 54D. These signals are generated in the input and clock controller 24 (FIG. 8).

Referring to FIG. 6, data from counter 54 corresponding to bits 0-B of count bus 60 is provided to the D inputs of a series of flip-flops 180A-180L of pointer latch 62.
The Q outputs of these flip-flops 180A to 180L are connected to bits 0 to B of the latch bus 64.

The external trigger is connected by a line on the control bus 50 to the ECL comparator 182 of the external trigger control 68 (FIG. 6). The output of the comparator 182 is sequentially connected to the driver 184. The non-inverting output of the driver 184 is connected to a first input of a NAND gate 186. The NAND gate 186 has a second input connected to SBUS5N and a third input connected to SBUS6N as an external trigger enable signal.

The output of the NAND gate 186 is connected to one input of the OR gate 188. The other input of OR gate 188 has NAND gate 1
90 outputs are connected. The NAND gate 190 has a first input connected to the inverted output of the driver 184, and a second input connected to SBUS5.
And SBUS6N. Therefore, the output of OR gate 188 is SBUS6N, the non-inverted output of driver 184 and SB
When all the US5Ns become L, it becomes H. These states are:
It shows that it is triggered by the negative slope of the signal applied to the comparator 182. Of course, the output of OR gate 188 is SBUS6
N, H when the inverted output of the driver 184 and SBUS5 are all L. These states indicate that they are triggered by the positive slope of the signal applied to comparator 182.

The output of OR gate 188 is provided to one input of OR gate 192. This OR gate 192 has its other input grounded and its output clocking flip-flop 194. The D input of this flip-flop 194 is connected to SBUS6.
Therefore, when the external start enable signal is formed by making SBUS6N become a logic L, SBUS6 turns on the Q of the flip-flop 194 when the external signal applied to the comparator 182 changes state.
It forms a logic H signal clocked synchronously with the output.

The Q output of flip-flop 194 is
Is applied to the D input. This flip-flop 196
Is connected to the output of OR gate 198. The OR gate 198 has a first input grounded and a second input connected to clock CPC1 by line 70 (FIG. 1). This clock is used by the primary counter 54 and is generated from the input and clock controller 24 (FIG. 9). Accordingly, flip-flop 196 is synchronously clocked by a pulse on CPC1 that occurs after the Q output of flip-flop 194 goes high. Thereafter, the Q output state TRIGFF of flip-flop 196 is synchronized with the pulse of CPC1 immediately after the occurrence of the external trigger, and indicates the generated external trigger of the selected slope.

The QN output of flip-flop 196 is connected to the input of OR gate 198. This OR gate 198 has another input grounded and an output connected to the input of the driver 200. The driver 200 has sufficient fan-out capability so that its inverted output can drive each first input of a series of OR gates 202A-L through line 66. These OR gates
Each second input of 202A to 202L is grounded. Thus, as described above, the outputs of OR gates 202A-L clock the data on count bus 60 into latch bus 64.

A reset signal RESET3 from the input and clock controller 24 (FIG. 8) resets the flip-flops 180A-180L.

In some gate array, it is difficult to obtain the properties and performance to form a preset 16-bit counter that can be counted on 100 MHz _Z, has become sometimes impossible. The use of a prescaler 49 programmed in the control register 46 eliminates this difficulty. Primary counter 54 may be operated at a lower count rate but, prescaler 49 is operated in 100 MHz _Z.

7A and 7B, control register 46 comprises flip-flops 204A-204D each having a D input connected to internal data bus 36, bits 0-3. These flip-flops 204A to 204D
And is clocked by the signal CPPRE from the input and clock controller 24 (FIG. 8) by the method of the OR gates 206A-206D. Flip-flops 204A-20
4D has Q outputs of bits 0 to 0 of the programming bus 45, respectively.
The QN output is connected to the input of each of the inverting OR gates 208A to 208D. A 4-bit presettable binary counter of a type known to those skilled in the art is an OR gate 208A-
208D, 210A to 210D, 212A to 212C, 214A and 214B, OR connection gates 216A to 216D, and flip-flops 218A to 218D. This array is designated for high speed counting. Flip-flops 218A-218D are OR gates 220A-22
By the method of 0D, it is clocked at 100 MHz _Z system clock CP100 (Figure 9). The QN output of flip-flops 204A to 204D of control register 46 is flip-flop 218A
Forms a preset input for ~ 218D. Accordingly, the prescaler 49 can generate a time reference having a predetermined width depending on the binary number loaded into the control register 46. The prescaler 49 functions as a division number by an N counter, where N is 1 + complement of a binary number in the control register 46.

The QN outputs of flip-flops 218C and 218D are designated as CNT1N and CNT0N (FIG. 7B) and are provided as inputs to OR gates 222 and 224 (FIG. 7A). Of course, the QN outputs of the flip-flops 218A and 218B are also inverted OR gates 222.
And 224 as inputs. Flip-flop 218
When the QN outputs of A to 218D are all L, prescaler 4
9 is a top count, the inverted output of the inverted OR gate 222 is H, and forms a signal COUNTN. The output of OR gate 224 is low, forming signal LOADN. This COUNTN
Is supplied to one input of gate 210C and one input of gate 210D, while LOADN is connected to the second input of gate 210C and gate 208D.
(Figure 7B). COUNTN or LOADN is
Prescaler 49 used as time reference or clock
Is the output of The occurrence of COUNTN is an event that causes the prescaler 49 to load the number stored in the control register 46.

The flip-flops 218A to 218D are reset by the signal RESET6 of the input and clock controller 24.

In reference of 100 MHz _Z, capable of generating a pulse having a time base of 10 to 160 nanoseconds prescaler 49 is increased by 10 nanoseconds (increment). However, prescaler 49
The output of, as described below, may be supplied to the input of the primary counter 54 to generate a time reference of 20 nano-least 20 milliseconds of increase or decrease (2 ¹⁶ × 160 nanoseconds) every 20 nanoseconds .

The input control of the input and clock controller 24 is shown in FIG. A reference address specifying various input / output ports communicating with the microcomputer at a predetermined time is decoded by a method known in the art. When the device 20 of the present invention is selected, the microcomputer supplies a logic low level to the external chip select input CSN in the manner of the control bus 50. Receiver 226 converts the TTL level to an ECL level and has an output connected to the input of driver 228. Driver 2
The non-inverting output of 28 is connected to one input of OR gate 230. The output of this OR gate 230 is connected to the input of a tri-state capable driver 232. The driver 232 outputs
The output enable signal OUTEN is used to enable the drivers 94A-94H (FIGS. 2A, 2B, 2C and 2D).

Of course, the control bus 50 supplies the read signal RDN to the receiver 234, which in turn drives the driver 236. The output of the driver 236 is connected to the second input of the OR gate 230. Therefore, when RDN is logic H and OUTEN is H,
As the drivers 94A-94H are required to perform a write operation, immediately by the method of the internal data bus 36, the data on the bidirectional tristate data bus 30 is written from the microcomputer to the registers of the device 20. prohibited.

In a read operation, i.e., supplying data to the microcomputer from one of the registers of the device 20, RDN
Is a logic L, but the signal WRN supplied from the microcomputer to the receiver 238 by the line of the control bus 50 is a logic H. The output of the receiver 238 is connected to the input of the driver 240. The output of driver 240 is applied to each gate 242 and 244
Is connected to one input. These gates are logic equivalent to an AND gate having an inverting input and non-inverting and inverting outputs. The output of driver 228 is connected to a second input of each gate 242 and 244. The third inputs of these gates 242 and 244 are each grounded. The gate 242 has a fourth input connected to the internal address line IA2, and a non-inverted output connected to the invertable input of the decoder 246. Gate 2
44 has a fourth input connected to the internal address line IA2N,
The inverted output is connected to a possible input of the decoder 248.
Which output of each of the decoders 246 and 248 becomes logic H
Determined by internal address signals IA0 and IA1, these signals are connected to the A and B inputs of both decoders 246 and 248.

Assuming that the chip select input CSN goes to logic L, WRN goes to logic L, and RDN goes to logic H, gates 242 and 24
4 and the above described arrangement of decoders 246 and 248 generate outputs in accordance with the supplied inputs, forming the operations described below. These operations are considered write operations.

Microcomputer software of all registers
Order reset is achieved when the Y2 output of decoder 248 is applied to each first input of OR gates 250A-250H, as described above. Each output of these OR gates 250A-250H is connected to the input of a driver 252A-252H whose output forms RESET1-SESET6, RESET8 and RESET9.

Microcomputer of all programmable registers
Software order reset is achieved when the Y3 output of decoder 248 is applied to each second input of OR gates 250C, 250F, 250G and 250H, as described above. On the other hand, OR gates 250A, 250B, 250D and 250E are grounded. Therefore, the logic H is applied only to RESET3, RESET6, RESET8 and RESET9, and only the pointer latch 62, the prescaler 49 and the primary counter 54 are reset. The registers having the values to be loaded, that is, the input data buffer 44, the control register 46, and the instruction buffer 42 are not affected, and the values loaded in the respective registers are held for the next operation.

Assuming that CSN is logic L, RDN is logic L, and WDN is logic H, address bits A0, A1, A2 used internally as IA0, IA1, IA2 control switch 26. Thus, data from the address bus 22, the counting bus 60, the latch bus 64, and the status bus 72 are loaded into the internal data bus 36. These operations are considered reading operations as described below.

Preferably, when power is first applied to the device 20 or associated microcomputer, all registers are cleared. An external clear input CLEAR is provided to the receiver 254 via the control bus 50 line. The output of the receiver 254 is connected to the driver 256. The inverted output of the driver 256 is connected to the third inputs of the OR gates 250A to 250H.
Therefore, when CLEAR is at logic L, all registers are reset.

With reference to FIG. 9, the ECL clock CPECL or its inverted clock CPECLN is supplied to the input and the clock control unit of the clock controller 24 by the line of the control bus 50.
Receiver 258 receives CPECL and provides an output to the non-inverting input of driver 260. The receiver 262 receives CPECLN and supplies an output to the inverting input of the driver 260. This driver has its output connected to the B input of NAND gate 264. The NAND gate 264 has an A input connected to SBUS1 and an output connected to an input of the driver 266. Driver 2
The output of 66, appeared clock 100 MHz _Z, if SBUS1 is if a logical H, generates an output CP100 that is used as an output of the prescaler 49.

Terminal output EOCFF of counting flip-flop 166 (FIG. 5)
Are supplied to the A input of the AND gate 268. Of course, this EOCFF is supplied to the first input of the OR gate 270. The OR gate 270 has a second input grounded and an output connected to the output cell or input of the driver 272. This driver 2
The output of 72 forms an EOCN outside device 20.

The B input of AND gate 268 is grounded. When the counters 54A to 54D of the primary counter 54 reach the end of the counting state, a logical H output is generated by the AND gate 268. The output of this AND gate 268 is connected to a first input of an AND gate 274 having three inverting inputs. This AND gate 274
Has a second input connected to SBUS1N and a third input connected to the inverted output of AND gate 276. AND gate 276
Both inputs are prescaler 49 top count outputs COUN
Connected to TN. Thus, AND gate 274 forms a logic high output on OR gate 278 when prescaler 49 is not in top count, AND gate 268 is low, and SBUS1N is low. This last state is the primary counter
A prescaler 49 is used to form the clock input for 54.

The second input of the OR gate 278 has A having three inverting inputs.
The output of the ND gate 280 is connected. AND gate 280
Has a first input grounded, a second input connected to the inverted output of the driver 260, and a third input connected to SBUS1.

The output of OR gate 278 is connected to one input of each of OR gates 282 and 284. Each of the OR gates 282 and 284 has its second input connected to the output of the OR gate 286. This OR
One input of gate 286 is 50M along the line of control bus 50
Receiving a TTL clock pulse CPTTL frequency H _Z TTL / EC
Driven by L driver.

These OR gates 282 and 284 are connected to the third input by the decoder 24.
8 (FIG. 8) are connected to the inputs of drivers 290 and 292 which generate clock signals CPC1 and CPC2, respectively, used in primary counter 54.

The inputs to gates 268, 276, 280, 278 and 274 determine whether the input clock reaches primary counter 54 or prescaler 49.

When SBUS1N is L, the top count of prescaler 49 appears as an input to primary counter 54.

Gates 282 and 284 are connected to the clock, CPTTL or CPB
One clock selected from the group consisting of IT is allowed to be selected.

In applications where it is necessary to generate a time reference, the top count TCNT of the primary counter 54 may be used.
This TCNT is formed at the I0 input of the switch 294. CPC1 is connected to the I1 input. Selector input S1 of switch 294
Is connected to SBUS2. When SBUS2 is H
The selection is performed as previously described and the TCNT is switched
Appears in the output of 294. SBUS2 appears in the output of the clock signal output or 100 MHz _Z is switcher 294 of the prescaler 49 when a L. The non-inverted output of switch 294 is converted to an output cell or driver 296. The output of this driver 296 can be provided outside the device 20 as an ECL nominal clock output CPOUT1.

The inverted output of the switch 294 is supplied to one input of an OR gate 298. This OR gate 298 has a second input grounded,
The output is clocking flip-flop 300. The QN output of this flip-flop 300 is connected to the D input to form a symmetric output waveform at half the normally asymmetric CPOUT1 frequency and is reset by RESET8.

The Q output of the flip-flop 300 is connected to the first input of the OR gate 302. The OR gate 302 has a second input grounded and an inverted output supplied to an output cell or driver 304 that forms an ECL symmetric clock output CPOUT2 external to the device 20.

On the other hand, the QN output of the flip-flop 300 is connected to the first input of the OR gate 306. This OR gate 306
TTL output cell or driver 308 whose input is grounded and whose inverted output forms a TTL symmetric clock output CPOUT3 external to device 20.
Is supplied to

The control bus 50 has an additional two lines LAOD1 which are used to supply a signal which is intended to preload the counter 54.
And have LAOD2. LAOD1 is TTL / ECL conversion driver 310
This is the TTL signal supplied to This driver 310 has an OR
One input of the gate 312 is connected. This OR gate 312
The other input is grounded, and the inverted output is provided to the input of a gate 314 that serves as an AND gate with an inverted input and an inverted output.

LAOD2 is the ECL signal connected to the input of ECL comparator 316. The output of the comparator 316 is connected to the input of the driver 318. The driver 318 outputs the inverted output to the gate 314.
Connected to other inputs. Gate 314 has the remaining input grounded.

The inverted output of gate 314 is connected to the first input of NAND gate 320. The NAND gate 320 has a second input connected to SBUS7N, a third input grounded, and an output connected to a first input of the OR gate 322. This OR gate 322 is
The output of the NAND gate 324 is connected to the input. The NAND gate 324 has two inputs grounded, but a third input connected to SBUS0N. Inverted output EXL of OR gate 322
D is used to cause the primary counter 54 to preload data from the input data buffer 44 on the load bus 50. This occurs when SBUS0N is logic low and LAOD1 or LAOD2 and SBUS7N are logic low.

Thus, it is clear that the device 20 may be programmed with the optimal logic signal from the microcomputer to form a time reference signal, act as a counter, or directly access the address memory. In addition, the device 20
Counting and address data can be easily integrated in the microcomputer.

Referring to FIG. 10, three modules 20 according to the invention
A, 20B and 20C are used for the counter / timer 326. Ten
0MH _Z clock is formed in the module 20A, when the module 20A is programmed by a microcomputer, and an optimum time reference. Module 20
A time reference output is connected to a first input of gate 328. The second input of gate 328 is connected to the output of a conventional selector 330 of the type commonly used for counters / timers. The output of the comparator 332A supplied by the driver 334A is connected to a first input of the selector 330. The first reference voltage VREF1 is connected to the comparator 332A. This comparator may have some hysteresis.

A signal indicative of the first event is applied to the input CHA of a microcomputer-programmable attenuator 336A. The output of the attenuator 336A is connected to the input of the driver 334A. The arrangement and operation of comparator 332A, driver 334A and attenuator 336A are well known in the art.

The comparator 332B, the driver 334B, and the attenuator 336B have the input CHB.
For forming other channels. That is, the comparator 332B
Has a reference voltage VREF2 connected to the input and an output
It is connected to the.

The output of gate 328 is connected to module 20B constructed in accordance with the present invention. This module 20B serves as a count accumulator for counting gated through gate 328. If the count is sufficient to fill the primary counter 54 and cause an overflow, a second module 20C is configured to count the top count output of module 20B. The counting data from the modules 20B and 20C is supplied to the microcomputer. If both modules 20B and 20C are used, a counter / timer with a 32-bit accumulator is formed.

FIG. 11 shows how three modules 20D, 20E and 20E according to the invention form an arbitrary function generator 338, controlled by a microcomputer. 100MH
A stable frequency source, such as _Z , is connected to the input of module 20D, which is programmed by a microcomputer to act as a time reference generator. The timing output of the module 20D is programmed to supply a signal to the module 20D when a predetermined number of required repetitions of an arbitrary function occurs, and is supplied to a module 20E configured as a burst counter. Of course, the output of module 20D is also provided to module 20F programmed for memory address control. Module 20F controls a stimulus memory 340 loaded by a computer that supplies stimulus data to form an arbitrary function.

When an external trigger is provided to module 20F, reference address 342 in stimulus memory 340 is accessed. This reference address 342 has bits that are used to form a single indication that reference address 342 has been accessed. For example, other addresses in the stimulus memory 340 may have a corresponding bit of logic zero or this bit may have a logic one. When this logical 1 bit is detected, a synchronization signal indicating the start of an arbitrary function is output to the buffer 34.
Generated from 4. The module 20F is stepped through the locations in the stimulus memory 340, which in turn supplies the data at each location to the DA converter 346 in successive pulses from the time reference generator (module 20D) to the memory address control (module 20F). . The output of the DA converter 346 is supplied to a buffer 348 having sufficient output drive capability to form a signal used for detection or other purposes. When the function generated by the data in the stimulus memory 340 repeats the number of times programmed into the burst counter (module 20E), a reset of the microcomputer will occur and operation will continue until a new trigger signal is received at module 20F. Has been discontinued.

FIG. 12 shows how three modules according to the present invention are interconnected to form a digitizer 350 for storing a digital indication of an analog signal. Preferably the 100 MHz _Z clock is supplied to the input of the first module 20G constituted as a time base generator. This time reference output CPOUT is supplied to a second module 20H used as a memory address control. Of course, the third module where CPOUT acts as a counting transport sample
Supplied to 20I.

The input signal to be digitized is provided to an input terminal having a standard 50 ohm termination resistor 352 grounded at one end.
Programmable attenuator 354 adjusts the signal level to be suitable as an input to buffer 356. The sample and hold circuit 358 samples the output of the buffer 356, and periodically holds this value for conversion by the DA converter 360. The output of the DA converter 360 is supplied as a digital input to the cyclic memory file 362.

The synchronization pulse is provided to buffer 364 as an input. The output of this buffer 356 is supplied to a driver 366 with hysteresis to prevent undesired multiple triggers. The output of driver 366 is provided to memory address control (module 20H) and counting transport samples (module 20I).

Module 20H includes a primary counter 54 corresponding to an address in memory 362 accessed by module 20H.
Is programmed by a microcomputer such that it is on counting bus 60. When a synchronization signal is received, this value is stored in pointer latch 62 and forms a reference corresponding to a location in memory 362.
Of course, the output of the driver 366 is provided to the ENT input of the counting transport sample (module 201) which serves as a countable signal. This counting transport sample (module
20I) is programmed by the microcomputer to count a predetermined number of time reference signals from module 20G corresponding to the desired number of locations in memory 362.
After counting the predetermined number, module 20I
The end of the counting EOC pulse for 0H can be formed to prevent additional locations in memory 362 from being addressed, so that in memory 362 the desired data can be held in digital form.

The values programmed into the counting transport samples (module 20I) by the microcomputer are stored in the circular memory 362.
Is updated on a regular basis with the new data written on the old data, at a rate determined by the time reference formed in module 20H by module 20G, so that the digitized analog for a predetermined period before and after the occurrence of synchronization It is understood that it can be used to form signal storage.

An additional module, not shown, according to the present invention can form a time delay after the occurrence of the synchronization pulse before the external trigger and countable signal are provided to modules 20H and 20I, respectively.

Referring to FIG. 13, the digital word generator 368 is configured using the time base generator module 20J and the memory address control module 20K according to the present invention. Preferably the output of a stable oscillator of 100 MHz _Z is supplied to the module 20 J. According to the output of module 20J, module 20K
Are used to address the stimulus memory 370, response memory 372, tri-state control memory 374, and expected response memory 376.

The stimulus memory 370 is a memory of N bits × M bits, where N is an output indicated by the number of bits or a predetermined time, and M is a number of various outputs where M exists. Module 20K
When accessed by the stimulus memory 370, the data at one of the M positions is provided to an N-bit driver 378, and the optimal enable signal is output to the tri-state control memory 37.
4 is placed on the bidirectional tri-state data bus 380 when received.

The data bus 380 supplies data to a unit under inspection (not shown). Data is transferred from the unit under inspection to the bus
380 (or, if the switch 384 is open, return from the optimal separation bus 382) and feed the receiver 386.
The outputs of these receivers 386 provide data back to the response memory 372 under the control of the module 20K. Digital comparator 388 compares the data supplied to response memory 372 with data from a corresponding address location in expected response memory 376. If the response from the unit under test did not correspond to the expected response, comparator 388 forms an output that is used, for example, to stop the test. Of course, the comparator 388 may be formed of an optimum circuit that indicates one of the bits of the data returned from the unit under test is not logic H or logic L, but indicates a certain level therebetween.

From the above, it is clear that the device of the present invention has widespread applicability of test equipment as a reference time generator, event accumulator, or memory address controller.

Claims (16)

(57) [Claims] A clock input means for receiving a clock input signal; a computer input means for providing an input from a computer; and at least one output processing and processing at least one of the clock input signal and the input from the computer. A control means for controlling the processing means according to further inputs from the computer to determine the output to be generated; and selecting the at least one output for use outside the apparatus. A programmable device comprising: an output selection unit. 2. The apparatus of claim 1, wherein said output selection means selects said at least one output in response to an additional input from said computer. 3. A counter (5) for counting pulses of the clock input signal.
3. Apparatus according to claim 1 or 2, comprising: (4) and means (55) for preloading a value to said counter (54) according to input from said computer. 4. The processing means includes a counter (54); the computer input means; bidirectional data means (30) for transmitting and receiving data; and an input for storing data to be loaded into the counter (54). Apparatus according to any of claims 1 to 3, comprising a data buffer (44) and an instruction buffer (42) for storing further inputs from the computer. 5. Apparatus according to claim 1, wherein said output selection means includes at least one multiplexer having output circuit means for directly addressing a memory. 6. The processing means includes a counter (54) responsive to the clock input signal, and a register (62) for storing a count value in the counter (54), wherein the register (62) is Output to the output selection means,
6. Apparatus according to claim 1, wherein said counter provides an output to said output selection means. 7. A counter (54) when a signal is applied.
7. The apparatus according to claim 6, further comprising external input means (68) for storing said count value in said register (62). 8. Clock input means for receiving a clock input signal; computer input means for providing an input from a computer; an address input (22) for supplying an address provided by said computer to said apparatus; Computer input means combining control input means (50) for supplying a control input supplied by a computer to the apparatus; and data transmission means (30) for inputting data to the apparatus and outputting data from the apparatus. A programmable device comprising: processing means for processing at least one of the clock input signal, the address, and the data according to the control input to form at least one output signal. 9. An instruction buffer (42) for receiving and storing program data for programming the processing means from the data transmission means, and input data for receiving and storing data from the data transmission means. An apparatus as claimed in claim 8, including a buffer (44). 10. The input data buffer (44) includes a first group of flip-flops clocked in response to a first control input, and a second group of flip-flops clocked in response to a second control input. 10. The apparatus of claim 9, comprising a group of flip-flops. 11. The processing means comprises: counter means for counting pulses of the clock input signal; and a latch (62) for storing a count value in the counter means; 11. Apparatus according to claim 8, wherein data is used for preloading said counter means. 12. An apparatus according to claim 8, further comprising output selection means for selecting one of said at least one output signal formed by said processing means as an output by said data transmission means. An apparatus according to any one of the above. 13. An internal data bus (3) for transmitting data transmitted by said data transmission means inside the apparatus.
13. The apparatus according to claim 11, further comprising: 6); and loading means for loading the data stored in the input data buffer into the counter means. 14. A prescaler (49) for receiving and dividing the clock signal to generate a divided clock signal, and a primary counter (49) for counting the divided clock signal. 54) and the claim
An apparatus according to any of paragraphs 11 to 13. 15. The apparatus according to claim 14, wherein said load means preloads data in said input data buffer to said primary counter. 16. A control register (46) for receiving and storing counter control data on said internal data bus (36); an additional load means for supplying said counter control data to said prescaler; 16. The apparatus of claim 14 or claim 15, further comprising: means for supplying said control data as an input to said output selection means for transmission.