JP2592238B2 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistorInfo
- Publication number
- JP2592238B2 JP2592238B2 JP61147381A JP14738186A JP2592238B2 JP 2592238 B2 JP2592238 B2 JP 2592238B2 JP 61147381 A JP61147381 A JP 61147381A JP 14738186 A JP14738186 A JP 14738186A JP 2592238 B2 JP2592238 B2 JP 2592238B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- cvd
- film
- channel semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims description 56
- 239000000758 substrate Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims description 19
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 claims description 18
- 229910052739 hydrogen Inorganic materials 0.000 claims description 15
- 239000001257 hydrogen Substances 0.000 claims description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 10
- 229910000077 silane Inorganic materials 0.000 claims description 10
- 238000009832 plasma treatment Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 238000003795 desorption Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、液晶パネルのドライバー等に用いる経時
変化の少ない薄膜トランジスタの製造方法に関するもの
である。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor which is used for a driver of a liquid crystal panel and has little change over time.
この発明は、薄膜トランジスタのチャネル半導体膜
に、トリシラン以上の高次シランの熱CVDによるアモル
ファスシリコン膜を用いることにより、経時変化の少な
い薄膜トランジスタを製造するものである。According to the present invention, a thin film transistor with little change over time is manufactured by using an amorphous silicon film formed by thermal CVD of higher silane such as trisilane as a channel semiconductor film of the thin film transistor.
〔従来の技術〕 従来、薄膜トランジスタのチャネル半導体膜としてモ
ノシランを原料としたプラズマCVDによる水素化アモル
ファスシリコン膜が用いられてきた。これは、低温で比
較的簡単に成膜することができ、移動度の高い薄膜トラ
ンジスタが実現されている。[Prior Art] Conventionally, a hydrogenated amorphous silicon film formed by plasma CVD using monosilane as a raw material has been used as a channel semiconductor film of a thin film transistor. In this case, a film can be formed relatively easily at a low temperature, and a thin film transistor having high mobility is realized.
しかし、上記の従来例においてはバイアスを印加した
直後の比較的短時間でのオン電流の変化や、バイアスを
長時間印加した後でのしきい値電圧の変動や移動度の劣
化という問題があった。これらの劣化の原因は明らかに
されておらず実用的な安定性が得られていない。However, in the above-described conventional example, there are problems such as a change in the on-current in a relatively short time immediately after the bias is applied, a change in the threshold voltage and a deterioration in the mobility after the bias is applied for a long time. Was. The cause of these deteriorations has not been clarified, and practical stability has not been obtained.
そこで、この発明では安価なガラス基板が使用できる
低い温度で成膜でき、高い移動度で安定な動作をする薄
膜トランジスタを製造することを目的としている。Therefore, an object of the present invention is to manufacture a thin film transistor which can be formed at a low temperature at which an inexpensive glass substrate can be used, and which operates stably with high mobility.
この発明では、チャネル半導体膜として、トリシラン
以上の高次シランを原料ガスに用いた熱CVDによるアモ
ルファスシリコン膜を用い、その製造条件と膜質の関係
を明確にすることにより問題を解決した。In the present invention, the problem is solved by using an amorphous silicon film formed by thermal CVD using a higher-order silane of trisilane or higher as a source gas as a channel semiconductor film, and clarifying the relationship between the manufacturing conditions and the film quality.
トリシラン以上の高次シランの熱CVDによるアモルフ
ァスシリコン膜は荷電粒子によるダメージがなく、この
膜をチャネル半導体膜に用いると薄膜トランジスタのオ
ン電流の経時変化を小さく抑えることができる。An amorphous silicon film formed by thermal CVD of higher-order silane such as trisilane has no damage due to charged particles. When this film is used as a channel semiconductor film, a change over time in on-current of a thin film transistor can be suppressed.
まず、この発明により実現される薄膜トランジスタの
構造例を第１図（ａ）〜（ｃ）により説明する。First, a structural example of a thin film transistor realized by the present invention will be described with reference to FIGS. 1 (a) to 1 (c).
第１図（ａ）は逆スタガード型の薄膜トランジスタ
で、絶縁基板１上に蒸着、スパッタ等によるNi,W,M0等
のゲート２を形成し、その上にCVD等によるシリコン酸
化膜、シリコン窒化膜等のゲート絶縁膜３を積む。この
上に本発明のトリシラン以上の高次シランの熱CVDによ
るシリコン膜４を形成する。さらに、Ｐ形あるいはｎ形
の低抵抗半導体膜と金属膜の二層構造のソース５および
ドレイン６を形成する。各層のパターニングはフォトリ
ソグラフィ技術を用いる。In Figure 1 (a) is reverse staggered type thin film transistor, deposited on the insulating substrate 1, Ni by sputtering, W, a gate 2 such M 0, the silicon oxide film by CVD or the like thereon, a silicon nitride A gate insulating film 3 such as a film is stacked. On this, a silicon film 4 is formed by thermal CVD of a higher silane of trisilane or higher according to the present invention. Further, a source 5 and a drain 6 having a two-layer structure of a P-type or n-type low-resistance semiconductor film and a metal film are formed. The patterning of each layer uses a photolithography technique.
第１図（ｂ）はスタガード型の薄膜トランジスタで、
各層の形成は第１図（ａ）と同様である。FIG. 1B shows a staggered thin film transistor.
The formation of each layer is the same as in FIG.
第１図（ｃ）は、低抵抗シリコン基板をゲート２とし
て用いたものである。ゲート絶縁膜３はCVD等のデポジ
ション膜以外に、低抵抗シリコン基板の熱酸化膜によっ
ても形成できる。このほかの層の形成は第１図（ａ）と
同様である。FIG. 1C shows a case where a low-resistance silicon substrate is used as the gate 2. The gate insulating film 3 can be formed not only by a deposition film such as CVD but also by a thermal oxide film of a low-resistance silicon substrate. The other layers are formed in the same manner as in FIG.
次に、この発明のチャネル半導体膜の形成に用いる装
置例を第２図により説明する。Next, an example of an apparatus used for forming a channel semiconductor film of the present invention will be described with reference to FIG.
第２図において、７はチャンバーで、内部に石英板，
ガラス板，ステンレス板，シリコンウェハー等が載せら
れ（下向き等の場合には止め金具等で固定され）加熱さ
れる基板加熱手段８を有している。さらに基板加熱手段
８の近傍にガス吹出部９を形成し、ガス供給手段10とチ
ャンバー７内を排気する排気手段11がチャンバー７に接
続されている。ガス供給手段10からガス吹出部９までの
系は、ヒーター等により原料ガスの沸点（トリシランで
は53.1℃）以上の温度に保たれている。このほか、必要
に応じてチャンバー７の側面に真空ゲージ、観察窓等が
設けられている。このような装置において、基板温度を
400℃程度に加熱し、トリシラン以上の高次シランをチ
ャンバー７内に導入すると、基板上の熱分解反応によ
り、基板表面にアモルファスシリコン膜を形成すること
ができる。In FIG. 2, reference numeral 7 denotes a chamber, in which a quartz plate,
There is provided a substrate heating means 8 on which a glass plate, a stainless steel plate, a silicon wafer, or the like is mounted (in the case of a downward direction, fixed with a stopper or the like) and heated. Further, a gas blowing section 9 is formed near the substrate heating means 8, and a gas supply means 10 and an exhaust means 11 for exhausting the inside of the chamber 7 are connected to the chamber 7. The system from the gas supply means 10 to the gas outlet 9 is maintained at a temperature not lower than the boiling point of the source gas (53.1 ° C. for trisilane) by a heater or the like. In addition, a vacuum gauge, an observation window, and the like are provided on the side surface of the chamber 7 as needed. In such an apparatus, the substrate temperature
When heating to about 400 ° C. and introducing a higher silane of trisilane or higher into the chamber 7, an amorphous silicon film can be formed on the substrate surface by a thermal decomposition reaction on the substrate.
第３図は、100％トリシランを用いた熱CVDによるアモ
ルファスシリコン膜のデポジションレートのデータの一
例を示すものである。第３図で、横軸は基板温度の逆数
（1/K），縦軸はデポジションレート（Å/min）であ
り、△，□，○，◇，▽印はそれぞれ反応圧力が1,2,5,
10,12,Torrの場合である。FIG. 3 shows an example of data on the deposition rate of an amorphous silicon film formed by thermal CVD using 100% trisilane. In FIG. 3, the horizontal axis represents the reciprocal of the substrate temperature (1 / K), the vertical axis represents the deposition rate (Å / min), and Δ, □, ○, Δ, and Δ represent reaction pressures of 1,2, respectively. ,Five,
It is the case of 10,12, Torr.
第４図は100％トリシランを用いて反応圧力5Torrの場
合の光学バンドギャップと結合水素量の基板温度依存性
の一例を示したものである。基板温度が480℃以下では
光学バンドギャップは約1.65eV,結合水素量は約7.5％で
ほぼ一定である。基板温度が480℃より高い温度では光
学バンドギャップ，結合水素量ともに減少する。これよ
りトリシラン以上の熱CVDでは基板温度480℃より高い温
度で水素脱離が起こることを示している。FIG. 4 shows an example of the substrate temperature dependence of the optical band gap and the amount of bonded hydrogen when the reaction pressure is 5 Torr using 100% trisilane. When the substrate temperature is 480 ° C. or less, the optical band gap is about 1.65 eV and the amount of bonded hydrogen is about 7.5%, which is almost constant. When the substrate temperature is higher than 480 ° C., both the optical band gap and the amount of bonded hydrogen decrease. This indicates that hydrogen desorption occurs at a substrate temperature higher than 480 ° C. in thermal CVD of trisilane or higher.
第５図は、100％トリシランを用いて反応圧力5Torrの
場合の暗導電率（●印）とAM1スペクトラム60mW/cm2光
照射での光導電率（○印）の基板温度依存性を示したも
のである。光導電率は高くないが、光導電率と暗導電率
の比は３桁以上ある。また、基板温度480℃より高い温
度では、水素脱離により光導電率、暗導電率ともに低下
する。FIG. 5 shows the substrate temperature dependence of the dark conductivity (indicated by ●) and the photoconductivity (indicated by ○) when irradiated with 60 mW / cm 2 of AM1 spectrum light at a reaction pressure of 5 Torr using 100% trisilane. Things. Although the photoconductivity is not high, the ratio of photoconductivity to dark conductivity is more than three orders of magnitude. At a substrate temperature higher than 480 ° C., both photoconductivity and dark conductivity decrease due to hydrogen desorption.
以上のデポジションのデータを利用して第１図（ｃ）
の構造の薄膜トランジスタを作成し、チャネル半導体膜
の基本特性を調べた。第１図（ｃ）のゲート２は低抵抗
Ｐ型シリコン基板，ゲート絶縁膜３は前記シリコン基板
を1100℃のdryO2雰囲気中で熱酸化した約900ÅのSiO2膜
であり、その上にトリシラン以上の高次シランを用いた
熱CVDによるノンド−プアモルファスシリコン層６を形
成し、さらにn+アモルファスシリコン層とNi等の金属層
の二層より成るソース５及びドレイン６から成る薄膜ト
ランジスタである。以下薄膜トランジスタの特性の詳細
を示す。Fig. 1 (c) using the above deposition data
A thin film transistor having the above structure was fabricated, and the basic characteristics of the channel semiconductor film were examined. In FIG. 1 (c), the gate 2 is a low-resistance P-type silicon substrate, and the gate insulating film 3 is an approximately 900 ° SiO 2 film obtained by thermally oxidizing the silicon substrate in a dry O 2 atmosphere at 1100 ° C. A thin film transistor comprising a non-doped amorphous silicon layer 6 formed by thermal CVD using higher silane as described above, and a source 5 and a drain 6 comprising two layers of an n + amorphous silicon layer and a metal layer such as Ni. Hereinafter, the characteristics of the thin film transistor will be described in detail.
第６図は、第１図（ｃ）の構造の薄膜トランジスタの
しきい値電圧と電子移動度の基板温度依存性のデータの
一例を示したものである。この薄膜トランジスタはゲー
ト絶縁膜にSiO2を用い、ソース・ドレインのコンタクト
抵抗が大きいので、しきい値電圧は多少高い。電子移動
度は0.1cm2/V・Ｓと高い。基板温度480℃より高い温度
で形成した場合、しきい値電圧が高くなり電子移動度が
低下する。この原因は、第４図で示したアモルファスシ
リコン膜中の水素脱離によるものである。従って、薄膜
トランジスタの基板温度は480℃以下にする必要があ
る。FIG. 6 shows an example of data on the substrate temperature dependence of the threshold voltage and the electron mobility of the thin film transistor having the structure shown in FIG. 1 (c). Since the thin film transistor uses SiO 2 for the gate insulating film and has a large source / drain contact resistance, the threshold voltage is somewhat high. The electron mobility is as high as 0.1 cm 2 / V · S. When the substrate is formed at a temperature higher than 480 ° C., the threshold voltage increases and the electron mobility decreases. This is due to hydrogen elimination in the amorphous silicon film shown in FIG. Therefore, the substrate temperature of the thin film transistor needs to be 480 ° C. or lower.
第３図から、基板温度480℃におけるデポジションレ
ートの反応圧力依存性を示した図が第７図である。デポ
ジションレートは反応圧力のほぼ3/2乗に比例する。第
７図から分かる通り、基板温度480℃以下でデポジショ
ンを行う場合、実用的なデポジションレートとして１Å
/min以上を得るには反応圧力を0.1Torr以上にしなけれ
ばならない。FIG. 7 shows the reaction pressure dependence of the deposition rate at a substrate temperature of 480 ° C. from FIG. The deposition rate is approximately proportional to the 3/2 power of the reaction pressure. As can be seen from FIG. 7, when deposition is performed at a substrate temperature of 480 ° C. or less, a practical deposition rate of 1Å
To obtain more than / min, the reaction pressure must be more than 0.1 Torr.
チャネル半導体膜にトリシラン以上の高次シランの熱
CVD膜を用いた薄膜トランジスタはアモルファスシリコ
ン膜厚が厚くなると、ソースおよびドレインの抵抗が高
くなり、ドレイン−ソース電圧をある程度高くしない
と、チャネルとドレイン及びチャネルとソースとの間が
導通されずドレイン電流が流れない。チャネルが形成さ
れ、かつチャネルとドレイン間及びチャネルとソース間
が導通するのに必要な電圧、即ちドレイン電流が流れ始
める最小ソース・ドレイン電圧とアモルファスシリコン
膜厚の関係を示した図が第８図である。これよりアモル
ファスシリコン膜の厚さを600Å以下にするとよい。Heat of higher silanes higher than trisilane in channel semiconductor film
In a thin film transistor using a CVD film, as the amorphous silicon film thickness increases, the resistance of the source and the drain increases, and if the drain-source voltage is not increased to some extent, conduction between the channel and the drain and between the channel and the source does not occur. Does not flow. FIG. 8 is a diagram showing the relationship between the voltage required for forming a channel and conducting between the channel and the drain and between the channel and the source, that is, the minimum source / drain voltage at which the drain current starts flowing and the thickness of the amorphous silicon film. It is. Thus, the thickness of the amorphous silicon film is preferably set to 600 mm or less.
以上が、トリシラン以上の高次シランの熱CVDによる
薄膜トランジスタの基本的な構造方法であるが、次に示
す処理によりその特性をさらに向上させることができ
る。すなわち、第４図に示した通り熱CVDアモルファス
シリコン膜は結合水素量が低いので、膜形成後にその成
膜温度以下で水素プラズマ処理することにより、結合水
素量を増加させることができる。The above is the basic structure method of the thin film transistor by thermal CVD of higher order silane than trisilane. The characteristics can be further improved by the following treatment. That is, as shown in FIG. 4, since the thermal CVD amorphous silicon film has a low amount of bonded hydrogen, the amount of bonded hydrogen can be increased by performing a hydrogen plasma treatment at a film forming temperature or lower after forming the film.
第９図は、水素プラズマ処理による膜特性の向上の一
例を示したドレイン電流対ゲート電圧特性図である。図
中破線は100％トリシランを用いて、反応圧力5Torr,基
板温度430℃で作成した第５図の構造の薄膜トランジス
タである。実線はこの薄膜トランジスタを基板温度240
℃、反応圧力1Torr,高周波電力25Wの条件で１時間の水
素プラズマ処理を施したものである。水素プラズマ処理
により、ソース，ドレイン抵抗が小さくなり、移動度も
向上する。FIG. 9 is a drain current vs. gate voltage characteristic diagram showing an example of improvement of film characteristics by hydrogen plasma processing. The broken line in the figure is a thin film transistor having the structure of FIG. 5 prepared using 100% trisilane at a reaction pressure of 5 Torr and a substrate temperature of 430 ° C. The solid line shows that this thin-film transistor has a substrate temperature of 240
C., a reaction pressure of 1 Torr, and a high-frequency power of 25 W underwent hydrogen plasma treatment for 1 hour. By the hydrogen plasma treatment, the source and drain resistances are reduced, and the mobility is improved.
第１図（ａ）〜（ｃ）に示す構造の薄膜トランジスタ
のソースおよびドレインの接触抵抗を下げるために挿入
するＰ形あるいはｎ形の低抵抗半導体膜は、チャネル半
導体形成と連続させて、Ｐ形ドーパントのボロン、ｎ形
ドーパントのリンあるいはヒ素等を含むドーピングガス
をトリシラン以上の高次シランに混合させた熱CVDによ
り形成することができる。しかし、熱CVDでは、基板温
度が400℃以下では抵抗率をあまり低くできないので、
ソース及びドレインをプラズマCVD,光CVD,励起CVD等の
熱CVD以外の製造方法で、チャネル半導体膜の成膜温度
より低い温度で形成させることもできる。この場合、熱
CVDによるチャネル半導体膜の持つ特性が阻害されるこ
とは殆どない。A P-type or n-type low-resistance semiconductor film inserted to reduce the contact resistance between the source and the drain of the thin film transistor having the structure shown in FIGS. 1A to 1C is formed continuously with the formation of the channel semiconductor. It can be formed by thermal CVD in which a doping gas containing boron as a dopant and phosphorus or arsenic as an n-type dopant is mixed with higher silane such as trisilane. However, in thermal CVD, the resistivity cannot be reduced too much when the substrate temperature is 400 ° C or less.
The source and the drain can be formed at a temperature lower than the film forming temperature of the channel semiconductor film by a manufacturing method other than the thermal CVD such as plasma CVD, photo CVD, and excitation CVD. In this case, heat
The characteristics of the channel semiconductor film by CVD are hardly hindered.
第10図は、ドレイン電流の時間変化を本発明の薄膜ト
ランジスタと従来のプラズマCVDにより作成した同じ構
造の薄膜トランジスタについて比較したものである。図
中、実線が本発明による100％トリシランの反応圧力5To
rr,基板温度430℃の熱CVD試料で、破線が従来の製造方
法による熱CVDと同一のチャンバーで反応圧力0.7Torr,
基板温度300℃，高周波電力10Wの条件によるモノシラン
のプラズマCVD試料である。ドレイン電流１μＡを３時
間流した場合、従来のプラズマCVD試料では20％程度減
少するのに対し、本発明の熱CVD試料では10％以下と安
定である。FIG. 10 shows a comparison of the change over time in drain current between the thin film transistor of the present invention and a thin film transistor of the same structure formed by conventional plasma CVD. In the figure, the solid line indicates the reaction pressure of 5% of 100% trisilane according to the present invention.
rr, a thermal CVD sample with a substrate temperature of 430 ° C. The broken line is a reaction pressure of 0.7 Torr in the same chamber as the thermal CVD by the conventional manufacturing method.
This is a plasma CVD sample of monosilane under the conditions of a substrate temperature of 300 ° C and high-frequency power of 10W. When a drain current of 1 μA is applied for 3 hours, the plasma CVD sample of the present invention is reduced by about 20%, whereas the thermal CVD sample of the present invention is stable at 10% or less.
以上説明したように、この発明は薄膜トランジスタの
チャネル半導体膜にトリシラン以上の高次シランの熱CV
Dによるシリコン膜を用いることにより、移動度が高く
安定な動作を行うことができる薄膜トランジスタを実現
した。As described above, the present invention relates to the thermal CV of higher silane than trisilane in the channel semiconductor film of the thin film transistor.
By using a silicon film made of D, a thin film transistor having high mobility and stable operation has been realized.
また、この発明の薄膜トランジスタは光照射時のコン
ダクタンスが低いことから、遮光膜の不要な液晶パネル
ドライバーとして有効である。Further, the thin film transistor of the present invention has a low conductance at the time of light irradiation, and thus is effective as a liquid crystal panel driver which does not require a light shielding film.
さらに、この発明はプラズマ等の荷電粒子によるダメ
ージがなく、低温で製造できるので、LSI等と組合せ
た、三次元ICや高感度光センサーIC等に利用するのに有
効である。Further, since the present invention can be manufactured at low temperature without damage by charged particles such as plasma, it is effective for use in a three-dimensional IC, a high-sensitivity optical sensor IC, or the like combined with an LSI.
第１図（ａ）〜（ｃ）はこの発明が適用される薄膜トラ
ンジスタの断面図の一例、第２図はこの発明の製造に用
いる装置の断面図の一例、第３図はこの発明による100
％トリシランを用いた熱CVDにおけるデポジションレー
トの基板温度依存性を示す図、第４図は光学バンドギャ
ップと結合水素量の基板温度依存性を示す図、第５図は
導電率の基板温度依存性を示す図、第６図は薄膜トラン
ジスタのしきい値電圧と電子移動度の基板温度依存性を
示す図、第７図は基板温度480℃におけるデポジション
レートの反応圧力依存性を示す図、第８図はチャネル半
導体のシリコン膜厚と最少ドレイン・ソース電圧の関係
を示す図、第９図は水素プラズマ処理の効果を示す図、
第10図はドレイン電流の時間変化を示す図である。 図中、１は絶縁基板、２はゲート、３はゲート絶縁膜、
４はシリコン膜、５はソース、６はドレイン、６はチャ
ンバー、８は基板加熱手段、９はガス吹出部,10はガス
供給手段である。1 (a) to 1 (c) are an example of a sectional view of a thin film transistor to which the present invention is applied, FIG. 2 is an example of a sectional view of an apparatus used for manufacturing the present invention, and FIG.
Fig. 4 shows the substrate temperature dependence of the deposition rate in thermal CVD using% trisilane, Fig. 4 shows the substrate temperature dependence of the optical band gap and the amount of bonded hydrogen, and Fig. 5 shows the substrate temperature dependence of the conductivity. FIG. 6 is a diagram showing the dependence of the threshold voltage and electron mobility of a thin film transistor on the substrate temperature, FIG. 7 is a diagram showing the reaction pressure dependence of the deposition rate at a substrate temperature of 480 ° C. FIG. 8 is a diagram showing the relationship between the silicon film thickness of the channel semiconductor and the minimum drain / source voltage, FIG. 9 is a diagram showing the effect of the hydrogen plasma treatment,
FIG. 10 is a diagram showing a time change of the drain current. In the figure, 1 is an insulating substrate, 2 is a gate, 3 is a gate insulating film,
4 is a silicon film, 5 is a source, 6 is a drain, 6 is a chamber, 8 is a substrate heating means, 9 is a gas blowing part, and 10 is a gas supply means.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山中 光之 茨城県新治郡桜村梅園１丁目１番４号 工業技術院電子技術総合研究所内 (72)発明者 梅村 光雄 群馬県安中市磯部２丁目13番１号 信越 化学工業株式会社シリコーン電子材料技 術研究所内 (72)発明者 岡崎 智 群馬県安中市磯部２丁目13番１号 信越 化学工業株式会社シリコーン電子材料技 術研究所内 (72)発明者 高田 量司 東京都江東区亀戸６丁目31番１号 セイ コー電子工業株式会社内 (72)発明者 神谷 昌明 東京都江東区亀戸６丁目31番１号 セイ コー電子工業株式会社内 合議体 審判長 倉地 保幸 審判官 相田 義明 審判官 真々田 忠博 (56)参考文献 特開 昭56−135968（ＪＰ，Ａ) 特開 昭59−55441（ＪＰ，Ａ) 特開 昭59−78919（ＪＰ，Ａ) 特開 昭58−171859（ＪＰ，Ａ) ────────────────────────────────────────────────── ─── Continuing on the front page (72) Mitsuyuki Yamanaka 1-4-1 Sakuramura Umezono, Shinji-gun, Ibaraki Pref. Inside the Research Institute of Electronics and Technology (72) Mitsuo Umemura 2-Chome Isobe, Annaka-shi, Gunma 13-1 Shin-Etsu Chemical Co., Ltd. Silicone Electronic Materials Technology Laboratory (72) Inventor Satoshi Okazaki 2-1-1 Isobe, Annaka-shi, Gunma Prefecture Shin-Etsu Chemical Co., Ltd. Silicone Electronics Materials Technology Laboratory (72) Inventor Kazushi Takada 6-31-1, Kameido, Koto-ku, Tokyo Inside Seiko Electronic Industries Co., Ltd. (72) Inventor Masaaki Kamiya 6-31-1, Kameido, Koto-ku, Tokyo Judge Yasuyuki Kurachi Judge Yoshiaki Aida Judge Tadahiro Sanada (56) References JP-A-56-135968 (JP, A) JP-A-59- 55441 (JP, A) JP-A-59-78919 (JP, A) JP-A-58-171859 (JP, A)
Claims (4)
導体膜、ソース、ドレインなどから成る薄膜トランジス
タにおいて、他のガスが添加されていないトリシラン
（Si3H8）以上の高次シランの熱CVDにより、成膜温度を
480℃以下とすると共に、反応圧力を0.1Torr以上の減圧
下として、チャネル半導体膜を形成することを特徴とす
る薄膜トランジスタの製造方法。In a thin film transistor comprising a substrate, a gate, a gate insulating film, a channel semiconductor film, a source, a drain, and the like, a high-order silane of at least trisilane (Si 3 H 8 ) to which no other gas is added is subjected to thermal CVD. , The deposition temperature
A method for manufacturing a thin film transistor, comprising forming a channel semiconductor film at a temperature of 480 ° C. or lower and a reaction pressure under a reduced pressure of 0.1 Torr or more.
によるチャネル半導体膜の形成後に連続して、プラズマ
CVD、光CVD,励起種CVDにより低抵抗ｐ形あるいはｎ形の
半導体膜で形成した特許請求の範囲第１項記載の薄膜ト
ランジスタの製造方法。2. The method according to claim 1, wherein said source and drain are formed by said thermal CVD.
Plasma after the formation of the channel semiconductor film by
2. The method for manufacturing a thin film transistor according to claim 1, wherein the thin film is formed of a low-resistance p-type or n-type semiconductor film by CVD, light CVD, or excited species CVD.
温度以下で水素プラズマ処理した特許請求の範囲第１項
又は第２項記載の薄膜トランジスタの製造方法。3. The method for manufacturing a thin film transistor according to claim 1, wherein said channel semiconductor film is subjected to a hydrogen plasma treatment at a temperature lower than a film forming temperature of said thermal CVD.
である特許請求の範囲第１項記載の薄膜トランジスタの
製造方法。4. The method according to claim 1, wherein the film pressure of the channel semiconductor film is 600 ° or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61147381A JP2592238B2 (en) | 1986-06-24 | 1986-06-24 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61147381A JP2592238B2 (en) | 1986-06-24 | 1986-06-24 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS633463A JPS633463A (en) | 1988-01-08 |
| JP2592238B2 true JP2592238B2 (en) | 1997-03-19 |
Family
ID=15428958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61147381A Expired - Lifetime JP2592238B2 (en) | 1986-06-24 | 1986-06-24 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2592238B2 (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0779150B2 (en) * | 1988-12-23 | 1995-08-23 | 株式会社東芝 | Semiconductor integrated circuit |
| US6101078A (en) * | 1997-09-12 | 2000-08-08 | Nec Corporation | Semiconductor device with protection circuit |
| KR101027485B1 (en) | 2001-02-12 | 2011-04-06 | 에이에스엠 아메리카, 인코포레이티드 | Improved process for deposition of semiconductor films |
| US7026219B2 (en) | 2001-02-12 | 2006-04-11 | Asm America, Inc. | Integration of high k gate dielectric |
| US6815007B1 (en) | 2002-03-04 | 2004-11-09 | Taiwan Semiconductor Manufacturing Company | Method to solve IMD-FSG particle and increase Cp yield by using a new tougher UFUN season film |
| JP5005170B2 (en) | 2002-07-19 | 2012-08-22 | エーエスエム アメリカ インコーポレイテッド | Method for forming ultra-high quality silicon-containing compound layer |
| US7294582B2 (en) | 2002-07-19 | 2007-11-13 | Asm International, N.V. | Low temperature silicon compound deposition |
| US7186630B2 (en) | 2002-08-14 | 2007-03-06 | Asm America, Inc. | Deposition of amorphous silicon-containing films |
| US7092287B2 (en) | 2002-12-18 | 2006-08-15 | Asm International N.V. | Method of fabricating silicon nitride nanodots |
| US7005160B2 (en) | 2003-04-24 | 2006-02-28 | Asm America, Inc. | Methods for depositing polycrystalline films with engineered grain structures |
| US7629270B2 (en) | 2004-08-27 | 2009-12-08 | Asm America, Inc. | Remote plasma activated nitridation |
| US7253084B2 (en) | 2004-09-03 | 2007-08-07 | Asm America, Inc. | Deposition from liquid sources |
| US7966969B2 (en) | 2004-09-22 | 2011-06-28 | Asm International N.V. | Deposition of TiN films in a batch reactor |
| US7427571B2 (en) | 2004-10-15 | 2008-09-23 | Asm International, N.V. | Reactor design for reduced particulate generation |
| US7674726B2 (en) | 2004-10-15 | 2010-03-09 | Asm International N.V. | Parts for deposition reactors |
| US7553516B2 (en) | 2005-12-16 | 2009-06-30 | Asm International N.V. | System and method of reducing particle contamination of semiconductor substrates |
| US7691757B2 (en) | 2006-06-22 | 2010-04-06 | Asm International N.V. | Deposition of complex nitride films |
| US7851307B2 (en) | 2007-08-17 | 2010-12-14 | Micron Technology, Inc. | Method of forming complex oxide nanodots for a charge trap |
| US7833906B2 (en) | 2008-12-11 | 2010-11-16 | Asm International N.V. | Titanium silicon nitride deposition |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56135968A (en) * | 1980-03-27 | 1981-10-23 | Canon Inc | Amorphous silicon thin film transistor and manufacture thereof |
| JPS58171859A (en) * | 1982-03-31 | 1983-10-08 | Canon Inc | Manufacture of thin film transistor |
| JPS5955441A (en) * | 1982-09-24 | 1984-03-30 | Mitsui Toatsu Chem Inc | Formation of hydrogenated amorphous silicon film |
| JPS5978919A (en) * | 1982-10-26 | 1984-05-08 | Mitsui Toatsu Chem Inc | Formation of amorphous silicon film |
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1986
- 1986-06-24 JP JP61147381A patent/JP2592238B2/en not_active Expired - Lifetime
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|---|---|
| JPS633463A (en) | 1988-01-08 |
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