JP2591312B2 - Reset circuit for semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit for a semiconductor memory, and more particularly, to a method of storing image data of one field or one frame of a television signal in a unit of an integral number of horizontal scanning periods. The present invention relates to a reset circuit of a semiconductor memory having a reset function in a memory circuit for storing data in a cell array.

[Conventional technology]

A configuration example of a conventional semiconductor memory configured to store one field or one frame of image data of a conventional television signal along one row in a memory cell array in 1 / l unit (1 is an integer) of a horizontal scanning period. This will be described with reference to the block diagram of FIG. The semiconductor memory shown in FIG.
System television signal is digitized with a sampling clock of 4f _SC (f _SC is about 3.58MHz for chrominance signal subcarrier frequency), and an image for one field is stored in units of quantization 4 bits. It is a semiconductor memory. The NTSC system television signals, when digitized at a sampling clock of 4f _SC is the number of pixels one horizontal scanning period just becomes 910 pixels and the number of scanning lines is 262
Or 263 books. Therefore, this semiconductor memory
In the memory cell array, memory cells of 910 pixels × 4 bits are arranged in the horizontal direction, ie, along one row line, and 263 lines of memory cells are arranged in the vertical direction, ie, along one column line.

Next, the configuration of this semiconductor memory will be described. The memory cell array 310 has memory cells of 910 pixels × 4 bits in the horizontal direction and 263 lines in the vertical direction.
It is formed of 4-bit memory cells. The write data registers 321 and 322 each specify a write data register composed of 455 × 4 bits, and the write address pointers 331 and 332 specify a write address in the write data register.
The data input buffer 341 has a write data input terminal D _in 0 to
Write data from the write data registers 321 and 322
Transfer to Read data registers 351 and 352 are 4
The read data register and read address pointers 361 and 362 are configured by 55 × 4 bits and designate a read address in the read data register. Data output buffer 342
Inputs an output control signal ▼, reads data in the read data register, and outputs the data from the data output terminals D _out 0 to 3. Row address decoder 371 is a memory cell array 310
Used to select 263 row lines within. The write address counter 381, the read address counter 382, and the refresh address counter 383 generate address signals for selecting a write row, a read row, and a refresh row, and supply them to the row address decoder 371. The controller timing generator 391 outputs the write clock signal WCK, write control signal, write address clear signal ▲ ▼, read clock signal RCK, read address clear signal ▲
Is input to supply control signals to the write address pointer, write address counter, read address counter, refresh address counter, and read address pointer. The refresh timer 392 outputs a control signal for periodically refreshing a memory cell composed of dynamic cells.

Next, the operation will be described. In response to the signal input, the write address counter 381 and the write address pointer 3
31,332 are reset and initialized to the initial addresses respectively. WCK is the 4f _SC write clock described above,
That is, a clock that oscillates 910 times in one horizontal scanning period is input. Is input with a low level signal indicating write enable. When the reset of the write address counter and the write address pointer is completed, a write operation is performed in synchronization with a write clock signal from WCK. That is, the write data input from Din 0 to Din 3 is input to the write data register 321 through the data input buffer 341 _in synchronization with the WCK signal. When 455 times of writing are completed, the write data register 321 becomes full, so that the data is continuously accumulated in the write data register 322, and
Is transferred to the first row (first row) in the memory cell array 310. When the writing to the write data register 322 is completed 455 times, the writing is transferred to the write data register 321 again, and the write data accumulated in the write data register 322 is transferred to the first row (first row) in the memory cell array. You. When writing to the write data register 321 is completed 455 times again, the writing is transferred to the write data register 322 and the write data accumulated in the 321 is transferred to the second row in the memory cell array. Hereinafter, such an operation is referred to as write data register 321, 32.
2 and the memory cell array 310 are alternately repeated, and data writing is continuously performed. Write address counter
381 supplies a row address signal for transferring data in the write data registers 321 and 322 to the memory cell array 310 to the row address decoder 371, and each time the transfer of the write data registers 321 and 322 is completed, the write address is Preferably, the address is incremented by one, and when the line reaches 263, the line returns to the first line. The read operation is performed in synchronization with a read clock signal from RCK. When a signal is input, the read address counter 382 and the read address pointers 361 and 362 are reset, and are initialized to initial addresses. The aforementioned 4f _SC read clock is input to RCK. In the symbol ▼, a low level signal is input so as to enable reading. For reading, ▲
▼ The signal resets the counter 382 and the pointers 361 and 362, and resets the first
Row data is transferred to the read data registers 351 and 352 in advance. When reset and data transfer are completed, RC
The read operation is performed in synchronization with the read clock signal from K. That is, the read data stored in the read data register 351 in synchronization with the RCK signal passes through the data output buffer 342 to the read data output terminals D _out 0 to D _out 0 to
Output from 3. When 455 read operations have been completed, the read data register 351 becomes empty, so that reading is continued from 352, and the data of the second row is stored in the memory cell array to be read next in the read data register 351 in advance. Will be transferred. When reading is performed 455 times on the read data register 352, the data becomes empty, so that reading is continued from the read data register 351.
Next, the data of the second row in the memory cell array to be read is transferred in advance. When reading is performed on the read data register 351 455 times, the data becomes empty, so that reading is continued from the read data register 352, and the memory to be read next is stored in the empty read data register 351. The data of the third row in the cell array is transferred in advance. The following operation is referred to as the read data register.
Data reading is performed continuously and alternately between the memory cells 351, 352 and the memory cell array 310. The read address counter 382 supplies a row address signal for transferring data in the memory cell array 310 to the read data registers 351 and 352 to the row address decoder 371. The read address is incremented by one every time the transfer to the 351 and 352 is completed. The address is incremented by one, and when it reaches line 263, it returns to line 1.

[Problems to be solved by the invention]

In the above-described conventional semiconductor memory, image data corresponding to the number of pixels in one horizontal scanning period is stored along exactly one row line. Therefore, the first address of each row line always includes each horizontal line. The first data in the scanning period is accumulated. For example, even if data in each horizontal scanning line is read out every other row, simply reading out every other row line of this memory has been dealt with.

However, when such a semiconductor memory is incorporated into a television set, large voltage fluctuations and noise may occur on the power supply line and the GND line of the semiconductor memory due to discharge noise of a CRT drive circuit, a high-voltage circuit, and the like. . Since there is no reset circuit when the data write position of the semiconductor memory shifts due to such voltage fluctuation and noise, there is a disadvantage that data of exactly one horizontal scanning line cannot be stored in each row line. .

An object of the present invention is to provide a semiconductor memory having a reset circuit that detects the voltage fluctuation and noise and always stores image data corresponding to each horizontal scanning line in each row line of the semiconductor memory. It is in.

[Means for solving the problem]

The semiconductor memory reset circuit of the present invention is a semiconductor memory reset circuit that stores a television signal,
A first reset circuit that outputs a first reset signal in the 0th cycle of a write or read clock based on an externally input horizontal synchronization signal, and counting of the clock by the first reset signal is started; A counter circuit for outputting a pulse signal when the clock signal reaches a specified number of times; comparing a temporal position between the first reset signal and the pulse signal; if not, at least one horizontal scan until the deviation is recovered; And a second reset circuit for generating a second reset signal during the period.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. First
In the embodiment shown in the figure, a write reset circuit 4 and a read reset circuit 5 are added to the configuration of FIG. 6 showing a conventional example.
That is, a matrix has memory cells in a two-dimensional direction, and image data of one field or one frame of a television signal is stored in one of the memory cell arrays 310 in 1 / l unit (1 is an integer of 2 or more) of a horizontal scanning period. In order to initialize row data writing / reading in a semiconductor memory configured to store data in rows and configured to write / read data in / from memory cells via the write radar registers 321 and 322 and the read data registers 351 and 352. 3 shows a state in which a circuit for generating a reset signal is incorporated. The circuits having the same symbols as those in FIG. 6 are the same as those in the conventional example.

The write reset circuit 4 receives the write clock WCK and the horizontal synchronization signal HD, and supplies the second reset signal SPSA to the controller and timing generator 391A and the write address pointers 331A and 332A. The read reset circuit 5 is configured to read the read clock RCK and the horizontal synchronizing signal H
D is input to supply the second reset signal SPSB to the controller and timing generator 391A and the read address pointers 361A and 362A. Next, the operation based on this circuit will be described. As described above, the second reset signal SPSA is generated due to noise inside the device.
Occurs when the address in the write address pointer shifts, directly resets and initializes the write address pointer, acts on the controller and the timing generator, and writes the data written to the wrong address in the write data registers 321 and 322. Limit transfer to memory cell array. Note that the second reset signal SPSA
Continues for one horizontal scanning period (approximately 63.58 μs in the case of the NTSC system), so that a write address pointer having a large load capacity can be reliably initialized. Second
Reset signal SPSB is generated when the address in the read address pointer is shifted, directly resets and initializes the read address pointer, acts on the controller and the timing generator, and transfers the data from the memory cell to the read data registers 351 and 352. Make the transfer. Further, the second reset signal SPSB is also set to 1
During the horizontal scanning period, the read address pointer having a large load capacity can be reliably initialized because the read address pointer continues to be output.

Next, the circuit configuration and operation of the write reset circuit 4 and the read reset circuit 5 will be described with reference to the circuit diagram of FIG. In FIG. 2, DFF1 to DFF4 and DFF11 to DFF20 denote D-type flip-flops, and AND1 to AND3 denote AND gates. DFF
1 · DFF2 · AND1 is the first signal that generates the first reset signal FRS
Reset generation circuit 1 of DFF11 to DFF20, AND2, DF
F3 is a counter circuit 2 that generates a first pulse signal FPS. AND3 · DFF4 is a second reset generation circuit 3 that compares the first reset signal FRS and the first pulse signal FPS to generate a second reset signal SPS. Next, the operation of the embodiment circuit shown in FIG. 2 and the role of each signal will be described with reference to the timing chart shown in FIG. In FIG. 3, WCK (RCK) is a write (read) clock signal that oscillates 910 times within one horizontal scanning period. HD is 1 from outside
This is a horizontal synchronizing signal that is periodically input once in the horizontal scanning period, and has a length (high-level period) for several clocks in general. HD1 and HD2 are signals obtained by synchronizing the horizontal synchronizing signal HD with the clock WCK (RCK).
Delayed by about 1WCK (RCK) in phase opposite to D. FRS is a first reset signal, which is generated by a logical product of signals HD1, HD2 and WCK (RCK). The FRS signal is used as a comparison signal for resetting a counter circuit for generating a column address of an address pointer and for generating a second reset signal SPS. This signal is periodically generated at the 0th position of the WCK (RCK) signal in each horizontal scanning period.
CQ1, CQ2, CQ3,..., CQ9, CQ10 are output signals of the counter circuit composed of DF11 to DF20, which are twice the WSK (RCK) signal, respectively.
The signal is output at the cycle of 8 times, 8 times to 512 times, and 1024 times, and is used as the column address signal of the write (read) address pointer as described above. The C909 signal is the 909th highest level of WCK (RCK) by a combination of the signals CQ1 to CQ10. The FPS signal is the first pulse signal and C
909 signal is synchronized by WCK (RCK) signal, and WCK (RCK)
Becomes the high level at the 0th time. Since this signal is generated based on the address signals CQ1 to CQ10 of the write (read) address pointer generated inside the chip, if a shift occurs in the address signal, the FRS generator also shifts. The FPS signal is input to a second reset signal generation circuit, and is compared with the first reset signal FRS to generate a second reset signal SPS described later. The RS signal is a reset signal of DFF4, and is generated by a logical product of the first reset signal FRS and the first pulse signal FPS. The SPS signal functions as a second reset signal, which will be described with reference to the timing chart of FIG. 3 and a circuit example of FIG. FIG. 3 shows a case where the circuit is operating normally, and in particular, a case where a counter circuit for supplying a column address to a write (read) address pointer has no address shift. First, paying attention to the first reset signal FRS signal, this signal is synchronized with the horizontal synchronization signal HD and the external input signal of the clock WCK (RCK) signal, and is the 0th of WCK (RCK) within one horizontal scanning period. Always output a high level. The first pulse signal FPS is
Since it is generated based on the signals of the outputs CQ1 to CQ10 of the counter circuit, as shown in FIG. 3, when the counter circuit does not cause an address shift, it occurs at the 909th position of WCK (RCK). Through DFF3 to which the C909 signal is input, the 0th level is always output at the high level. Therefore, in the second reset signal generating circuit for inputting the FRS signal and the FPS signal, when the counter circuit does not cause an address shift, both signals always go to the 0th high level of WCK (RCK). ,
The logical product of the RS signal is also at the 0th high level.
Accordingly, the DFF4 input to the reset terminal by the RS signal is reset, and the second reset signal SPS signal continues to output a low level. Although the second reset signal SPS will be described later, since the high-level signal directly resets the heavily loaded address pointer during one horizontal scanning period, the address pointer is reset during the low level as in this case. And normal operation is guaranteed. Next, referring to FIG. 4, a case where the address of the counter circuit 2 for supplying the address signal to the write (read) address pointer is shifted due to noise or the like applied inside the device will be described. 4th
FIG. 4A shows the case where the last pulse C909 of the horizontal synchronization signal is shifted by one address in the plus direction, and FIG.
Indicates that at least one address is shifted in the minus direction. The write (read) clock WCK (RCK) and the horizontal synchronization signal HD are continuously input from the outside, and as a result, the first
Is periodically generated at the 0th WCK (RCK). As shown in FIG. 4A, when the output of the counter circuit is shifted by one in the positive direction, the C909 signal becomes WC.
It occurs at the 908th K (RCK), and the FPS signal occurs at the 909th. As a result, the logical product signal RS of FRS and FPS is not generated, and the second reset signal SPS becomes high level at the rising edge of FRS and keeps high level until the RS signal is generated. Also, as shown in FIG. 4B, when the counter circuit output is shifted by at least one in one direction, the C909 signal does not generate a high-level signal even when it becomes the 909th WCK (RCK), As a result, the FPS signal does not generate a high level even at the next 0th time. This results in FRS and FPS
Does not occur, and the second reset signal SPS is F
It goes high at the rising edge of RS and keeps it high until the RS signal is generated. By applying the reset circuit thus configured to reset image data of a television signal having memory cells in a two-dimensional matrix as described above, at least when the address in the write address pointer is shifted, the following is performed. Line writing is restricted, but in subsequent lines, unless the address is shifted,
It is possible to write data at the correct address steadily.
In FIG. 1, the reset signal SPSB in FIG.
Occurs when the address in the read address pointer is shifted, directly resets and initializes the read address pointer, and acts on the controller and the timing generator to transfer data from the memory cells to the read data registers 351 and 352. Since the second reset signal SPSB continues to be output during one horizontal scanning period, the read address pointer having a large load capacity can be reliably initialized. In the case of the embodiment shown in FIG. 2, the counter circuit is reset every horizontal scanning by the first reset signal FRS which is periodically generated, so that the read column address is initialized to the start address. Then, the PCK signal causes the counter circuit 2 to start incrementing, but the second reset signal SPSB continues to be output, so that the address pointer continues to be initialized, and in the next horizontal scanning period, correct data is reliably read from the first address. It becomes possible. In this case, it is sufficiently possible to steadily transfer the read data of the next row to the read data register in advance while the second reset signal SPSB is output.
As described above, according to the first embodiment, when the address in the write / read address pointer is shifted, the shift can be reliably detected, and the address is shifted via the write / read data register.
Even in a circuit type that requires a relatively long transfer period, such as accessing data in a memory cell, a sufficiently long reset period can be taken, so that the next line can be written / read at a correct address position. A semiconductor memory can be provided.

Next, a second embodiment of the present invention will be described with reference to the circuit diagram of FIG. The second embodiment is almost the same as the first embodiment shown in FIG. 2, except that the second reset signal generation circuit is more simplified. RSFF1 is an RS flip-flop. When a pulse signal is input to the S terminal and the R terminal at the same time, RFF
The signal at the terminal has priority. As described with reference to FIGS. 3 and 4, the FRS signal goes high at the 0th WCK (RCK) and is input to the S terminal to try to raise the SPS signal to the high level. However, if the counter circuit is operating normally and the address is not shifted, the FPS signal goes high at the same time, so the RS signal goes high and is input to the R terminal, and as a result, the SPS signal goes high. Prevent the level from rising. If the address shifts, the SPS signal rises because the RS signal does not go high, and the operation shown in FIG. 4 is performed.

〔The invention's effect〕

As described above, according to the present invention, by providing the write and read reset circuits, when the address in the write / read address pointer is shifted, the shift can be reliably detected, and via the write / read data register, Even if the circuit type requires a relatively long transfer period, such as accessing data in a memory cell, a sufficiently long reset period can be taken, so that a semiconductor memory capable of writing / reading at the correct address position in the next line There is an effect that can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a main part of the embodiment of FIG. 1, and FIGS. 3 and 4 show operations of the first embodiment. FIG. 5 is a circuit diagram of a main part of a second embodiment of the present invention, and FIG. 6 is a block diagram of a conventional semiconductor memory. 1... A first reset generation circuit, 2... A counter circuit,
3 ... second reset generation circuit, 4 ... write reset circuit, 5 ... read reset circuit, 310 ... memory cell array, 321,322 ... write data register, 331,3
32: Write address pointer, 341, 342: Data input buffer, 351, 352: Read data register, 361A,
362A: Read address pointer, 381: Write address counter, 382: Read address counter, 383
... Refresh address counter, 391A ... Controller timing generator, 392 ... Refresh timer, DFF1, DFF2, DFF3, DFF4, DFF11, DFF12, DFF13, DFF19, DF
F20: D-type flip-flop, AND1, AND2, AND3 ... AND
Gate, WCK: Write clock, RCK: Read clock, HD: Horizontal synchronization signal, HD1, HD2: Internal signal of horizontal synchronization signal, FRS: First reset signal, C909: Signal generated by counter circuit, FPS pulse signal, RS reset signal, SPS second reset signal.

Claims (2)

(57) [Claims] 1. A reset circuit for a semiconductor memory for storing a television signal, the first circuit outputting a first reset signal in the 0th cycle of a write or read clock based on an externally input horizontal synchronizing signal. A reset circuit, a counter circuit that starts counting the clock with the first reset signal, and outputs a pulse signal when the clock signal reaches a specified number, and a time period between the first reset signal and the pulse signal. A reset circuit that compares target positions and generates a second reset signal during at least one horizontal scanning period until the deviation is recovered in the case of a mismatch. 2. The method according to claim 1, wherein the first and second reset circuits initialize and initialize the writing and reading of image data during a horizontal scanning period of a television signal to a memory array arranged in units of 1 / l (l is an integer). 2. The reset circuit of a semiconductor memory according to claim 1, wherein said reset signal is generated.