JP2589324B2 - Electroless gold plating method - Google Patents
Electroless gold plating methodInfo
- Publication number
- JP2589324B2 JP2589324B2 JP26840687A JP26840687A JP2589324B2 JP 2589324 B2 JP2589324 B2 JP 2589324B2 JP 26840687 A JP26840687 A JP 26840687A JP 26840687 A JP26840687 A JP 26840687A JP 2589324 B2 JP2589324 B2 JP 2589324B2
- Authority
- JP
- Japan
- Prior art keywords
- gold plating
- plating
- electroless
- electroless gold
- bonding property
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/42—Coating with noble metals
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明はセラミック、ガラス等からなる絶縁体上のメ
タライズパターンへの無電解金めっき方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for electroless gold plating on a metallized pattern on an insulator made of ceramic, glass or the like.
(従来の技術) ピングリッドアレイあるいはチップキャリア等の半導
体装置用パッケージにあっては、配線部等の導体回路部
はメタライズ層などからなるメタライズパターンによっ
て形成されており、このメタライズパターンにたいして
は通常ニッケルめっきおよび金めっきがなされる。この
ニッケルめっきおよび金めっきは、一般に電解めっきに
よってなされ、めっきのための導通を確保するため前記
メタライズパターンはすべて短絡された形状に形成され
ている。(Prior Art) In a package for a semiconductor device such as a pin grid array or a chip carrier, a conductor circuit portion such as a wiring portion is formed by a metallized pattern formed of a metallized layer and the like. Plating and gold plating are performed. The nickel plating and the gold plating are generally performed by electrolytic plating, and the metallized patterns are all formed into a short-circuited shape in order to secure conduction for plating.
したがって、これら電解めっきによってめっき処理が
なされるピングリッドアレイ、チップキャリア等の半導
体装置用パッケージではめっき後に、導通パターンのめ
っきのために短絡させた不要部分を研削などして除去
し、導体回路部等を独立分離させなければならない。Therefore, in a package for a semiconductor device such as a pin grid array or a chip carrier which is subjected to a plating process by electrolytic plating, unnecessary portions short-circuited due to plating of a conductive pattern are removed by grinding after plating, and the conductive circuit portion is removed. Etc. must be separated independently.
(発明が解決しようとする問題点) 上述したように、従来の電解めっきによる場合は、導
通パターンをあらかじめ短絡した形状に構成しなければ
ならないため、短絡パターンを形成するためのスペース
が必要であること、また短絡した導通パターンを形成す
るために余分のペーストを要すること、後工程で研削な
どにより除去される部分の金めっきが無駄になること等
の問題点がある。(Problems to be Solved by the Invention) As described above, in the case of the conventional electrolytic plating, since the conductive pattern must be formed in a short-circuited shape in advance, a space for forming the short-circuit pattern is required. In addition, there is a problem that extra paste is required to form a short-circuited conductive pattern, and that gold plating in a portion removed by grinding or the like in a later process is wasted.
なお、金めっきに関しては無電解金めっき方法も試み
られているが、適当な金めっき浴がないのが現状であ
り、また置換金めっき後に単に無電解金めっきを行うだ
けでは半導体装置用パッケージとして要求される耐熱
性、ダイボンディング性、ワイヤボンディング性を満足
するものが得られない。As for gold plating, an electroless gold plating method has also been tried, but at present there is no suitable gold plating bath. A material satisfying the required heat resistance, die bonding property, and wire bonding property cannot be obtained.
そこで、本発明は上記問題点を解消すべくなされたも
のであり、その目的とするところは、無電解金めっき方
法によって、半導体装置用パッケージとしての十分な耐
熱性、ダイボンディング性、ワイヤボンディング性を有
するパッケージを得ることのできる無電解金めっき方法
を提供するにある。Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device package having sufficient heat resistance, die bonding property, and wire bonding property by an electroless gold plating method. An object of the present invention is to provide an electroless gold plating method capable of obtaining a package having the following.
(問題点を解決するための手段) 本発明は上記目的を達成するため次の構成をそなえ
る。(Means for Solving the Problems) The present invention has the following configuration to achieve the above object.
すなわち、絶縁体の表面に設けられたメタライズパタ
ーンの無電解金めっき方法において、前記メタライズパ
ターンに置換金めっき処理を行った後に、アニール処理
および酸処理を施し、さらに再び置換金めっき処理を施
し、ついで無電解金めっき処理を施すことを特徴とす
る。That is, in the electroless gold plating method of the metallized pattern provided on the surface of the insulator, after performing the replacement gold plating process on the metallized pattern, performing an annealing process and an acid process, and further performing the replacement gold plating process, Then, an electroless gold plating process is performed.
(発明の概要) 本発明では、メタライズパターンが設けられた半導体
装置用パッケージにたいし、ニッケルめっきおよび金め
っきを無電解ニッケルめっきおよび無電解金めっきによ
って行う。なお、無電解金めっきの際、置換金めっきを
行った後に単に無電解金めっきを行うだけでは前述した
ように十分な耐熱性、ダイボンディング性、ワイヤボン
ディング性を有する半導体装置用パッケージが得られな
いので、本発明では、所定のニッケルめっき等の処理が
施された試料に置換金めっきを施し、ついで水素還元雰
囲気中で760℃、10分間熱処理した後、硝酸(1:1)に浸
漬し、これによって試料の表面に過剰に拡散してきたニ
ッケルを除去し、再び置換金めっきそして無電解金めっ
きを施す。(Summary of the Invention) In the present invention, nickel plating and gold plating are performed by electroless nickel plating and electroless gold plating on a semiconductor device package provided with a metallized pattern. In the case of electroless gold plating, simply performing electroless gold plating after performing displacement gold plating can provide a semiconductor device package having sufficient heat resistance, die bonding property, and wire bonding property as described above. Therefore, in the present invention, a sample subjected to a predetermined treatment such as nickel plating is subjected to displacement gold plating, and then subjected to a heat treatment at 760 ° C. for 10 minutes in a hydrogen reducing atmosphere, and then immersed in nitric acid (1: 1). Thus, nickel excessively diffused on the surface of the sample is removed, and replacement gold plating and electroless gold plating are performed again.
これらの工程によって、良好な耐熱性およびダイボン
ディング性、ワイヤボンディング性を有する金めっきが
施された半導体装置用パッケージが得られる。Through these steps, a gold-plated semiconductor device package having good heat resistance, die bonding property, and wire bonding property can be obtained.
(実施例) 以下、本発明の金めっき方法をピングリッドアレイに
施した実施例について説明する。(Example) Hereinafter, an example in which the gold plating method of the present invention is applied to a pin grid array will be described.
リードピンのろう付け工程まで終了した64ピンのピン
グリッドアレイにたいし、以下の工程によって無電解金
ニッケルめっきおよび無電解金めっきを施した。The 64-pin pin grid array completed up to the lead pin brazing step was subjected to electroless gold nickel plating and electroless gold plating by the following steps.
脱脂処理(オーカイト、60℃、5分) →酸処理(1:10硫酸、常温5分) →活性化処理(パラジウム活性液、65℃、20分) →酸処理(1:1塩酸、常温30秒) →無電解ニッケルめっき(Ni−Bプロセス、65℃、20
分) →置換金めっき(IM-Gold:日本高純度化学製、90℃、30
分) →アニール処理(水素雰囲気、760℃、10分) →酸処理(1:1硝酸、常温5分) →置換金めっき(IM-Gold、90℃、20分) →無電解金めっき(シアン化金カリウム5.8g/l、シアン
化カリウム1.3g/l、水酸化カリウム45g/l、ジメチルア
ミンボラン23.6g/l、鉛2ppm、85℃、2時間) 上記処理のうちアニール処理はニッケルめっき層にた
いして置換金めっき層の密着性をたかめる作用があり、
その後の硝酸による酸処理はアニール後の置換金めっき
層表面に、より金含有量が多い部分を露出させるために
行うものである。Degreasing treatment (okite, 60 ° C, 5 minutes) → acid treatment (1:10 sulfuric acid, normal temperature 5 minutes) → activation treatment (palladium active solution, 65 ° C, 20 minutes) → acid treatment (1: 1 hydrochloric acid, normal temperature 30) Sec) → Electroless nickel plating (Ni-B process, 65 ℃, 20
Min) → displacement gold plating (IM-Gold: manufactured by Nippon Kojundo Chemical, 90 ℃, 30
Minutes) → Annealing treatment (hydrogen atmosphere, 760 ° C, 10 minutes) → Acid treatment (1: 1 nitric acid, normal temperature 5 minutes) → Displacement gold plating (IM-Gold, 90 ° C, 20 minutes) → Electroless gold plating (cyan 5.8 g / l potassium potassium cyanide, 1.3 g / l potassium cyanide, 45 g / l potassium hydroxide, 23.6 g / l dimethylamine borane, 2 ppm lead, 85 ° C, 2 hours) Has the effect of enhancing the adhesion of the gold plating layer,
The subsequent acid treatment with nitric acid is performed to expose a portion having a higher gold content on the surface of the substituted gold plating layer after annealing.
以下、表1および表2に、上記工程によって金めっき
されたピングリッドアレイと、置換金めっきに単に無電
解金めっきを施したもののそれぞれについて、耐熱性と
ワイヤボンディング性を比較した結果を示す。Hereinafter, Tables 1 and 2 show the results of comparing the heat resistance and the wire bonding property of each of the pin grid array plated with gold in the above-described process and the one obtained by simply performing electroless gold plating on the replacement gold plating.
表1は、試料を450℃に保った際の金めっきの変色の
程度によって耐熱性を調べたものである。 Table 1 shows the heat resistance determined by the degree of discoloration of the gold plating when the sample was kept at 450 ° C.
表1でNo.1の試料は置換金めっき後に単に無電解金め
っきを施したもの、No.2の試料は上述した置換金めっ
き、アニール処理、酸処理、置換金めっき、無電解金め
っきを施したものである。表中で○印は指定時間内で金
めっきが変色しなかったもの、×印は変色したもの、△
印は若干変色したものを示す。In Table 1, the No. 1 sample was obtained by simply applying electroless gold plating after replacement gold plating, and the No. 2 sample was obtained by using the above-described replacement gold plating, annealing, acid treatment, replacement gold plating, and electroless gold plating. It was done. In the table, ○ indicates that the gold plating did not change color within the designated time, X indicates that the color changed, Δ
The mark indicates a slightly discolored one.
表1の結果から上述した置換金めっき、アニール処
理、酸処理および置換金めっきを無電解金めっきの前に
施した金めっきは加熱にたいして安定しており、単に置
換金めっき後に無電解金めっきを施したものに比べては
るかに耐熱性が向上していることがわかる。From the results shown in Table 1, the gold plating obtained by performing the above-described substitutional gold plating, annealing treatment, acid treatment, and substitutional gold plating before the electroless gold plating is stable against heating. It can be seen that the heat resistance is much improved as compared with the heat treatment.
表2はワイヤボンディングがなされた上記No.1とNo.2
の試料各50個の検体にたいして、200℃、60時間エージ
ング処理を施した後のワイヤの剥離数を調べたものであ
る。 Table 2 shows the above No. 1 and No. 2 with wire bonding.
For each of 50 samples, the number of peeled wires after aging treatment at 200 ° C. for 60 hours was examined.
表2から、アニール処理後、酸処理、置換金めっきお
よび無電解金めっきが施されたNo.2の検体についてはエ
ージング後もワイヤの剥離が1個も見られず、No.1の検
体と比較して顕著なワイヤボンディング性の向上が見ら
れた。Table 2 shows that no wire peeling was observed even after aging for the No. 2 sample that had been subjected to the acid treatment, displacement gold plating, and electroless gold plating after the annealing treatment. A remarkable improvement in the wire bonding property was observed.
次に、表3および表4は44ピンのチップキャリアにつ
いて同様な試験を行った結果を示すものである。表3お
よび表4でNo.3の試料は置換金めっきおよび無電解金め
っきを施したものであり、No.4の試料は上述したピング
リッドアレイでのNo.2の試料の処理工程と全く同じ処理
工程によって金めっきを施したものである。なお、ここ
では無電解金めっき方法によっているので、チップキャ
リアは1つ1つ分割されたチップキャリアを用いてい
る。Next, Tables 3 and 4 show the results of similar tests performed on a 44-pin chip carrier. In Tables 3 and 4, the sample of No. 3 was subjected to displacement gold plating and electroless gold plating, and the sample of No. 4 was completely the same as the process of processing the sample of No. 2 in the above-mentioned pin grid array. The gold plating was performed in the same processing step. Here, since the electroless gold plating method is used, a chip carrier divided into individual chip carriers is used.
ワイヤボンディング性を試験するために用いた検体数
は30個であり、エージング条件は200℃、60時間であ
る。 The number of samples used for testing the wire bonding property was 30, and the aging conditions were 200 ° C. and 60 hours.
これらの結果からも、アニール処理後、酸処理、置換
金めっきおよび無電解金めっきを施したチップキャリア
の耐熱性およびワイヤボンディング性がきわめて向上し
ていることがわかる。From these results, it can be seen that the heat resistance and the wire bonding property of the chip carrier which has been subjected to the acid treatment, the substitutional gold plating and the electroless gold plating after the annealing treatment are extremely improved.
上述した結果からわかるように、金めっきの際にアニ
ール処理、酸処理等を施すことによって、金めっきの耐
熱性およびワイヤボンディング性を大幅に向上させるこ
とができた。また、ダイボンディング性に関してもワイ
ヤボンディング性と同様に良好な特性が得られた。この
結果、無電解金めっき方法を使用して、半導体パッケー
ジに要求される条件を十分満足するものを得ることがで
きる。As can be seen from the above results, the heat resistance and the wire bonding property of the gold plating could be significantly improved by performing the annealing treatment, the acid treatment and the like at the time of the gold plating. As for the die bonding property, the same good properties as the wire bonding property were obtained. As a result, by using the electroless gold plating method, it is possible to obtain a product that sufficiently satisfies the conditions required for the semiconductor package.
(発明の効果) 本発明の無電解金めっき方法によれば、上述したよう
に、置換金めっきを施した後に、アニール処理、および
酸処理を行って置換金めっきを安定化し、その後再度、
置換金めっきを行ってから無電解金めっきを行うことに
より、耐熱性、ダイボンディング性、ワイヤボンディン
グ性に優れた金めっき被膜が得られるから、半導体装置
用パッケージとして要求される十分な耐熱性、ダイボン
ディング性、ワイヤボンディング性を満足する信頼性の
高い半導体装置用パッケージを提供することができる。(Effects of the Invention) According to the electroless gold plating method of the present invention, as described above, after performing substitutional gold plating, annealing treatment and acid treatment are performed to stabilize the substitutional gold plating.
By performing electroless gold plating after performing displacement gold plating, a gold plating film having excellent heat resistance, die bonding property, and wire bonding property can be obtained. A highly reliable semiconductor device package that satisfies the die bonding property and the wire bonding property can be provided.
また、これら半導体装置用パッケージは無電解めっき
によって得られるから、メタライズパターンにめっきの
ための短絡部分を設ける必要がなく、スペースを有効に
活用できる点で有利であり、メタライズペーストおよび
研削などにより除去される金めっきが節約できるととも
に、メタライズパターンを独立分離させる研削工程など
が不要となる等の著効を奏する。In addition, since these semiconductor device packages are obtained by electroless plating, there is no need to provide a short-circuit portion for plating on the metallized pattern, which is advantageous in that the space can be effectively utilized, and is removed by metallizing paste and grinding. This saves the amount of gold plating to be performed and eliminates the need for a grinding step for separating metallized patterns independently.
以上、本発明について好適な実施例を挙げて種々説明
したが、本発明はこの実施例に限定されるものではな
く、発明の精神を逸脱しない範囲内で多くの改変を施し
得るのはもちろんのことである。As described above, the present invention has been described variously with reference to the preferred embodiments. However, the present invention is not limited to these embodiments, and it goes without saying that many modifications can be made without departing from the spirit of the invention. That is.
Claims (1)
ーンの無電解金めっき方法において、前記メタライズパ
ターンに置換金めっき処理を行った後に、アニール処理
および酸処理を施し、さらに再び置換金めっき処理を施
し、ついで無電解金めっき処理を施すことを特徴とする
無電解金めっき方法。In a method of electroless gold plating of a metallized pattern provided on the surface of an insulator, after the metallized pattern is subjected to substitutional gold plating, an annealing treatment and an acid treatment are performed, and then the substitutional gold plating treatment is performed again. And then performing an electroless gold plating process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26840687A JP2589324B2 (en) | 1987-10-24 | 1987-10-24 | Electroless gold plating method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26840687A JP2589324B2 (en) | 1987-10-24 | 1987-10-24 | Electroless gold plating method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01111881A JPH01111881A (en) | 1989-04-28 |
JP2589324B2 true JP2589324B2 (en) | 1997-03-12 |
Family
ID=17458033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26840687A Expired - Fee Related JP2589324B2 (en) | 1987-10-24 | 1987-10-24 | Electroless gold plating method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2589324B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3693300B2 (en) * | 1993-09-03 | 2005-09-07 | 日本特殊陶業株式会社 | External connection terminal of semiconductor package and manufacturing method thereof |
JPH11150355A (en) * | 1997-11-17 | 1999-06-02 | Hitachi Ltd | Plating method of ceramic board |
-
1987
- 1987-10-24 JP JP26840687A patent/JP2589324B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH01111881A (en) | 1989-04-28 |
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Legal Events
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