JP2587423B2 - Cryptographic processing unit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a cryptographic processing device suitable for an information processing device. In particular, the present invention relates to a variable type cryptographic processing device of a conventional type cryptographic device which can perform flexible encryption by changing the number of encryption processing stages.

[Summary] The present invention provides a cryptographic processing apparatus suitable for an information processing apparatus, in which information on the number of stages of encryption processing is included in an encryption key, the information is decrypted, and an encryption processing block corresponding to the number of decrypted processing steps is selected. Thus, it is possible to flexibly set the encryption strength and the encryption processing performance according to the amount of data handled by the information processing apparatus and the confidentiality.

[Prior Art] Conventionally, an encryption processing method is composed of n encryption processing blocks and n encryption processing blocks.
The encryption strength is maintained by performing the encryption process twice. As such a conventional cryptographic processing method, US FIPS (FIPS, Federal I
Data Encryption Standard (Date Encryption Standard, hereinafter DES)
It is called a method. ) (FIPS Publication 46).

The outline of this DES is described in Iwanami Shoten Publishing Co., Ltd. Iwanami Course Information Science-4 Information and Coding Theory 1985 pp. 223-227 Hiroshi Miyagawa et al.

[Problems to be Solved by the Invention] However, in such a conventional cryptographic processing method, the cryptographic processing itself is disclosed, and it is advantageous for the spread of cryptography such as being integrated into a large-scale integrated circuit and commercially available. An information processing apparatus that incorporates an encryption process that focuses on maintaining strength has the following disadvantages. In other words, when applied to data processing that needs to process a large amount of data, for example, data exchange using a magnetic tape file, multi-stage encryption processing (16 stages in the DES method) takes a lot of time to encrypt. Even if the entire information processing time is too long, or the information that reduces the confidential value of the information in a short period of time (for example, a financial report of a company before publication, such as a newspaper) is encrypted with the same information processing device, important confidentiality is maintained. In the same way as with, encryption can be performed only to maintain encryption strength that takes years to decrypt, so that unnecessary encryption processing time is wasted.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks, and an object of the present invention is to provide an encryption processing device capable of flexibly setting an encryption strength and an encryption processing speed according to the amount of data handled by an information processing device and confidentiality.

[Means for Solving the Problems] The present invention relates to a plurality of processing blocks for inputting a plurality of keys and encrypting a plaintext to form a ciphertext, or performing a process of decoding a ciphertext to form a plaintext. Inputting an encryption key including information indicating the number of stages of encryption processing, and inputting a processing stage number decryption circuit for obtaining the number of stages of encryption processing from the information, and at the time of encryption, inputting a plaintext to be subjected to encryption processing; The number of encryption processing stages is obtained from the processing stage number decryption circuit, and circuits are connected so that the plaintext is sequentially encrypted by the processing blocks corresponding to the number of stages, and at the time of decryption, the encryption target to be decrypted is decrypted. A process of inputting the minutes and obtaining the number of stages of encryption processing from the processing stage number decryption circuit to obtain the number of stages of decryption processing, and connecting the circuits so that the ciphertext is sequentially decrypted by the processing blocks corresponding to the number of stages. Stage number switcher and front A plurality of keys are created by inputting the encryption key, and during encryption, the plurality of keys are sequentially supplied to the corresponding processing blocks. And a key supply circuit for sequentially supplying the processing blocks to the processing block in reverse order.

[Operation] Information indicating the number of stages for performing the encryption process included in the encryption key is decrypted by the processing stage number decryption circuit, and the number of processing stages is output. The number of processing stages switching means selects an encryption processing block for performing encryption processing based on the number of processing stages. By the above operation, the encryption strength and the encryption processing performance can be flexibly set according to the data amount and confidentiality handled by the information processing apparatus.

Example An example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a cryptographic processing apparatus according to one embodiment of the present invention. In FIG. 1, a cryptographic processing apparatus includes an input terminal A for inputting an encryption key from outside the figure, and an encryption key input from the input terminal A, and generates n different keys K1 to Kn according to a predetermined rule to perform encryption. A key supply circuit 1 that outputs the keys in reverse order during encryption and decryption, and a continuously connected encryption processing block that inputs keys K1 to Kn from the key supply circuit 1 and performs encryption or decryption processing 2 1-2n.

Further, the cryptographic processing device includes an encryption key input from outside the drawing including information indicating the number of processing stages to be encrypted or decrypted, a processing stage number decoding circuit 3 for decoding this information, and a plaintext or ciphertext from outside the drawing. Input terminal B, and a plaintext or ciphertext is input from the input terminal B, and the processing stage number decoding circuit 3
The internal switch is switched by inputting the number of processing stages x for encryption or the decryption for decryption (terminal a at the time of decryption) to process the output of the encryption processing stage number switching device 4 and the output of the encryption processing stage number switching device 4 A dividing circuit 5 for passing the data through the cryptographic processing block 2 having the number of stages x, a merging circuit 6 for receiving data that has been subjected to encryption or decryption processing, and a decryption circuit 3 for determining whether or not the data is encrypted at the time of encryption. The number of processing stages x is input at the time of encryption, and the internal switch is switched (terminal b at the time of encryption) to input the output of the merging circuit 6 and the output of the decryption stage number switch 7 is input. An output terminal C for outputting to the outside is provided.

The operation of the cryptographic processing device having such a configuration will be described. In FIG. 1, an encryption key is determined first. next,
In this embodiment, the encryption key includes information on the number of encryption stages. That is, as for the method of creating an encryption key, for example, a random number is generated as in the conventional technique, and an encryption key (for example, 56 bits in the DES method) is obtained, and then the first m bits are changed so that the first m bits indicate the number of processing stages. A known method is used. FIG. 1 illustrates a case where a method of indicating the number of processing stages in the first m bits of the encryption key is used.

First, an encryption key is input from the input terminal A, and plaintext is input from the input terminal B. The processing stage number decryption circuit 3 decodes the first m bits of the encryption key to obtain the processing stage number x, and then notifies the encryption processing stage number switch 4 of the processing stage number x. Further, it notifies the decryption processing stage number switch 7 that the encryption is performed. The encryption processing stage number switch 4 switches the internal switch according to the processing stage number x, and maintains the circuit so that the plaintext passes through the block of the x-stage sentence and is encrypted. Decoding processing stage number switch 7
Connects a circuit so as to obtain the output of the encryption processing block 2n according to the instruction of encryption.

FIG. 1 shows the case where x = n-1, where the plaintext is encrypted in a cryptographic processing block 22 according to the key K2 obtained by the key supplier 1 and then in a cryptographic processing block 23 according to the key K3. The data is encrypted and thereafter similarly encrypted by the encryption processing block 2n according to the key Kn to become a ciphertext, which is output from the output terminal C via the terminal b. That is, the plaintext is subjected to encryption processing for the number of processing stages x stored in the first m bits of the encryption key.

Next, in the decryption process for returning the cipher text to plain text, the same encryption key given at the time of encryption is input from the input terminal A, and the cipher text is input from the input terminal B. The processing stage number decoding circuit 3 calculates the processing stage number x from the first m bits of the encryption key.
After that, the number of processing stages x is notified to the decoding stage number switch 7. Further, the encryption processing stage number switch 4 is notified that the decryption is performed. The number-of-decryption-stages switch 7 switches the internal switch according to the number of processing stages x so that the ciphertext passes through the x-stage encryption processing blocks 2 and is decrypted. Each circuit is connected so as to provide an input to the cryptographic processing block 21 in accordance with an instruction to that effect. When decrypting the ciphertext obtained as described above, the input from the input terminal B flows to the cryptographic processing block 21 through the terminal a, and the output to the output terminal C flows from the cryptographic processing block 2X. Connected.

The ciphertext is the key given in reverse order by the key supplier 1.
According to Kn, the data is decrypted in the cryptographic processing block 21 and then in the cryptographic processing block 22 in accordance with the key Kn-1.
1 is decrypted into plaintext, which is output from the output terminal C. That is, the plaintext undergoes decryption processing for the number of processing stages x stored in the first m bits of the encryption key.

As described above, in this embodiment, if the number of encryption processing stages is increased, processing performance is slow but encryption strength is strong.
It is particularly suitable for encrypting a small amount of important information, and if the number of encryption processing steps is reduced, the encryption strength is weak but the processing performance is fast. Can be realized.

[Effects of the Invention] As described above, according to the present invention, information on the number of encryption processing stages is included in an encryption key, and this information is read by a processing stage number decryption circuit to control the number of encryption and decryption processes. As a result, there is an excellent effect that the encryption strength and the encryption processing performance can be flexibly set according to the amount of data handled by the information processing apparatus and the confidentiality.

[Brief description of the drawings]

FIG. 1 is a block diagram of a cryptographic processing apparatus according to one embodiment of the present invention. 1 ... key supply circuit, 21-2n ... encryption processing block,
3... Processing stage number decryption circuit, 4... Encryption processing stage number switcher,
5 split circuit, 6 merge circuit, 7 decoding processing stage number switch, A, B ... input terminal, C ... output terminal, K1 to Kn
... Keys, a, b... Terminals, x.

Claims (1)

(57) [Claims] 1. A plurality of processing blocks for inputting a plurality of keys and encrypting a plaintext to form a ciphertext, or performing a process of decrypting a ciphertext to form a plaintext, and information indicating the number of stages of the encryption process. And a processing stage number decryption circuit for obtaining the number of stages of encryption processing from the information, and at the time of encryption, a plaintext to be encrypted is input,
The number of encryption processing stages is obtained from the processing stage number decryption circuit, and circuits are connected so that the plaintext is sequentially encrypted by the processing blocks corresponding to the number of stages. Minutes, and the number of stages of the encryption process is obtained from the number of stages of decryption circuit and the number of stages of the decryption process,
A processing stage number switch for connecting circuits so that the ciphertext is sequentially decrypted by the processing blocks for the number of stages; and inputting the encryption key to create the plurality of keys. A key supply circuit for sequentially supplying a plurality of keys to the corresponding processing blocks, and for sequentially supplying the plurality of keys to the processing block in a reverse order to the decryption at the time of decryption. Characteristic cryptographic processing device.