JPS59167147A - Ciphering device - Google Patents

Ciphering device

Info

Publication number
JPS59167147A
JPS59167147A JP58040580A JP4058083A JPS59167147A JP S59167147 A JPS59167147 A JP S59167147A JP 58040580 A JP58040580 A JP 58040580A JP 4058083 A JP4058083 A JP 4058083A JP S59167147 A JPS59167147 A JP S59167147A
Authority
JP
Japan
Prior art keywords
data
circuit
register
encryption
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58040580A
Other languages
Japanese (ja)
Inventor
Shunichiro Sakamoto
俊一郎 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP58040580A priority Critical patent/JPS59167147A/en
Publication of JPS59167147A publication Critical patent/JPS59167147A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12Details relating to cryptographic hardware or logic circuitry

Abstract

PURPOSE:To shorten the access time to a ciphering circuit by using an exclusive OR between many different ciphered data and input data as output data and ciphering data again to lead out many different ciphered data on a basis of output data when all ciphered data are used. CONSTITUTION:A cipher key is set into a ciphering circuit 3, and the initial value is set to a register 2 through an input selecting circuit 6. This initial value is ciphered by a ciphering circuit 3 and is inputted to a register 9 of a data transposing circuit 7. Input data is set to a register 1, and OR between input data and the output of the circuit 7 is operated in an exclusive OR circuit 5 and is outputted to a line 13. At this time, since an input selecting circuit 6 selects the line 13, output data is set to the register 2 simultaneously and is ciphered by the circuit. The circuit 7 sets ciphered data from the circuit 3 to the register 9 and outputs it to the circuit 5. The circuit 5 operates exclusive OR between ciphered data and data in the register 1 and outputs the result to the line 13.

Description

【発明の詳細な説明】 (技術分野) 本発明は、特に例えばDES (Data Encry
ptionStandard )アルゴリズムとして知
られている暗号手段及びフィードバック機構を用いて暗
号化する暗号装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention is particularly applicable to, for example, DES (Data Encry
The present invention relates to a cryptographic device that performs encryption using a cryptographic means and feedback mechanism known as a ptionStandard algorithm.

(従来技術) 従来から暗号化のためにDESアルゴリズムと呼ばれる
暗号手段が知られている。該暗号手段は64ビツトのデ
ータを実質56ビツトの暗号キイを使用し16段の類似
の変換を積重ね他の64ビツトのデータに変換するもの
である。このため解読がきわめて困難であるが反面、暗
号化の時間が大きいという欠点があった。
(Prior Art) An encryption means called DES algorithm has been known for encryption. The encryption means essentially uses a 56-bit encryption key to convert 64-bit data into other 64-bit data by stacking 16 stages of similar conversions. This makes it extremely difficult to decipher, but on the other hand, it has the disadvantage that it takes a long time to encrypt.

また単一の暗号キイに対して同一のビット・パターンを
もつデータの暗号出力は同じビットパターンをとる。こ
のため暗号データ中に存在する同一のビット・ノやター
ンが暗号キイ解読の手掛シとして利用される危険性があ
った。
Furthermore, the encrypted output of data having the same bit pattern for a single encryption key has the same bit pattern. Therefore, there was a risk that the same bits and turns existing in the encrypted data could be used as clues to decrypt the encrypted key.

この点を解決する方式、とじていわゆるフィード・バッ
ク構成を利用する方式が知られている。これは以前の暗
号化処理の結果が次の入力データブロックの暗号化に利
用されていく。このため入力データが同一のビットパタ
ーンであっても暗号化出力は個々異なったビット・パタ
ーンをもつようになる。第1図はこのフィード・バック
構成を取り入れた暗号装置の代表例である。第1図にお
いて1は入力データ・レジスタ、2は暗号化入力レジス
タ、3は暗号化回路、4は暗号出力レジスタ、5は排他
的論理和回路を表わしている。暗号キイは暗号化回路3
にセットされ最初レジスタ2には暗号基準データとして
初期値がセットされる。この状態で暗号化回路3は上記
レジスタ2の内容に対して暗号キイを作用させ出力をレ
ジスタ4に入れる。レジスタ4の内容と入力データ・レ
ジスタ2の内容がビット対応に排他的論理和が取られ出
力される。該暗号出力はレジスタ2に帰還されて次の暗
号基準データとなる。
A known method for solving this problem is a method using a so-called feedback structure. The result of the previous encryption process is used to encrypt the next input data block. Therefore, even if the input data has the same bit pattern, the encrypted output will have different bit patterns. FIG. 1 is a typical example of a cryptographic device incorporating this feedback structure. In FIG. 1, 1 is an input data register, 2 is an encryption input register, 3 is an encryption circuit, 4 is an encryption output register, and 5 is an exclusive OR circuit. The encryption key is encryption circuit 3
, and an initial value is initially set in register 2 as cryptographic reference data. In this state, the encryption circuit 3 applies the encryption key to the contents of the register 2 and inputs the output to the register 4. The contents of register 4 and the contents of input data register 2 are exclusive ORed bitwise and output. The cipher output is fed back to the register 2 and becomes the next cipher reference data.

このフィード・バック暗号化装置においても暗号化回路
3の出力によって暗号化される入力データのビット数は
暗号化回路3の出力ビツト数と同じであり、暗号化回路
3の暗号化の速度以上にこの装置の処理速度を上げるこ
とはできない。
In this feedback encryption device as well, the number of bits of input data encrypted by the output of the encryption circuit 3 is the same as the number of output bits of the encryption circuit 3, and the encryption speed is faster than the encryption speed of the encryption circuit 3. It is not possible to increase the processing speed of this device.

(発明の目的) 本発明は上記点に鑑みてなされたものでその目的1−す
Aところは暗号化回路の出力から多数の異なった暗号化
データを発生することにょシ暗号化回路へのアクセス時
間を減少し暗号化処理速度の速い暗号装置を提供するこ
とである。
(Object of the Invention) The present invention has been made in view of the above points.Object 1-A: Access to the encryption circuit is necessary to generate a large number of different encrypted data from the output of the encryption circuit. It is an object of the present invention to provide an encryption device that reduces time and has a high encryption processing speed.

(発明の構成) 本発明は暗号化回路の出力から多数の異った暗号化デー
タを導き各暗号化データと入力データとの排他的論理和
を求めこれを出力データとし、上記具った暗号化データ
を総て使用したときに出力データを基に再び暗号化して
多数の異った暗号化データを導くことにょシ暗号化を行
なうものである。以下詳細に説明する。
(Structure of the Invention) The present invention derives a large number of different encrypted data from the output of an encryption circuit, performs an exclusive OR of each encrypted data and input data, and uses this as output data. When all the encrypted data is used, the output data is encrypted again to derive a large number of different encrypted data. This will be explained in detail below.

(実施例) 第2図は本発明σ一実施例であって図中6は暗号化入力
データレジスタ2への入力選択回路、7はデータ組み替
え回路、8は制御回路、9は64ビz、・トLのシフト
レノスタ、1oはインバータ回路、11はデータ組み替
え回路7の制御回路、12は入力データ・ライン、13
は出力データ・ラインである。尚、第1図と同一のもの
は同一符号とする。
(Embodiment) FIG. 2 shows an embodiment of the present invention, in which 6 is an input selection circuit to the encrypted input data register 2, 7 is a data recombination circuit, 8 is a control circuit, 9 is a 64 bit,・Shift reno star of L, 1o is an inverter circuit, 11 is a control circuit for the data recombination circuit 7, 12 is an input data line, 13
is the output data line. Components that are the same as those in FIG. 1 are given the same reference numerals.

次に暗号化処理は以下の如く行なわれる。Next, the encryption process is performed as follows.

(1)  暗号化の前に暗号キーと初期値を設定する。(1) Set the encryption key and initial value before encryption.

暗号キーは暗号化回路3内にセットされ初期値は入力デ
ータ・ライン12から入力選択回路6を通って暗号化入
力データレジスタ2にセットされる。
The encryption key is set in the encryption circuit 3 and the initial value is set in the encryption input data register 2 from the input data line 12 through the input selection circuit 6.

この初期値に対して暗号化回路3で暗号化を行い暗号化
された初期値をデータ組み替え回路7のシフトレノスタ
9に入力しておく。
This initial value is encrypted by the encryption circuit 3 and the encrypted initial value is input to the shift reno star 9 of the data recombination circuit 7.

(2)  ここで入力データの暗号化が可能となシ、入
力データが制御回路8のロード指示によシ入力データレ
ソスタ1にセットされデータ組み替え回路7の出力と排
他的論理和回路5で排他的論理和が取られ出力データ・
ライン13に出力される。
(2) If the input data can be encrypted here, the input data is set in the input data register 1 according to the load instruction from the control circuit 8, and is exclusively processed by the output of the data recombination circuit 7 and the exclusive OR circuit 5. The logical OR is taken and the output data is
It is output on line 13.

(3)  このとき入力選択回路6は制御回路8の選択
指示により出力データ・ライン13を選択しであるので
出力データは同時に制御回路8のロード指示によシ暗号
化入力データレジスタ2にセットされる。セットが完了
すると暗号化回路3によシ暗号化しておく・ (4)データ組み替え回路7は暗号化回路3から入力さ
れる暗号化データを制御回路8のロード指示によシシフ
トレジスタ9にセットし制御回路8の出力指示により逐
次排他的論理和回路5に出力する。排他的論理和回路5
は該暗号化データと入力データレジスタ1のデータとの
排他的論理和演算を行ない出力データ・ライン13に出
力する。
(3) At this time, the input selection circuit 6 selects the output data line 13 according to the selection instruction from the control circuit 8, so the output data is simultaneously set in the encrypted input data register 2 according to the load instruction from the control circuit 8. Ru. When the setting is completed, the encryption circuit 3 encrypts the data. (4) The data recombination circuit 7 sets the encrypted data input from the encryption circuit 3 to the shift register 9 according to the load instruction from the control circuit 8. The output signal is sequentially output to the exclusive OR circuit 5 according to an output instruction from the control circuit 8. Exclusive OR circuit 5
performs an exclusive OR operation on the encrypted data and the data in the input data register 1, and outputs the result to the output data line 13.

出力データが図示せぬ他の回路で正常に受は取られると
シフトレノスタ9の最上位ビットHeインバータ回路1
0で反転し最下位ビア)(L)とする循環シフトが行な
われ他の暗号化データが求められ上記同様入力データと
排他的論理和演算され出力データ・ライン13に出力さ
れる。この様にして暗号化回路3から出力された単一の
暗号化データから64種の異った暗号化データを得て暗
号化を行なうとデータ組み替え回路7は制御回路8に終
了指示を与え、すでに(3)で用意されている次の暗号
化のためのデータ(暗号化回路3の出力)を制御回路8
0ロード指示により再びシフトレノスタ9にセットし前
記同様にして入力データの暗号化を進めていく。
When the output data is normally received by another circuit (not shown), the most significant bit He inverter circuit 1 of the shift reno star 9
A cyclic shift is performed to invert the bit by 0 and set it to the lowest via) (L) to obtain other encrypted data, which is subjected to an exclusive OR operation with the input data in the same manner as described above and is output to the output data line 13. When 64 types of different encrypted data are obtained from the single encrypted data outputted from the encrypting circuit 3 in this way and encrypted, the data recombination circuit 7 gives a termination instruction to the control circuit 8, The data for the next encryption (output of the encryption circuit 3) already prepared in (3) is sent to the control circuit 8.
In response to the 0 load instruction, the shift recorder 9 is set again, and the input data is encrypted in the same manner as described above.

復号化処理は復号化処理中入力選択回路6を入力データ
選択にすることによシ暗号化処理と全く同じ動作を行え
ば良い。
The decryption process may perform exactly the same operation as the encryption process by setting the input selection circuit 6 to select input data during the decryption process.

以上の如く暗号化、復号化が実行されるが第2図中のデ
ータ組み替え回路7の実施例ではシフトレジスタ9を用
いたが64ビツトのデータを多数の相異なる64ビツト
のデータに変換する機能をもったものであれば利用が可
能である。第3図にはROM (読出し専用メモリ)を
使ったデータ組み替え回路の例を示す。ここで14は6
4ビットルノスタ、15はカウンタ、16は変換用RO
M 。
Encryption and decoding are executed as described above, and although the shift register 9 is used in the embodiment of the data recombination circuit 7 in FIG. 2, it has the function of converting 64-bit data into a large number of different 64-bit data. It can be used if it has the following. FIG. 3 shows an example of a data recombination circuit using ROM (read-only memory). Here 14 is 6
4-bit Runo Star, 15 is counter, 16 is conversion RO
M.

Iノは前記制御回路である。I is the control circuit.

入力されfc64ビットはレジスタ14にセット出力指
示によシ出力される。このとき出力データとカウンタ1
5の値がROM 16のアドレスとして示えられそのア
ドレスのROMデータが再度レジスタ14に入力される
。あらかじめ決められている回数出力すると制御回路4
は終了を出力する。ここでカウンタ15の出力をROM
アドレスとして加えることにより同じ出力データに対し
て同じ値を再入力しないようにし・母ターンのくシ返し
をさけている。又、当然ROMの代シにRAM (書込
み可能メモリ)を用いても良い。
The input fc64 bit is output to the register 14 in response to a set output instruction. At this time, output data and counter 1
The value 5 is indicated as the address of the ROM 16, and the ROM data at that address is input into the register 14 again. After outputting a predetermined number of times, the control circuit 4
prints the end. Here, the output of counter 15 is stored in ROM.
By adding it as an address, we prevent the same value from being re-entered for the same output data and avoid repeating the mother turn. Also, of course, a RAM (writable memory) may be used in place of the ROM.

(発明の効果) 以上説明したように本発明によれば低速の暗号化ユニッ
トを用いて実質的に高速の暗号化復号化が可能となり高
速データ通信システムにも適用可能である。また暗号ア
ルゴリズムをファームウェアで実行するようなシステム
では速度の点でDESアルゴリズムの採用には問題があ
ったが本発明により十分実用可能となる。
(Effects of the Invention) As described above, according to the present invention, substantially high-speed encryption and decryption can be performed using a low-speed encryption unit, and it is also applicable to high-speed data communication systems. Furthermore, in systems where the cryptographic algorithm is executed by firmware, there was a problem in adopting the DES algorithm in terms of speed, but the present invention makes it fully practical.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のフィードバック構成の暗号装置、第2図
は本発明の一実施例のブロック図、第3図は他の実施例
のブロック図である。 !二人力データ・レジスタ、2:暗号化入力レジスタ、
3:暗号化回路、4:暗号出力レジスタ、5:排他的論
理和回路、6:入力選択回路、7:データ組み替え回路
、9:シフトレジスタ、10:インバータ、11:デー
タ組み替え回路の制御部、12:入力データ・ライン、
13:出力データ・ライン、14:レジスタ、15:カ
ウンタ、16:変換用ROM 。 特許出願人 沖電気工業株式会社
FIG. 1 is a block diagram of a conventional feedback configuration encryption device, FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is a block diagram of another embodiment. ! Two-person data register, 2: Encrypted input register,
3: Encryption circuit, 4: Encryption output register, 5: Exclusive OR circuit, 6: Input selection circuit, 7: Data recombination circuit, 9: Shift register, 10: Inverter, 11: Control unit of data recombination circuit, 12: Input data line,
13: Output data line, 14: Register, 15: Counter, 16: Conversion ROM. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 入力されるデータを暗号キイに基づき暗号化する暗号化
回路を有し、該暗号化回路から出力される暗号化データ
と暗号化したいデータとの排他的論理和を取り暗号デー
タとし、さらに該暗号データを上記暗号化回路の入力デ
ータとする帰還型暗号装置において、上記暗号化回路か
ら出力される単一の暗号化データから複数の相異なる暗
号化データを発生する手段を備え、1つの暗号化データ
から複数の暗号化データを得て暗号化することを特徴と
する暗号装置。
It has an encryption circuit that encrypts input data based on an encryption key, performs an exclusive OR of the encrypted data output from the encryption circuit and the data to be encrypted, and then generates the encrypted data. A feedback cryptographic device that uses data as input data to the encryption circuit, comprising means for generating a plurality of different encrypted data from a single encrypted data output from the encryption circuit, An encryption device characterized in that a plurality of pieces of encrypted data are obtained from data and encrypted.
JP58040580A 1983-03-14 1983-03-14 Ciphering device Pending JPS59167147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58040580A JPS59167147A (en) 1983-03-14 1983-03-14 Ciphering device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58040580A JPS59167147A (en) 1983-03-14 1983-03-14 Ciphering device

Publications (1)

Publication Number Publication Date
JPS59167147A true JPS59167147A (en) 1984-09-20

Family

ID=12584424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58040580A Pending JPS59167147A (en) 1983-03-14 1983-03-14 Ciphering device

Country Status (1)

Country Link
JP (1) JPS59167147A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6259437A (en) * 1985-09-10 1987-03-16 Oki Electric Ind Co Ltd Ciphering system
JPS63146535A (en) * 1986-07-24 1988-06-18 Meiji Milk Prod Co Ltd Method and apparatus for generating authentication data
JPS63237633A (en) * 1987-03-26 1988-10-04 Tokyo Electric Power Co Inc:The Secret communication system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6259437A (en) * 1985-09-10 1987-03-16 Oki Electric Ind Co Ltd Ciphering system
JPH0418734B2 (en) * 1985-09-10 1992-03-27 Oki Electric Ind Co Ltd
JPS63146535A (en) * 1986-07-24 1988-06-18 Meiji Milk Prod Co Ltd Method and apparatus for generating authentication data
JPH0453464B2 (en) * 1986-07-24 1992-08-26 Meiji Milk Prod Co Ltd
JPS63237633A (en) * 1987-03-26 1988-10-04 Tokyo Electric Power Co Inc:The Secret communication system

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