JP2587105B2 - Switching output circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a switching output circuit.

[Conventional technology]

FIG. 9 is a circuit diagram showing a switching output circuit used for a conventional TTL. Input terminal IN is connected to the base of an NPN transistor Q _4. The emitter of the NPN-type transistor Q ₄ are connected to the ground level GND via the resistor R _1. The collector of NPN type transistor Q ₄ are current supplying means I _C
To one end. The other end of the current supply means I _C is connected to a voltage source V _CC for supplying power to this circuit. Base of an NPN transistor Q ₅ is an NPN transistor
The collector of Q _4, collector connected to a voltage source V _CC, an emitter connected to the ground level GND via a resistor R _2. N
Based PN-type transistor Q ₆ to the emitter of NPN type transistor Q _5, the collector is connected to a voltage source V _CC. The base of the NPN-type transistor Q ₇ is connected to the emitter of NPN type transistor Q _4, the collector is connected to the ground level GND. The emitter and collector of NPN type transistor Q ₇ of the NPN type transistor Q ₆ is connected to the output terminal OUT in common.

Next, the operation will be described. First, the voltage V is applied to the input terminal IN.
_{BE (OFF)} if (base-emitter voltage of the NPN transistor Q ₄ is turned OFF state) is applied, an NPN transistor Q _4, Q ₇ is turned OFF, the NPN transistor Q _5, Q ₆ is turned ON , And the output terminal OUT is in the H state.

The voltage V _{BE (ON)} is applied to the input terminal IN (NPN transistor Q ₄ is ON
Is applied, the NPN transistors Q ₄ and Q ₇ are turned on, the NPN transistors Q ₅ and Q ₆ are turned off, and the output terminal OUT becomes L state.

When the voltage V _{BE (ON)} and V _{BE (OFF)} are alternately applied to the input terminal IN, the voltage of the input terminal IN and the ON of the NPN transistor Q ₇
/ OFF state, the NPN transistor from ON / OFF state and the voltage source V _CC of an NPN transistor Q ₆ Q _6, through Q ₇ ground level GN
The waveform of the through current I _S that flows into the D respectively shown in the timing chart of FIG. 10.

When the applied voltage of the input IN changes from the voltage V _{BE (OFF)} to the voltage V _{BE (ON)} , the NPN transistor Q ₇ changes from the OFF state to the ON state, and the NPN transistor Q ₆ changes from the ON state to the OFF state. I do. In general, when a transistor changes from an ON state to an OFF state, a delay time is generated due to accumulated charge of a base. Resistors R ₁ and R ₂ are added to discharge the base accumulated charge. The power consumption increases when the resistance values of the resistors R ₁ and R ₂ are reduced, and the delay time increases when the resistance values are increased.

In the timing chart of FIG.
After changing from V _{BE (OFF)} to the voltage V _{BE (ON),} NPN type transistor Q ₆ is rendered conductive for some time by the delay time. Voltage source V
Through the NPN type transistor Q _6, Q ₇ from _CC to ground level GND through current I _S flows. Also, when the applied voltage of input IN is voltage V
Similarly, after the change from _{BE (ON)} to the voltage V _{BE (OFF),} flows through current I _S becomes conductive NPN type transistor Q ₇ is a while. This through current I _S is performed a high-speed operation, further increases in proportion to the number of switching operations.

[Problems to be solved by the invention]

Because the conventional switching output circuit is configured as described above, power consumption is increased because the through current I _S, there is a problem that further power consumption increases in the high-speed operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a switching output circuit that has little through current even when a switching operation is performed at a high speed and that consumes less power.

[Means for solving the problem]

The switching output circuit according to the present invention includes first and second power supply lines each having a relatively high potential and the other having a relatively low potential, and first, second, and second power supply lines connected to the first power supply line. Third current supply means, an input terminal,
A first transistor having a base connected to the input terminal, an emitter connected to the second power supply line, a collector connected to the first current supply means, a base connected to the input terminal, and an emitter connected to the second power supply line; In the line, connect the collector to the second
A second transistor connected to the current supply means, a third transistor having a base connected to the collector of the first transistor, an emitter connected to the second power supply line, and a base connected to the second transistor. To the collector of
A fourth transistor connected to the third current supply means, a base connected to the collector of the fourth transistor, an emitter connected to the collector of the third transistor, and a collector connected to the first power supply line. A connected fifth transistor, a base connected to the emitter of the fifth transistor, a collector connected to the first power supply line, a sixth transistor connected to the base, and a base connected to the emitter of the fourth transistor; A seventh transistor connected to the second power supply line, and an output terminal commonly connected to an emitter of the sixth transistor and a collector of the seventh transistor. The supply current of the current supply means is larger than the supply currents of the second and third current supply means.

[Action]

The first and second current supply means according to the present invention include:
The period during which the third and fourth transistors are turned on and off is controlled, and the period during which the sixth and seventh transistors are turned on at the same time is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a switching output circuit according to one embodiment of the present invention. Input terminal IN is NPN transistor Q
_1, is connected in common to the base of Q _2. NPN transistor
The emitters of Q ₁ and Q ₂ are connected to ground level GND. The collector of NPN type transistor Q ₁ is at one end of the current supply means I _A consisting of a constant current source, the collector of NPN type transistor Q ₂ is connected to one end of the current supply means I _B consisting of a constant current source. Current supplying means I _A, the other end of I _B is connected to a voltage source V _CC. Base of an NPN transistor Q ₃ is an NPN transistor
The collector of Q _1, the emitter is connected to the ground level GND. Base of an NPN transistor Q ₄ is an NPN transistor
The collector of Q _2, the emitter to the base of an NPN transistor Q _7, the collector is connected to one end of the current supply means I _C consisting constant current source. The other end of the current supply means I _C and the voltage source V
Connected to _CC . The base of the NPN-type transistor Q ₅ to the collector of an NPN transistor Q _4, the emitter to the collector of an NPN transistor Q _3, a collector is connected to a voltage source V _CC. The base of the NPN-type transistor Q ₆ to the emitter of NPN type transistor Q _5, the collector is connected to a voltage source V _CC. Base of an NPN transistor Q ₇ is an NPN transistor
The emitter of Q _4, the emitter is connected to the ground level GND. The emitter and collector of NPN type transistor Q ₇ of the NPN type transistor Q ₆ is connected to the output terminal OUT in common.

Next, the operation will be described. First, the voltage V is applied to the input terminal IN.
_{BE (OFF)} if (base-emitter voltage of an NPN transistor Q _1, Q ₂ becomes OFF state) is applied, an NPN transistor Q _1, Q ₂ are turned OFF, the NPN transistor Q _3, Q ₄ ,
Q ₇ is turned ON, NPN type transistor Q _5, Q ₆ is turned OFF, the output terminal OUT is in the L state.

Voltage V _{BE (ON)} (NPN transistors Q ₁ , Q ₂
NPN transistors Q ₁ and Q ₂ are in the ON state, NPN transistors Q ₃ , Q ₄ and Q ₇ are in the OFF state, and NPN transistors Q ₅ and Q ₆
Becomes ON state, and the output terminal OUT becomes H state.

When the voltages V _{BE (ON)} and V _{BE (OFF)} are alternately applied to the input terminal IN, the voltage at the input terminal IN and the NPN transistors Q ₁ and Q
_2, Q _3, the Q _4, Q ₆ and the ON / OFF state of the Q _7, the through current I _S from the voltage and a voltage source V _CC for output OUT through the NPN type transistor Q _6, Q ₇ flows to the ground level GND The waveform is shown in the timing chart of FIG.

In general, when a transistor changes from an ON state to an OFF state, a delay time is generated due to accumulated charge of a base. FIG. 2 shows the state of each transistor, considering only the delay time when the transistor changes from the ON state to the OFF state and ignoring the delay time when the transistor changes from the OFF state to the ON state.

The voltage applied to the input terminal IN is the voltage at the time T _S
The voltage changes from V _{BE (OFF)} to the voltage V _{BE (ON),} and changes at time _{TF from} the voltage V _{BE (ON)} to the voltage V _{BE (OFF)} . An NPN transistor Q ₁ is made from the OFF state to the ON state at the time T _S, after further delay time T ₁ elapses from the time T _F, OFF from ON state
State. The NPN-type transistor Q ₃ are after the delay time T ₃ has elapsed from the time T _S, made from the ON state to the OFF state, after a slightly longer delay time T _1A elapsed since the delay time T ₁ from the time T _F, the OFF state Turns on.

NPN type transistor Q ₂ is, similarly to the NPN type transistor Q _1, made from an OFF state to an ON state at time T _S, the time T _F
After the delay time T ₂ has elapsed since consists ON state and OFF state. An NPN transistor Q ₄ are, like the NPN type transistor Q _3, after a lapse of the delay time T ₄ from the time T _S, OF from ON state
It becomes F state, after a lapse of a slightly longer delay time T _2B than the delay time T ₂ from the time T _F, made from an OFF state to an ON state.

The NPN transistors Q ₅ and Q ₆ are Darlington connected. When the NPN transistor Q ₄ is ON, the base potential of the NPN transistor Q ₅ drops and the NPN transistor Q ₅
Both of Q _5, Q ₆ in an OFF state. Further, when the NPN-type transistor Q ₃ is turned ON, lower the base potential of the NPN type transistor Q _6, an NPN transistor Q ₆ is turned OFF. That NPN type transistor Q _6, after approximately equal delay time T _6S elapsed from the time T _S and longer of the delay time T _3, T _4, made from an OFF state to an ON state. The NPN-type transistor Q _6, the time T _F from the delay time T _1A, after shorter the delay time T _6F course which is determined in relation ones of T _2B, composed of ON state and OFF state. The delay time T _6F includes a specific delay time of an NPN transistor Q _6.

An NPN transistor Q _7, after a lapse of a delay time given by the sum of the time T _S and the delay time T ₄ with the delay time T _7S, consisting of ON state and OFF state. This delay time T _7S is NP
A time required to discharge the stored charge in the base of N type transistor Q _7, related to the base-emitter junction capacitance of the NPN type transistor Q _7. The NPN-type transistor Q _7, after a lapse of the delay time T _7F from the time T _F, made from the OFF state to the ON state. An NPN transistor Q ₇ is, an NPN transistor Q ₄ since during the OFF state does not become ON state, the delay time T _7F is substantially equal to the delay time T _2B.

The output voltage OUT is determined by the ON / OFF state of the NPN type transistor Q _6, Q _7. From time T _S + T _6S to time T _S + T ₄ + T
_In the period up to _7S , NPN on the timing chart
The transistors Q ₆ and Q ₇ are both in the ON state, but are actually in the transient state including a minute period before and after this, and during this period, the output voltage OUT increases and changes from the L state to the H state. . Similarly, in the period from time _TF + _T7F to time _TF + _T6F , the output voltage OUT decreases and changes from the H state to the L state.

Therefore, in FIG. 2, from time T _S + T _6S to time T _S + T ₄
In + T period from the period and time T _F + T _7F up _7S to time T _F + T _6F, NPN type transistors Q _6, Q ₇ there is a time period while both turned ON. Thus, although the through current I _S that flows from the voltage source V _CC to ground level GND through the NPN type transistor Q _6, Q ₇ is present, the period in comparison with the conventional example shown in FIG. 10 is relatively short Through current I _S
Decreases.

In the present embodiment, by increasing the supply current of the current supply means I _A, during one of the transistors of the NPN type transistor Q _6, Q ₇ is in the OFF state, the OFF state other transistor from ON state Alternatively, a transition from the OFF state to the ON state is made, that is, in FIG. 2, T _6S > T
₄ + T _7S and T _6F <T _7F
By adjusting the ON / OFF timing of an NPN transistor Q _6, Q _7, we can further reduce the through current I _S.

Increasing the current from the current supply means I _A, since the base accumulated charge amount base current of the NPN type transistor Q ₃ is increased to increase the delay time at the time of change from the ON state of the NPN type transistor Q ₃ to the OFF state T ₃ is increased as the delay time T ₃ '. For this reason, the delay time of an NPN transistor Q ₆ T
_6S also increases like the delay time T _6S ′. As a result, T _6S
> T ₄ + T _7S is satisfied, and the through current I _S is minimized.

The base potential rise speed of the NPN type transistor Q ₃ is faster at the time of change from the OFF state of the NPN type transistor Q ₃ to the ON state, the delay time T _1A is further reduced. Thus, the base is an NPN transistor of NPN type transistor Q ₆
By Q _3, also decreases the delay time T _6F because it is shorted to the earlier forcibly ground level GND. As a result, T _6F
The condition of < _T7F is satisfied, and the through current I _S is minimized.

In other words, Datosuruto ON / OFF timing of an NPN transistor Q ₇ is constant, slow the timing when the ON state of the NPN type transistor Q ₆ by increasing the current of the current supply means I _A, can quickly timing turned OFF Therefore, it further reduces the through current I _S. In this case, the current supply means
I _A current current supply unit I _B of may be set to be larger than the current I _C.

FIG. 3 is a circuit diagram showing a switching output circuit according to another embodiment of the present invention. In this embodiment, an NPN transistor Q ₈ to facilitate the turn-off of the NPN type transistor Q ₇ is provided. The base of the NPN-type transistor Q ₈ is connected to the input terminal IN. The emitter of the NPN-type transistor Q ₈ is connected to the ground level GND, the collector is connected to the base of an NPN transistor Q _7. Other configurations are the same as those of the switching output circuit shown in FIG.

Next, the operation will be described. First, the voltage V is applied to the input terminal IN.
_{BE (OFF)} if (base-emitter voltage of an NPN transistor Q _1, Q _2, Q ₈ is turned OFF) is applied, an NPN transistor Q _1, Q _2, Q ₈ is turned OFF, the NPN Transistor
Q ₃ , Q ₄ , Q ₇ are ON, NPN transistors Q ₅ , Q ₆ are OFF, and output terminal OUT is L.

Voltage V _{BE (ON)} (NPN transistor Q ₁ ,
If Q _2, Q base-emitter _{voltage 8} is turned ON) is applied, NPN type transistors Q _1, Q _2, Q ₈ is ON state, N =
The PN transistors Q ₃ , Q ₄ , and Q ₇ are turned off, the NPN transistors Q ₅ and Q ₆ are turned on, and the output terminal OUT goes to the H state.

When the voltages V _{BE (ON)} and V _{BE (OFF)} are alternately applied to the input terminal IN, the voltage at the input terminal IN and the NPN transistors Q ₁ and Q
₂ , Q ₃ , Q ₄ , Q ₆ , Q ₇ and Q ₈ ON / OFF state, output OUT voltage and through current I flowing from the voltage source V _CC to ground level GND via NPN type transistors Q ₆ and Q ₇ The waveform of _S is shown in the timing chart of FIG.

In FIG. 4, as in FIG. 2 described above, only the delay time when the transistor changes from the ON state to the OFF state is considered, and the delay time when the transistor changes from the OFF state to the ON state is ignored. The state of each transistor is shown.

The voltage applied to the input terminal IN is the voltage at the time T _S
The voltage changes from V _{BE (OFF)} to the voltage V _{BE (ON),} and changes at time _{TF from} the voltage V _{BE (ON)} to the voltage V _{BE (OFF)} . An NPN transistor Q ₁ is made from the OFF state to the ON state at the time T _S, after further delay time T ₁ elapses from the time T _F, OFF from ON state
State. The NPN-type transistor Q ₃ are after the delay time T ₃ has elapsed from the time T _S, made from the ON state to the OFF state, after a slightly longer delay time T _1A elapsed since the delay time T ₁ from the time T _F, the OFF state Turns on.

NPN type transistor Q ₂ is, similarly to the NPN type transistor Q _1, made from an OFF state to an ON state at time T _S, the time T _F
After the delay time T ₂ has elapsed since consists ON state and OFF state. An NPN transistor Q ₄ are, like the NPN type transistor Q _3, after a lapse of the delay time T ₄ from the time T _S, OF from ON state
It becomes F state, after a lapse of a slightly longer delay time T _2B than the delay time T ₂ from the time T _F, made from an OFF state to an ON state.

An NPN transistor Q _8, from the OFF state at the time T _S
Becomes the ON state, after a lapse of delay time T _X from the time T _F, made from the ON state to the OFF state. The delay time T _X can be adjusted by including an NPN transistor size of Q _8, the structure as described below.

The NPN transistors Q ₅ and Q ₆ are Darlington connected. When the NPN transistor Q ₄ is ON, the base potential of the NPN transistor Q ₅ drops and the NPN transistor Q ₅
Both of Q _5, Q ₆ in an OFF state. Further, when the NPN-type transistor Q ₃ is turned ON, lower the base potential of the NPN type transistor Q _6, an NPN transistor Q ₆ is turned OFF. That NPN type transistor Q _6, after approximately equal delay time T _6S elapsed from the time T _S and longer of the delay time T _3, T _4, made from an OFF state to an ON state. The NPN-type transistor Q _6, the time T _F from the delay time T _1A, after shorter the delay time T _6F course which is determined in relation ones of T _2B, composed of ON state and OFF state. The delay time T _6F includes a specific delay time of an NPN transistor Q _6.

An NPN transistor Q _7, after a lapse of delay time T _7S from the time T _S, made from the ON state to the OFF state. This delay time T _7S
A time required to discharge the stored charge in the base of an NPN transistor Q _7, relating the base-emitter junction capacitance of the NPN type transistor Q _7, in the ON resistance when conducting the NPN type transistor Q ₈ . The size of the NPN type transistor Q ₈ as the delay time T _7S described later, can be adjusted by such structure. The NPN-type transistor Q _7, after a lapse of the delay time T _7F from the time T _F, made from the OFF state to the ON state.
An NPN transistor Q _7, since an NPN transistor Q ₈ is between and an NPN transistor Q ₄ in the ON state does not become the ON state during the OFF state, the delay time T _7F delay time T _2B, among the T _X Is approximately equal to the longer one.

The output voltage OUT is determined by the ON / OFF state of the NPN type transistor Q _6, Q _7. In the period from time T _S + T _7S to time T _S + T _6S , the NPN transistors Q ₆ and Q ₇ are both OFF in the timing chart, but are actually in a transient state, during which the output voltage OUT increases. Then, the state changes from the L state to the H state. Similarly, in the period from the time _TF + _T6F to the time _TF + _T7F , the output voltage OUT decreases and changes from the H state to the L state.
State.

In this embodiment, as shown in FIG. 4, the circuit is configured so that there is no period during which both the NPN transistors Q ₆ and Q ₇ are completely conductive. The method of the adjustment will be described later. Therefore, from the voltage source V _CC to the NPN transistor
The through current I _S flowing to the ground level GND via Q ₆ and Q ₇ is minimized.

The state in which the through current is minimized is that one of the NPN transistors Q ₆ and Q ₇ is in the OFF state while the other transistor is in the OFF state from the ON state or is in the O state.
It will be maintained if the state changes from the FF state to the ON state. That is, in FIG. 4, it is sufficient that T _6S > T _7S and T _7F > T _6F . Further, the greater the difference between the delay times is, the more stable the through current minimum state becomes.

Next, the delay times T _6S , T _7S and the delay times T _6F , T
A method for increasing the difference between the _7F and stabilizing the through current minimum state will be described. First, the current supply means I _A
Increasing the current from, OFF of the NPN type transistor Q ₃
When changing from the ON state to the ON state, the NPN transistor Q ₃
Of the base potential increases, and the delay time T _1A decreases. Also at the time of transition from the ON state to the OFF state, since the base accumulated charge amount of the NPN type transistor Q ₃ is increased, it increases the delay time T _3. Thus an NPN transistor Q ₆ is affected by this, slow timing becomes ON state (T _6S is large), the timing becomes OFF state becomes faster (T _6F is small).

Further, as well as increasing the current from the current supply means I _B, timing becomes ON state of the NPN type transistor Q ₄ are quickly (T _2B is small), slow timing becomes OFF state (T ₄ is greater) Become. For this reason, NPN transistors
For Q _5, Q _6, timing becomes ON state is slow, OF
The timing to enter the F state is earlier. That, NPN type transistor Q _6, the delay time T _6S is large, the delay time T _6F decreases.

In any case, NPN type transistor Q ₇ of the ON /
Assuming that the OFF timing is constant, the NPN transistor Q ₆
Since the ON timing is late and the OFF timing is early, it is easy to maintain the through current minimum state.

The current supply unit I _A, without increasing the amount of current I _B,
Or in addition to these increases, the size of the NPN type transistor Q _8, be varied structure through current minimum state can be stabilized.

FIG. 5 is a sectional view showing an example of a structure of an NPN transistor Q _8. In the figure, substrate 1, isolation region 2, collector layer
The base region 4, the emitter region 5, the collector diffusion layer 6, the collector electrode 7, the base electrode 8, and the emitter electrode 9 constitute a normal transistor. Further, the substrate-collector interlayer buried high impurity concentration layer 10 and the collector electrode 7 are connected by a layer having a higher impurity concentration than the collector layer 3 (collector wall diffusion layer 11). According to this structure, since the base accumulated charge amount increases, OFF of the NPN type transistor Q ₈
The timing to enter the state is late, and the equivalent resistance value between the collector and the emitter at the time of ON decreases.
_The timing of the OFF state of ₇ becomes earlier. Datosuruto timing of the ON / OFF state of the NPN transistor Q ₆ is constant,
Timing becomes ON state of the NPN type transistor Q ₇ is slow, since Taimigu the faster becomes the OFF state, it is easy to hold the through current minimum state.

Further, in this structure, the base accumulated charge increases as the temperature rises and decreases as the temperature falls. That the temperature rises, the timing becomes the OFF state of the NPN type transistor Q ₈ is slow, timing becomes ON state is faster. Therefore, the through current is further reduced, and the heat generation of the entire chip is suppressed.

On the other hand, increasing the base-emitter junction area by increasing the size of the NPN type transistor Q _8,
The collector-emitter equivalent resistance at ON decreases and the NPN
Base charges accumulated in the form transistor Q ₇ can be discharged more quickly. Therefore delay time T _7S becomes smaller, timing at which the OFF state of the NPN transistor Q ₇ is faster.

Further, the junction capacitance between the base and the emitter in accordance with the increase in the size, the collector-base junction capacitance, the parasitic capacitance such as a junction capacitance between the collector and the substrate is increased, slow timing becomes OFF state of the NPN type transistor Q ₈ Become. Therefore, the delay times T _X and T _7F become large, and the NPN transistor Q ₇
Is turned on later. Datosuruto constant ON / OFF timing of an NPN transistor Q ₆ is delayed timing becomes ON state of the NPN type transistor Q _7, since the timing at which the OFF state becomes faster, more easily hold the through current minimum state.

As described above, the current supply means I _A, or by increasing the current I _B, the size of the NPN type transistor Q _8, by performing the adjustment or suitably change the structural, easy to hold the through current minimum state Become. In addition, since these adjustments are independent, by applying these adjustments alone or in any combination to the switching output circuit, each effect can be synergistically contributed, and the through current minimum state is further maintained. Easier to do.

Actually, also flows through current I _S slightly in a period in which the NPN-type transistor Q _6, Q ₇ are both OFF state, the effect does not increase even if too therefore increase this period. But,
By performing the adjustment as described above, a through current I _S to optimize the length of this period can be minimized.

Figure 6 is when the current I _A, the I _B as a parameter, the input IN
T after the output voltage changes, the output voltage OUT, and the through current I _S
6 is a graph showing a relationship with the graph. When the current I _A, the I _B increases, the through current I _S is significantly reduced.

Figure 7 is a base-emitter junction area S of the NPN type transistor Q ₈ when a parameter, a graph showing the relationship between the time T after the input IN is changed and the output voltage OUT and the through current I _S is there. The junction area S is increased, the through current I _S is significantly reduced.

FIG. 8 is a circuit diagram showing still another embodiment of the switching output circuit according to the present invention. In this embodiment, the to advance the timing of the NPN type transistor Q ₇ at turn-off of the NPN type transistor Q ₇ becomes nonconductive
As turn-off promotion means from the base of an NPN transistor Q ₇ discharges the electric charge, it is connected in place of the NPN type transistor Q ₈ shown in Figure 3, the resistor R _a between the base and emitter of the NPN-type transistor Q ₇ . However, in the case of using the NPN-type transistor Q _8, due control of the base voltage, when it discharge time base stored charge of the NPN type transistor Q ₇ can be adjusted, using resistance R _a, the discharge Time is constant.

In the above embodiment, the circuit is constituted by NPN transistors, but the circuit can be constituted by PNP transistors or a combination of both. In the case of using a PNP type transistor, the transistor Q ₈ or resistance
Off facilitating means consisting of R _a is operative to charge the base charge in transistor Q _7.

〔The invention's effect〕

The present invention is configured as described above, and has the following effects. According to the switching output circuit of the first aspect, the first and second current supply means control the time when the third and fourth transistors are turned on and off, and the sixth and seventh transistors are simultaneously turned on. Since the conduction period is shortened, there is almost no through current even when the switching operation is performed at a high speed, power consumption can be suppressed, and the supply current of the first current supply means is reduced by the second and the second current supply means. Since the supply current is larger than the supply current of the third current supply means, it is possible to further reduce the through current and suppress the power consumption.

According to the switching output circuit of the second aspect, the turn-off promoting means hastens the timing at which the seventh transistor becomes non-conductive, so that the through current can be further reduced and the power consumption can be suppressed.

According to the switching output circuit of the third aspect, since the eighth transistor is provided as the turn-off promoting means, the period during which the through current flows can be controlled.

According to the switching output circuit of the fourth aspect, since the resistor is provided as the turn-off promoting means, the period during which the through current flows can be controlled.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a switching output circuit according to one embodiment of the present invention, FIG. 2 is a timing chart showing waveforms of respective parts of the switching output circuit shown in FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a timing chart showing waveforms of respective parts of the switching output circuit shown in FIG. 3, FIG. 5 is a cross-sectional view showing a structure of a transistor to which a collector wall is applied, and FIG. 7 is a timing chart showing changes in output voltage and through current, FIG. 8 is a circuit diagram showing a switching output circuit according to still another embodiment of the present invention, and FIG. 9 is a conventional switching output circuit. FIG. 10 is a circuit diagram, and FIG. 10 is a timing chart showing waveforms at various parts of the switching output circuit shown in FIG. In FIG, Q ₁ to Q ₈ is an NPN transistor, I _A, I _B and I _C is the current supply means, IN is an input terminal, OUT is an output terminal, V
_CC is a voltage source, GND is a ground level, and _Ra is a resistor. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

(57) [Claims] 1. A first and second power supply line, one of which supplies a relatively high potential and the other a relatively low potential, and first, second and third power supply lines connected to the first power supply line.
A first transistor connected to the input terminal, a base to the input terminal, an emitter to the second power supply line, a collector to the first current supply means, and a base to the input terminal. A second transistor having a terminal connected to the second power supply line, a collector connected to the second current supply means, a base connected to the collector of the first transistor, and an emitter connected to the second power supply line. A third transistor connected to a line, a base connected to the collector of the second transistor, a collector connected to the third current supply means, and a base connected to the collector of the fourth transistor. A fifth transistor having an emitter connected to the collector of the third transistor, a collector connected to the first power supply line, and a base connected to the fifth power supply line. A sixth transistor having a collector connected to the first power supply line, a base connected to the emitter of the fourth transistor, and a sixth transistor connected to the emitter of the fourth transistor and an emitter connected to the second power supply line. And an output terminal commonly connected to the emitter of the sixth transistor and the collector of the seventh transistor. The supply current of the first current supply means is controlled by the second and the third transistors. A switching output circuit which is larger than a supply current of the third current supply means. 2. A first and second power supply line, one of which supplies a relatively high potential and the other a relatively low potential, and first, second and third power supply lines connected to the first power supply line.
A first transistor connected to the input terminal, a base to the input terminal, an emitter to the second power supply line, a collector to the first current supply means, and a base to the input terminal. A second transistor having a terminal connected to the second power supply line, a collector connected to the second current supply means, a base connected to the collector of the first transistor, and an emitter connected to the second power supply line. A third transistor connected to a line, a base connected to the collector of the second transistor, a collector connected to the third current supply means, and a base connected to the collector of the fourth transistor. A fifth transistor having an emitter connected to the collector of the third transistor, a collector connected to the first power supply line, and a base connected to the fifth power supply line. A sixth transistor having a collector connected to the first power supply line, a base connected to the emitter of the fourth transistor, and a sixth transistor connected to the emitter of the fourth transistor and an emitter connected to the second power supply line. A seventh transistor, which is connected between the base of the seventh transistor and the second power supply line, so that when the seventh transistor is turned off, the timing at which the seventh transistor becomes non-conductive is advanced. A switching output circuit comprising: turn-off promoting means for charging or discharging the base of the seventh transistor; and an output terminal commonly connected to an emitter of the sixth transistor and a collector of the seventh transistor. . 3. The turn-off promoting means includes an eighth transistor having a base connected to the input terminal, an emitter connected to the second power supply line, and a collector connected to the base of the seventh transistor. A switching output circuit as described. 4. The switching output circuit according to claim 2, wherein said turn-off promoting means includes a resistor having one end connected to said second power supply line and the other end connected to a base of said seventh transistor.