JP2586234B2 - Correlation arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlation calculating device used for obtaining a motion vector of an image of an image pickup device or the like.

[0002]

2. Description of the Related Art As an example using a conventional correlation operation device,
There is one disclosed in JP-A-2-241188.
FIG. 7 is a block diagram of the correlation operation device, wherein 1 is a latch A, 2 is a representative point storage memory, 3 is a latch B, 4 is a subtractor, 5 is an address controller, 6 is an absolute value conversion circuit,
7 is a cumulative adder, 8 is a minimum address determiner, and 9 is an upper bit reduction circuit. Hereinafter, this operation will be described. The input image data is processed by the upper bit deletion circuit.
The upper bit is deleted, and this output becomes the timing pulse L
The data is taken into the latch A1 by P1 and written into the address corresponding to each representative point in the representative point storage memory 2 at a certain timing. And in the next frame,
The difference between the image data in the motion vector detection area around the position of each representative point and the image data of the representative point of the previous field stored in the representative point memory 2 is calculated, and the absolute value conversion circuit 6 calculates the difference. The absolute value is taken and input to the accumulator 7.
The accumulative adder 7 accumulates data obtained by taking the absolute value difference at the position where the coordinate position with respect to the representative point is the same. Then, when the cumulative addition around all the representative points is completed, the location having the minimum value of the cumulative added value stored in the cumulative adder 7 is determined by the minimum address determiner 8. In the correlation judgment based on the difference absolute value, the smaller the location of the image correlation, the smaller the value. Therefore, the minimum value based on the position of the representative point corresponds to the motion vector, and the minimum value is obtained. .

[0003]

However, in the above-described conventional correlation operation apparatus, when the motion vector is obtained, the high-order bits are reduced to reduce the size of the circuit. Then, a problem occurs that an overflow occurs in the output of the absolute value conversion circuit 6.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide the following devices 1) and 2). 1) At least an input circuit for inputting a digitized image signal, a filter for removing low-frequency components of the image signal, and a peak value for detecting a peak value of an output signal from the filter. A detecting circuit, a multiplying circuit for multiplying the image signal by a predetermined number according to the peak value, a holding circuit for holding the predetermined number, and a lower order for deleting lower bits of the image signal obtained by the multiplying circuit A bit elimination means, a representative point memory circuit for storing a representative point based on an output signal of the lower bit elimination means, one or more fields after the image signal, and multiplied by the predetermined number and the identification number; A correlation calculation device comprising: a correlation calculation circuit that calculates a correlation between an image signal from which lower bits are deleted thereafter and the representative point stored in the representative point memory circuit.

2) At least an input circuit for inputting a digitized image signal, a filter for removing low-frequency components of the image signal, and a peak for detecting a peak value of an output signal from the filter. A value detecting circuit, a multiplying circuit for multiplying the image signal by a predetermined number according to the peak value, a lower bit removing means for removing lower bits of the image signal obtained by the multiplier circuit, and a lower bit removing means. A representative point memory circuit for storing a representative point based on an output signal of the means;
Correlation between the image signal, which arrives at least one field after the image signal, is multiplied by the predetermined number and the identification number, and then the lower bit is deleted, and the representative point stored in the representative point memory circuit. And a correlation operation circuit for calculating the following.

[0006]

The digital image signal coming from the input circuit is filtered to remove low-frequency components.
The peak value is detected by a peak value detecting circuit, a constant corresponding to the peak value is multiplied by the image signal in a multiplying circuit, and the lower bits of the image signal are deleted by lower bit deleting means, and the deleted signal is deleted. The representative point of the image signal is stored in a representative point memory circuit, and one point is obtained from the representative point and the image signal.
And the correlation is multiplied by the identification number and then the correlation with the image signal whose lower bits are reduced is calculated by a correlation calculation circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the correlation operation device according to the present invention will be described.
The details will be described below with reference to the drawings. FIG. 1 is a block diagram of a correlation operation device according to a first embodiment of the present invention.
22 is a filter circuit (high-pass filter), 24 is a multiplication circuit for increasing or decreasing the level of the input signal, 28 is a peak value detection circuit for detecting the peak value of the input signal, and 30 is a circuit for controlling each circuit in the apparatus. A system control circuit; 32, a latch circuit (holding circuit) for latching the multiplication rate determined by the system control circuit 30;
Circuits A and B, 36 for clipping upper bits of a signal of a predetermined level or higher from the
Reference numeral 7 denotes a memory control circuit for controlling the representative point memory circuit 36, and a correlation operation circuit 38.

Next, the operation of this configuration will be described. For example, when an 8-bit digitized image signal at the time of an N-field is input to the input circuit 20, the low-frequency component is removed by the filter circuit 22 of the next stage and the signal is converted into a 10-bit signal. The signals are supplied to the multiplication circuit 24 and the peak value detection circuit 28, respectively. The peak value detected by the peak value detection circuit 28 is supplied to a system control circuit 30, where a preset multiplication value is selected according to the peak value. The multiplied value data is latched by the latch circuit 32, and a switching signal based on the multiplied value is supplied to the multiplying circuit 24. An image signal branched from the filter circuit is supplied to the multiplying circuit 24. This image signal is multiplied according to each multiplied value by a circuit configuration to be described later. Are removed to form an 8-bit signal, which is supplied to the next-stage clip circuit A34. In the clipping circuit A34, when a signal of a predetermined level or more is input, the signal portion is clipped to prevent the lower bits from being input. The signal passed through the clipping circuit A34 is transferred to the next-stage representative point memory circuit 36.
Supplied to A write signal and an address signal are supplied to the representative point memory circuit 36 at a predetermined timing from a memory control circuit 37 controlled by the system control circuit 30, and these signals are used to determine each representative point of the incoming signal. Are sequentially stored at the addresses. Each of the stored representative points (at the time of the N field) is stored at the memory control circuit 3 at the time of the next field (at the time of N eleven fields) or more.
7 and supplied to one end of the correlation operation circuit 38.

On the other hand, the other end of the correlation operation circuit 38 is supplied with an image signal at the time of N eleven fields. The signal supplied to the other end is supplied to the multiplying circuit 24 after the image signal at the time of N eleven fields branches off the filter circuit 22 and is latched by the latch circuit 32 in synchronization with the timing. The supplied N-field multiplication data is supplied. In the multiplication circuit 24, a signal having the same multiplication rate as that at the time of the N-field is selected by the selector circuit by a circuit configuration described later, and the clipping circuit B40 of the next stage is selected.
Supplied to In the clipping circuit B40, similarly to the clipping circuit A34, when a signal of a predetermined level or more is input, the signal portion is reduced and supplied to the other end of the correlation operation circuit 38. . In the correlation operation circuit 38, the correlation operation between each representative point in the N field multiplied by the same ratio and the image signal in the N11 field is sequentially performed. After that, a motion vector is detected through a memory circuit, a minimum value detection circuit, and the like (not shown).

FIG. 2 shows the multiplication circuit 2 which is an essential part of the present invention.
4, the operation in the circuit will be described in detail with reference to FIG. The multiplying circuit 24 converts the image signal input from the filter 22 into a selector circuit A 24 a and a selector circuit B as it is.
Path with a multiplication factor of 1 to be supplied to the multiplication circuit 24b and the doubling circuit 24
c through the selector circuit A24a and the selector circuit B24.
b, a path of a multiplication factor of 2 to be supplied to
c and the signal from the filter 22 are added to an adder 24.
d to obtain a signal with a multiplication factor of 3 to obtain a selector circuit A2
4a and a path with a multiplication factor of 3 times supplied to the selector circuit B24b, and a signal from the filter 22 to a quadruple circuit 24e.
Selector circuit A24a and selector circuit B24b
And a path with a multiplication factor of 4 times that is supplied to. For example, when a signal having a peak value of 50% or more and 100% or less comes from the filter circuit 22 at the time of the N field,
The peak value is detected by the peak value detection circuit 28, and based on the peak value information, the system control circuit 3
From 0, a switching signal is supplied to the selector circuit A24a, a path having a multiplication factor of 1 is selected, and a signal having the same ratio as that at the time of input is output. The output side of this selector circuit A24a is 10
The terminal corresponding to the lower two bits of the bits is not connected, and the two bits are deleted here. However, in this case, since a signal having a peak value of 50% or more is received, even if the lower two bits are deleted, most of them are deleted. Since it is a noise component, it does not affect the SN ratio.

On the other hand, the multiplied value data at the time of the N field is latched by the latch circuit 32, and when a signal at the time of the N eleven fields comes in, the selector circuit B24b based on the data. Thus, a signal with a multiplication rate of 1 is extracted. In the selector circuit B24b, the selector circuit A24
Similarly to a, the output side is not connected to the terminal corresponding to the lower two bits of the ten bits, and the two bits are deleted here. Both signals (signals at the time of N fields and signals at the time of N eleven fields) output from the selector circuits A24a and B24b are multiplied by the multiplication circuit 2
At 4, the signals have the same ratio and are supplied to the correlation operation circuit 38 at the subsequent stage. In addition, for example, at the time of the N field, the peak value is 30% or more by the filter circuit 22.
When a signal of less than 0% is received, a switching signal is supplied from the system control circuit 30 to the selector circuit A24a so that a signal having a multiplication factor of 3 is selected. Similarly,
When a signal having a peak value of 25% or less arrives, a signal having a multiplication factor of 4 is selected.

FIG. 3 is a circuit configuration diagram of a multiplication circuit 24A obtained by modifying the multiplication circuit 24. The multiplication circuit 24 is of a variable bit shift type in which an adder 24d in the multiplication circuit 24 is removed.
In the case of this configuration, a path with a multiplication factor of 3 is eliminated, but the circuit can be made smaller.

The multiplying circuit 24 or the multiplying circuit 24
The output signal from A is supplied to the next-stage clipping circuit A34 and clipping circuit B40, as described above, so that a signal of a predetermined level or higher is clipped. FIG. 3 shows input / output characteristics when input from the multiplication circuit 24 and output from the clip circuit A34 or the clip circuit B40.

A non-linear circuit may be provided in place of the clipping circuit A34 or the clipping circuit B40, as shown in FIG. In this case, the signal in this portion can be used effectively without clipping the high-level signal.
Therefore, according to the present embodiment, even if the bits are reduced to reduce the circuit scale, the lower-order two-bit signals to be deleted by the multiplication circuits 24 and 24A are amplified in advance, so that the representative point memory circuit is used. The same signal as before the bit reduction is obtained without increasing the number of bits of 36,
The circuit scale after the representative point memory circuit 36 can be reduced.

FIG. 5 is a block diagram of a correlation operation device according to a second embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted. Particularly, in this embodiment, the latch circuit 32 and the clipping circuit A40 in the correlation operation device of the first embodiment are removed to further reduce the size. For example, an image signal at the time of N-field that has sequentially passed through the input circuit 20 and the filter circuit 22 is
The peak value is detected by the peak value detection circuit 28 and supplied to the system control circuit 30 at the next stage. In the system control circuit 30, a switching signal based on a multiplied value set in advance according to the peak value is supplied to the multiplying circuit 24. An image signal branched from the filter circuit is supplied to the multiplication circuit 24, and an image signal obtained by multiplying the image signal based on the multiplication value data is selected. After the selected image signal is supplied to the clipping circuit A34, the representative point of the image signal is stored at a predetermined address of the next-stage representative point memory circuit 36. And
The representative point is read out one field or one frame later and supplied to one end of the correlation operation circuit 38. on the other hand,
The output of the clipping circuit A34 is branched at this point. When the representative point at the time of the N-field is read out from the representative point memory circuit 36 and supplied to one end of the correlation operation circuit 38, it is supplied. The image signal of N eleven fields is supplied to the other end. In this case, in rare cases, the multiplication rate at the time of the N-field may differ from the multiplication rate at the time of the N-th field. In such a case, the calculation result may not be adopted.

[0016]

According to the apparatus of the present invention, the circuit size can be reduced without lowering the detection accuracy. In particular, claim 1
According to the described device, there are effects such as further downsizing of the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram of a correlation value accumulating apparatus according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a multiplication circuit 24.

FIG. 3 is a diagram showing a modified circuit configuration of a multiplication circuit 24.

FIG. 4 is an input / output characteristic diagram of a multiplication circuit 24 and a clip circuit A34 or a clip circuit B40.

FIG. 5 is a diagram illustrating input / output characteristics when a non-linear circuit is provided instead of the clip circuit A34 and the clip circuit B40.

FIG. 6 is a block diagram of a correlation operation device according to a second embodiment of the present invention.

FIG. 7 is a block diagram of a conventional correlation operation device.

[Explanation of symbols]

 Reference Signs List 20 input circuit 22 filter (high-pass filter) 24, 24A multiplication circuit 24a selector circuit A 24b selector circuit B 24c double circuit 24d adder 24e quadruple circuit 24f 1x circuit 28 peak value detection circuit 30 system control circuit 32 latch Circuit 34 Clip circuit A 36 Representative point memory circuit 38 Correlation operation circuit 40 Clip circuit B

Claims (2)

(57) [Claims] 1. An input circuit for inputting a digitized image signal, a filter for removing low-frequency components of the image signal, and a peak for detecting a peak value of an output signal from the filter. A value detecting circuit, a multiplying circuit for multiplying the image signal by a predetermined number according to the peak value, a holding circuit for holding the predetermined number, and removing lower bits of the image signal obtained by the multiplying circuit. A lower-order bit elimination means, a representative point memory circuit for storing a representative point based on an output signal of the lower-order bit elimination means, and a predetermined number and an identification number multiplied by one or more fields after the image signal And a correlation operation circuit for calculating a correlation between the image signal from which lower bits are deleted thereafter and the representative point stored in the representative point memory circuit. 2. An input circuit for inputting a digitized image signal, a filter for removing low-frequency components of the image signal, and a peak for detecting a peak value of an output signal from the filter. A value detecting circuit, a multiplying circuit for multiplying the image signal by a predetermined number according to the peak value, a lower bit removing means for removing lower bits of the image signal obtained by the multiplier circuit, and a lower bit removing means. A representative point memory circuit for storing a representative point based on the output signal of the means, and an image which arrives at least one field after the image signal, is multiplied by the predetermined number and the identification number, and then the lower bits are deleted. A correlation calculation device comprising: a correlation calculation circuit that calculates a correlation between a signal and the representative point stored in the representative point memory circuit.