JP2584414Y2 - Test equipment for semiconductor devices - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for testing the reliability of a semiconductor device by applying a predetermined voltage to a predetermined terminal of the semiconductor device in a high-temperature atmosphere.

[0002]

2. Description of the Related Art A high-temperature application test is an item for evaluating the reliability of a semiconductor device. This means that the semiconductor element is 100 to 1
A change in characteristics is measured by applying a predetermined voltage in a high-temperature atmosphere of about 50 ° C. For example, a description will be given of a high-temperature application test of the insulated gate field effect transistor (hereinafter abbreviated as MOS FET) shown in FIG. First,
In the MOS FET shown in the figure, a semiconductor pellet fixed on a lead frame is sealed with resin, and respective leads of a gate (G), a drain (D) and a source (S) are led out at equal intervals. This MOS FET has an N channel and a P channel.
Although there is a channel, both leads are derived in the same arrangement. Such a MOS FET is placed in a high-temperature bath described below and placed between a source (S) and a drain (D) and between a source (S) and a gate (G), as shown in FIGS.
As shown in (c) and (d), a DC voltage is applied with its polarity changed. The applied voltage at this time is between 50 and 1,000 between the source (S) and the drain (D) depending on the rating of the semiconductor element.
It is set in the range of 0V, and between the source (S) and the gate (G) is set in the range of 10-30V. In addition,
The connection indicated by each broken line in FIG. 2 will be described later.

Next, referring to FIG. 2A as an example, an outline of a test apparatus when a plus (+) DC voltage is applied to the drain (D) and a minus (−) voltage is applied to the source (S). The test procedure will be described. To test a MOS FET in a high-temperature atmosphere, a high-temperature bath 1 as shown in FIG. 3 is used. That is, although this figure is a side view, in the figure, the heater 2 and the fan 3 are arranged behind the internal space 4 and the temperature of the internal space 4 is controlled to a predetermined temperature. It has a configuration. The internal space 4 has a tray 5
Are inserted in multiple stages along guide rails not shown. As shown in FIG. 4, the tray 5 has a socket mounting portion 5 on the front surface side of the substrate 14 and a connection portion (not shown) on the back surface side. In the socket mounting part 5, a MOS
A socket 6 matching the pitch of the leads of the FET is screwed. The wiring to each socket 6 is shown in FIG.
Taking the test of (a) as an example, the configuration is such that the wiring 11 is pulled out from the sockets D and S in FIG. 5 and a plurality of sockets 6 are connected in parallel. The wiring on the board is connected to the connector 7 through the panel section 8. The connector 7 provided at the end of the panel section 8 has an external DC power supply circuit 16.
Is connected.

Next, the procedure of a test performed using the test apparatus having the above-described configuration will be described. First, the N-channel MO shown in FIG. 2A is attached to each socket 6 of the tray 5 of FIG.
Insert SFET. That is, on the tray 5, M
A MOS FE is provided for each socket 6 into which an OS FET is inserted.
The drain (D) of T and the receptacles 9 (D) and 10 (S) corresponding to the source (S) lead are arranged, and MOS
Connect the FET leads to the corresponding sockets 9, 1 of each socket 6.
Insert at 0. In addition, MOS is also used for the receiving port 13 (G).
The gate lead (G) of the FET is inserted.
3 is wired, so that no electrical connection is established.

Next, the tray 5 is inserted into the high-temperature bath 1 shown in FIG. Next, the heater 2 of the high-temperature bath 1 is energized to raise the temperature in the high-temperature bath 1 to a predetermined temperature. Further, the DC power supply circuit 16 is connected to the connector 7 of the panel unit 8 of the tray 5 such that the drain (D) side is plus (+) and the source (S) side is minus (-),
A voltage is applied for a long time in the range of, for example, 50 to 1,000 V depending on the rating of the FET. Note that an NFB (no-fuse breaker) is arranged to stop voltage application to a MOS FET whose short-circuit or leakage current has reached a specified value or more during a test.

Next, when a test is performed by applying a predetermined voltage between the gate (G) and the source (S) to a P-channel MOS FET as shown in FIG. The wiring 11 of the socket 6 of the tray 5 in FIG. 5 is changed to the receiving port 13 corresponding to the gate (G). In this case, of course, the DC power supply 1 is connected to the CD terminal and the CS terminal of the connector 7.
The connection is changed so that voltages having different polarities from 6 are applied, that is, the source terminal (S) side is plus (+) and the gate terminal (G) side is minus (-). Therefore, the drain (D) and the source (S) in FIG.
High voltage reverse voltage test (hereinafter referred to as HTR)
Abbreviated as B test. ), Gate (G) and source (S)
High-temperature gate bias test (hereinafter, H
Abbreviated as TGBB test. ) Indicates the wiring 11 of the socket 6
Are different from each other in that the polarity of the applied voltage is inverted between the N-channel and P-channel elements of the MOS FET.

[0007]

[Problems to be Solved by the Invention]
The test equipment performs each test according to the procedure described above.
Therefore, there were the following problems to be solved. (1) N-channel and P-channel types of MOS FET
According to the connector of the panel part 8 of the tray 57Directly against
The power supply circuit 16 must be connected with its polarity changed,
The test preparation work is complicated. (2) In the HTRB test and the HTGBB test shown in FIG.
Cannot share tray 5, but with a separate tray
What you have to do. That is, in the HTRB test, the socket 9 is used as the socket 6.
(D) and the receiving port 10 (S) need to be arranged.
On the other hand, in the HTGB test, the socket 613
(G) and receptacle 10 (S) must be arranged
No. Therefore, the above-mentioned HTRB test or HTGB test
Re-work the wiring of the socket 6 for each test, or
Prepare a tray 5 of any kind or take one of the methods
I had no choice. However, the former requires more man-hours
And the latter requires the expensive tray 5 to be prepared.
There is a point. Also, for the diode, MOS FET
In the same manner as in the three-terminal outer shape, for example,
Configuration, and these high temperature reverse voltage tests
There were similar difficulties.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a semiconductor device test apparatus capable of easily performing a plurality of tests on one common tray. .

[0009]

The semiconductor device test apparatus according to the present invention is inserted into a high-temperature chamber 1 which can be controlled to a predetermined temperature.
Placed inside the high-temperature bath 1 and the insertion portion 20 inside the high-temperature bath 1
Tray 5 consisting of a high-temperature chamber outer panel 30 and output polarity
DC power supply circuit 40 provided with relay RL1 for switching
The insertion portion 20 in the high-temperature bath has a receiving port 9, 1.
A plurality of sockets 6 having 0, 13 are arranged,
The panel 30 outside the warm bath has a contact S1 to a contact D1 or a contact D1.
Mercury refill with a structure that can switch from contact S1 to contact G1
The socket 15 of the socket 6 has a contact D
1, socket 10 to contact S1, and socket 13 to contact G1.
And connected to the DC power supply circuit 40.
One of the polarities of the DC power supply
G1 and the other polarity is the contact D1 of the mercury relay 15
, Respectively.

[0009]

The test device for a semiconductor device of the present invention is a MOS F
When conducting a high-temperature voltage application test for ET, the voltage application lead and the voltage application polarity from the DC power supply circuit must be changed between the N-channel device and the P-channel device. And the polarity of the applied voltage is changed by a relay provided in the DC power supply circuit. Thus, four types of high-temperature voltage application tests can be easily performed.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, the tray 5 is roughly divided into two parts. That is, it is constituted by the high-temperature-tank insertion section 20 that enters the high-temperature tank 1 shown in FIG. The socket 6 is screwed onto the substrate 14 in the high-temperature bath insertion portion 20. Each socket 6
Ports 13 (G), 9 (D), and 10 (S) are MOS
FETs are provided corresponding to the gate (G), the drain (G), and the source (S), respectively.
They are arranged vertically in the figure and are connected in parallel with each other. One group of the parallel-connected sockets 6 shown in the drawing is one block, and many such blocks are provided in the vertical and horizontal directions of the board 14.

A single mercury relay 1 is formed on a panel 30 outside the high-temperature chamber of the tray 5 with one group of sockets 6 as one block.
5 are provided. The receptacle 10 (S) of the socket 6 is connected to the contact S1 of the mercury relay 15 by the wiring 11, and the receptacle 9 (D) is similarly connected to the contact D1 by the receptacle 1
3 (gate D) is connected to the contact point G1 by the wiring 11 respectively. A DC power supply circuit 40 is connected to the CD terminal and the CSG terminal of the connector 7. The DC power supply circuit 40 can output a constant voltage and a constant current, and has a voltmeter 42 and an ammeter 41. Also, the relay RL1
Is for switching the polarity of the direct current supplied to the connector 7 of the tray 5. In the DC power supply circuit 40, F is a no-fuse breaker. SW is a main switch, and is provided for turning on / off the voltage application to the tray 5. The portion shown in FIG. 1 is one block of the socket 6 as described above, and there are a plurality of blocks on the same substrate 14. A mercury relay 15 and a DC power supply circuit 40 are provided for each block.

Next, a test procedure using the test apparatus having the above configuration will be described. First, a case of performing an HTGB test for applying a voltage of the gate terminal (+) polarity in FIG. 2B will be described. The leads (D), 10 (S), and 13 (G) of each socket 6 on the tray 5 in FIG. to the corresponding inserted. Next, this tray 5
Is inserted into the high-temperature bath 1 shown in FIG . The temperature in the high-temperature bath 1 is set so as to be a predetermined temperature. The DC power supply circuit 40 is connected to the connector 7 of the tray 5 with the switch SW turned off. The relay RL1 in the power supply circuit 40 switches so that the CSG side of the connector 7 becomes plus (+). Next, the contacts are switched by the drive current of the mercury relay 15 (not shown) so that the contacts D1 and S1 of the mercury relay 15 are connected. After the above preparation is completed, the switch SW is turned on. Thereby, the positive (+) pole of the DC power supply circuit 40 is connected to the socket 1 of each socket 6 through the CSG terminal.
3 (G), and a positive (+) voltage is applied to the gate (G) of the MOS FET. On the other hand, the negative (-) side of the DC power supply circuit 40 is connected from the connector CD to the socket 9 (D) of the socket 6 and the mercury relay 15 to the socket 10 (S) of the socket 6 respectively. At this time, the drain terminal and the source terminal are short-circuited.

Next, a description will be given of the P-channel HTRB test shown in FIG. In such a case, the difference from the above-described example is that the contact connection relationship of the mercury relay 15 is changed and G1
This is to connect the contact and the S1 contact. Thereby, the gate terminal (G) and the source (S) of the MOS FET
Plus (+) to the source terminal (S) in a state where
A negative (-) side DC voltage can be applied to the drain and drain (D). 2 (b) and 2 (d) show the switching of the contact of the mercury relay 15 and the relay RL1.
It is clear that the HTGB test in which a negative (-) polarity voltage is applied to the gate and the N-channel HTRB test can be performed by the combination of. As described above, a significant feature of the test apparatus according to the present invention is that the mercury relay 15 is used for the panel 30 outside the high-temperature chamber of the tray 5.

In the HTGB test of FIG. 2, a voltage is applied between the gate (G) and the source (S) of the MOS FET.
Due to the characteristics of the OS FET, almost no current flows in any of FIGS. 2B and 2D. However, it is necessary that a predetermined voltage be applied reliably. By the way, in a general mechanical relay, even if the surface of the contact is oxidized, a current flows between the contacts, so that an oxide film formed on the surface is removed, and the contact is completed. However, when the voltage is as low as 10 to 30 V and the current hardly flows as in this test, the mechanical relay depends on the surface condition, and the contacts are in contact but may not be electrically connected. Occurs. Therefore, this test apparatus uses the mercury relay 15 to solve the above-mentioned inconvenience. Further, in the HTRB test of FIG. 2, noise is not induced in the wiring 11 of the socket 13 (G) of the socket 6 so that noise is not induced.
The mercury relay 15 is arranged on the panel 30 outside the high-temperature chamber of the tray 5.

The above-described test apparatus can be used for tests other than the MOS FET. For example , the diode shown in FIG. 6 can be used as a high-temperature reverse voltage application test. FIG. 6 shows a center tap type, a reverse type in which one diode chip is enclosed, and a normal type diode, and the relationship between the polarity of each lead applied voltage is also as shown. In this figure, for example, in the case of a center tap type and a cathode common, in the socket 6 of FIG. 1, the cathode lead (K) is in the socket receptacle 9 (D), and the anode lead (A) is in the receptacle 13 (G). ) And the receptacle 10 (S). Further, the mercury relay 15 connects the G1 contact and the S1 contact, and switches the relay RL1 in the DC power supply circuit 40 so that the CD terminal of the connector 7 becomes plus (+). As a result, a DC voltage is applied to this diode as shown. For other types of diodes, tests can be performed by changing the contact connection of the mercury relay 15 and the plus (+) side of the connector 7 , respectively.

[0016]

As described above, the testing device for semiconductor devices of the present invention changes the connection relationship between the leads of the semiconductor device by the mercury relay provided on the panel outside the high-temperature chamber, and also applies the direct current applied between the leads. The polarity of the DC voltage from the power supply circuit is
Since the configuration can be changed by a relay provided in the power supply circuit, the four tests shown in FIG. 2 can be easily performed on one common tray. In addition, since the mercury relay is located on the panel outside the high-temperature chamber of the tray, noise is less likely to enter the gate, and a predetermined voltage can be reliably applied, and a highly reliable test can be performed. it can. Furthermore, various diodes have an excellent effect that a target test can be easily performed by switching a switch using a common tray.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor device test apparatus of the present invention.

FIG. 2 is a diagram illustrating a method of applying a voltage to each lead and a polarity of the applied voltage when a high temperature application test is performed on a MOS FET.

FIG. 3 is a side view of the semiconductor device test apparatus of the present invention.

FIG. 4 is a detailed view of a tray in the semiconductor device test apparatus of the present invention.

FIG. 5 is a configuration diagram of a conventional test apparatus.

FIG. 6 is a diagram showing a method of applying a voltage to each lead and a polarity of an applied voltage when various diodes are subjected to a high-temperature application test.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High temperature chamber 2 Heater 3 Fan 4 Internal space 5 Tray 7 Connector 9,10,13 Socket socket 14 Substrate 15 Mercury relay 20 High temperature chamber insertion part 30 High temperature chamber panel part 40 DC power supply circuit

Claims (1)

(57) [Scope of request for utility model registration] 1. Inside a high-temperature bath (1) that can be controlled to a predetermined temperature.
Insertion part (20) in a high-temperature tank inserted into the tank and the high-temperature tank
(1) From the outside of the high-temperature chamber panel (30)
Tray (5) and a relay (R
L1) and a DC power supply circuit (40),
The first inlet (9) and the second
Moss with a receiving port (10) and a third receiving port (13)
A plurality of slots (6), and a panel portion outside the high-temperature chamber.
(30) includes a first contact (S1) to a second contact (D
1) or the first contact (S1) to the third contact (G1)
Mercury relay (15) with switchable structure
The first socket (9) of the socket (6) is connected to the second socket.
To point (D1), the second socket (10) is connected to the first contact (S
To 1), the third socket (13) is the third contact (G1).
Connected to the DC power supply circuit (40).
One of the polarities of the DC power supply
5) To the third contact (G1), the other polarity is the mercury
Respectively connected to the second contact (D1) of the relay (15).
A test device for a semiconductor device, characterized in that: