JP2580629B2 - Memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device such as a dynamic RAM or an image memory or a buffer memory. The present invention relates to a memory device including a setup circuit for generating a clear pulse signal or the like for a device having a function.

[Summary of the Invention]

The present invention relates to a memory device for storing an information signal,
By providing a clock signal generation circuit for supplying an initialization signal, a level detection circuit for controlling ON / OFF of a switch, and a setup circuit serving as a switch control circuit, automatic startup after power-on is realized. Things.

2. Description of the Related Art Generally, in a memory device such as a dynamic RAM, it is impossible to perform a sufficient circuit operation of the memory device immediately after power-on. Therefore, in these memory devices, an initialization signal is supplied from outside the chip after a time of about 100 μs elapses after the power is turned on. A dummy cycle for inputting a clock is used as the initialization signal, and this dummy cycle is applied to, for example, about eight cycles of the input portion of the memory device. After the input of such a dummy cycle, the memory device operates normally.

Recently, as a special function of a memory device such as an image memory or a buffer memory, a device having a so-called flash clear function is known. The flash clear function is a function of removing information of a required memory cell by inputting a clear pulse, and a clear pulse as an initialize signal is input from outside the chip.

[Problems to be solved by the invention]

As described above, in the conventional memory device, a waiting time (pause time) is required until the internal power supply is stabilized after the power is turned on, and an operation of refreshing with a dummy clock in the circuit (for example, RAS only refresh) is required. It is said. In an image memory or the like,
Some have a flash clear function.

However, an initialization signal for performing these operations is supplied from outside the chip before the original read / write operation is performed. Therefore, a function for generating these initialization signals is required outside. Further, depending on the chip to which the initialization signal is supplied, there is a memory device which operates sufficiently even if the waiting time is shortened due to its performance. Setting a uniform wait time for such a memory device will include extra time in the wait time, resulting in a redundant setup operation.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a memory device that realizes automatic startup after power-on and eliminates extra waiting time.

[Means for solving the problem]

The present invention provides a clock signal generating means, and an initializing signal generating means for outputting a clock signal generated by the clock signal generating means as an initializing signal to an initializing signal input unit via a first switch means and a second switch means. First switch control means for controlling the first switch means based on detection of the substrate voltage level; and the second switch based on a clock signal supplied via the first switch means. The above-mentioned problem is solved by a memory device comprising a set-up circuit comprising a second switch control means for controlling the other of the means to conduct for a predetermined period of time and then to shut off.

Here, the initialization signal is a dummy clock provided when power is turned on, or a clear pulse or the like used for flash clearing. Each of the first and second switch means may be, for example, a transistor, and may be constituted by a single transistor or a plurality of transistors. The detection of the level is performed, for example, with respect to the substrate voltage V _BB or the power supply voltage V _CC at the time of power-on. When a required level (for example, a potential difference that ensures stable operation) is detected, the first switch unit is turned on. Such control is performed by the first switch control means. The second switch control means is a circuit for outputting an initialization signal consisting of a necessary clock or a single pulse to an initialization signal input section, and then controlling the second switch means to be cut off. , A timer, a counter and the like.

[Action]

Since the first switch means is controlled based on the detection of the substrate voltage level, the initialization signal can be output from the initialization signal generation means at the most suitable timing for the chip, and the output of the initialization signal is completed. Sometimes, the second switch is shut off, so that an automatic setup operation is performed as a whole,
No extra waiting time is required.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment The memory device of this embodiment has a setup circuit 1 shown in FIG. The setup circuit 1 includes a clock signal generation circuit 4 serving as an initialization signal generation source.
A _VBB level detection circuit 2 for detecting the level of the substrate voltage _VBB and outputting a control signal; a counter circuit 3 as a switch control circuit for turning off the switch when the output of the initialization signal is completed; 5, 6, and 7 are the main components.

The clock signal generation circuit 4 is a self-excited oscillator,
A clock having a predetermined frequency is output. The switch (MOS transistor) 5 is connected to the output side of the clock signal generation circuit 4.
An initialization signal is sent to the initialization signal input unit via 11 and the like.

The V _BB level detection circuit 2 detects the level of the substrate voltage V _BB and outputs a control signal V _{5 g} when the level falls below a certain value V _ST . The certain value _VST is a voltage at which stable operation is guaranteed at least, and is a unique voltage of the chip. Therefore, in a chip having good performance, that is, a chip that stabilizes early after the power is turned on, the substrate voltage _VBB has a certain value V
_{The ST} reaches the _ST earlier, and a precharge operation or the like at a higher speed becomes possible. The control signal _V5g is sent to the gate of the switch 5. When the substrate voltage _VBB reaches a certain value _VST , the switch 5 is switched from the cutoff state to the conduction state by the control signal.

Here, an example of a specific circuit configuration of the _VBB level detection circuit 2 will be described with reference to FIG. That V
_{The BB} level detection circuit 2 has resistors 21 and 22 connected in series between the power supply voltage V _CC and the substrate voltage V _BB , and the level divided by the resistors 21 and 22 is input to the inverter 23. The above-mentioned certain value _VST is determined by the resistors 21 and 22, and the resistor 21 is connected to the resistor 22.
It has a smaller value. An inverter 24 is connected to the output side of the inverter 23, and a two-input NAND circuit 25 is connected to the output side of the inverter 24. This NAND circuit
The output of 25 is an output terminal 28 connected to the gate of the switch 5, and a part of it is used as the other input of the NAND circuit 25 via an inverter 26. At the other input of the NAND circuit 25, the power supply voltage V _CC
Is supplied.

The operation of the V _BB level detection circuit 2 will be described. The potential of the substrate voltage V _BB immediately after the power is turned on is substantially ground (G
ND) potential. Therefore, the middle point between resistors 21 and 22 is
The potential is higher than the threshold voltage _{Vth of the} inverter 23 due to the resistance division. Next, the substrate voltage V _BB gradually decreases,
Beyond a certain value V _ST, the potential of the middle point inverter 2
The potential is lower than the threshold voltage _{Vth of} 3. Then, the output of the inverter 24 is set to “L” level (low level),
The output of the input NAND circuit 25 changes from “L” level to “H” level (high level). Then, the switch 5 is turned on.

In the present embodiment, the counter circuit 3 has a function of stopping the output when the output of the initialization signal is completed. The counter circuit 3 includes a counter unit 31 and a latch unit 32
It is composed of The counter unit 31 is a circuit that counts pulses of the initialization signal. The output of the V _BB level detection circuit 2 is supplied to the inverter 1
2, and an initialization signal from the clock signal generation circuit 4 is further input via inverters 8 to 11 as delay circuits. The latch section 32 holds the output from the counter section 31. The output of the latch section 32 is the switch 6 and the switch 7
Is supplied to the gate.

Here, while referring to FIG.
An example of a specific configuration will be described. First, the counter section is composed of a plurality of T-type flip-flop circuits 34. The output from the _VBB level detection circuit is inverted and input to each terminal of each flip-flop circuit 34 via the inverter 12. The output of the inverter 11 is input to the terminal of the first-stage flip-flop circuit via the switch 7, and the output from the Q terminal of the first-stage flip-flop circuit is input to the terminal of the next-stage flip-flop circuit. The output of the Q terminal of the next-stage flip-flop circuit is further input to the terminal of the next-stage flip-flop, and is connected one after another in such a relationship. The output of the Q terminal at the last stage of the flip-flop circuit is input to the inverter 35. Next, the latch unit has a two-input NAND circuit 36 whose one input is the output of the inverter 35, and an inverter 37 that inverts the output of the NAND circuit 36 and feeds it back.
The output of the ND circuit 36 is connected to the above switch via an inverter 39.
It is output to 6,7 gates. A power supply voltage V _CC is connected via a resistor 38 to the other input terminal of the NAND circuit 36 as a feedback loop.

In such a counter circuit 3, the T-type flip-flop circuit 34 is provided according to the number of pulses of the initialization signal. For example, when the initialization signal is composed of eight pulses, the T-type flip-flop circuit 34
One is good. It is naturally possible to change the circuit according to the pattern of the initialization signal. The operation of the counter circuit 3 will be briefly described.
The reset signal changes from “H” level to “L” level via 12, and each flip-flop circuit is reset. Next, a part of the initialization signal is taken into the terminal of the first-stage flip-flop circuit 34 via the switch 7 via the inverters 8 to 11 as delay circuits. Due to the count operation of the multiple-stage flip-flop circuits 34, the Q terminal of the final-stage flip-flop circuit 34 changes from “L” level to “H” level at a predetermined count. Then, the output of the NAND circuit 36 changes from “L” level to “H” level via the inverter 35. Accordingly, the voltage supplied to the gates of the switches 6 and 7 via the inverter 39 also changes from the “H” level to the “L” level, and the switches 6 and 7 are turned off.

The switch 6 is connected to the output terminal of the inverter 11 and controls conduction and cutoff with the initialization signal input unit 13. The control is based on the output from the counter circuit 3. The switch 7 is connected to the output terminal of the inverter 11 and controls the input to the counter circuit 3. The control is also based on the output from the counter circuit 3. As the switches 6 and 7, for example, NMOS transistors can be used.

Setup circuit 1 having circuit configuration as described above
Operates as shown in the time chart of FIG. 4 as a whole. In FIG. 4, line (a) is the power supply voltage.
V _CC . Line (b) is the substrate voltage V _BB . Line (c)
This is a control signal _V5g from the _VBB level detection circuit 2. Line (d) is the output signal Φ _CL of the clock signal generation circuit 4. Line (e) is the output signal V _6g from the counter circuit 3. Line (f) is the initialization signal Φ _IN supplied to the initialization signal input unit 13.

First, the power at time t ₀ is turned initially, as shown in line (a), rising from the power supply voltage V _CC is "L" level,
Stabilizes at “H” level with some ringing. On the other hand, substrate voltage V _BB gradually decreases from the ground level “L” level due to the operation of the charge pump circuit. When the time was t ₁ elapsed, it reaches the voltage V _ST there is a substrate voltage V _BB. This voltage _VST is a voltage that enables at least a stable operation of the chip on which the setup circuit is mounted.

Now that reached the voltage V _ST there is a substrate voltage V _BB, the V
The potential at the midpoint of the _BB level detection circuit 2 divided by the resistance becomes lower than the threshold voltage _{Vth of the} inverter 23, and the operation of the _VBB level detection circuit 2 changes the control signal _V5g from "L" level to "H". It changes to the level (time t ₂ ). After the substrate voltage V _BB is reduced to the final “VL” level, the control signal V _5g
Can be set to the “H” level. Control signal V _5g is “H”
Level, and the switch 5 is turned on. Then
The output signal Φ _CL of the clock signal generation circuit 4 is supplied to the initialization signal input section 13 as the initialization signal Φ _IN (line (f)) via the inverters 8 to 11 and the switch 6. Further, when the control signal _V5g becomes “H” level, the reset signal sent via the inverter 12 also becomes “L” level, and the flip-flop circuit 34 of the counter circuit 3 is reset.

A part of the initialization signal Φ _IN is input to a first-stage terminal in the multiple-stage flip-flop circuit 34 via the switch 7. Thereafter, according to the pattern of the initialization signal Φ _IN (for example, 8 pulses), when the counting is completed, that is, when the output of the initialization signal is completed, the output of the last-stage flip-flop circuit 34 changes from “L” level to “H” level. . As a result, the output signal V _6g from the counter circuit 3 changes from “H” level to “L” level (time t
₃ ). Then, the gate voltages of the switches 6 and 7 are changed from “H” level to “L” level, and the switches 6 and 7 are turned off. Then, the supply of the signal of the initialization signal Φ _{IN to} the initialization signal input unit 13 is stopped, and the operation of the setup circuit 1 ends.

In the memory device of the present embodiment that performs the above operation, the initialization signal is used as a dummy clock or a pulse for flash clear by the operation of the setup circuit 1, and the automatic setup operation is easily performed after the power is turned on. Will be Further, setup in a minimum time according to the performance of the chip is realized.

Second Embodiment The memory device of this embodiment is a device having a setup circuit 51 in which a setup completion signal output circuit 70 is added to the setup circuit 1 of the first embodiment.

First, the configuration will be described with reference to FIG.
Similarly substantially in the first embodiment, a clock signal generating circuit 54 serving as a source of initialization signals, V _BB level detection circuit 52 for outputting a control signal by detecting a level of the substrate voltage V _BB
And a counter circuit 53 as a switch control circuit for turning off the switch when the output of the initialization signal is completed.
, Three switches 55 to 57 and inverters 58 to 62. Further, the setup circuit 51 according to the present embodiment is provided with a setup completion signal output circuit 70.

The setup completion signal output circuit 70 has a function of outputting a pulse signal from the chip D _OUT terminal 83 when the setup operation is completed. As shown in FIG. 5, the setup completion signal output circuit 70 has inverters 71 and 72 connected in series, a resistor 73 and a capacitor 7.
4, a two-input NAND circuit 75, and the NAND circuit 75.
It comprises an inverter 76 for inverting the output of the circuit 75, and a MOS transistor 77 connected to an output terminal 83 of an output buffer circuit composed of MOS transistors 81 and 82. The output from the counter circuit 53 is input to the inverter 71, and the output of the inverter 71 is
Input to NAND circuit 75. The output of inverter 72 is resistor 73
The connection point between the resistor 73 and the capacitor 74 is input to the NAND circuit 75. The output of the NAND circuit 75 is inverted by an inverter 76 to control the MOS transistor 77.

The operation of the setup completion signal output circuit 70 will be briefly described. When the output of the initialization signal is completed, the output of the counter circuit 53 changes from “H” level to “L” level. Then, one input of the NAND circuit 75 changes to “H” level via the inverter 71. At this time, the output of the NAND circuit 75 changes from the “H” level to the “L” level, the MOS transistor 77 changes from the OFF state to the ON state, and a pulse signal is output from the _DOUT terminal 83.
In parallel with this, the connection point of the integration circuit starts to gradually decrease from the “H” level via the inverter 72. Then, when the voltage _falls below the threshold voltage _Vth of the NAND circuit 75, N
The output of the AND circuit 75 changes from “L” level to “H” level. As a result, the MOS transistor 77 is turned off, and the output of the pulse signal from the _DOUT terminal 83 is stopped.

In this embodiment, the clock signal generation circuit 5
4, _VBB level detection circuit 52, counter circuit 53, switch 55
To 57, the inverters 58 to 62, etc., have the same configuration and operation as the corresponding ones of the first embodiment, and therefore detailed description thereof will be omitted.

In the memory device according to the present embodiment, first, the setup operation is automatically performed easily after the power is turned on by the operation of the setup circuit 51, and the setup in a minimum time according to the performance of the chip is realized. Will be done.
Further, the above-described setup completion signal output circuit 70
As a result, a pulse indicating that the setup operation has been completed is output, and it is possible to easily monitor the setup operation.

Note that the memory device of the present invention is not limited to the above-described embodiment, and various changes can be made without changing the gist of the memory device.

〔The invention's effect〕

In the memory device of the present invention, the automatic setup operation is easily performed after the power is turned on by the operation of the setup circuit, and there is no need to externally supply a dummy clock, a flash clear pulse, or the like. Further, setup in a minimum time according to the performance of the chip is realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an example of the memory device of the present invention, FIG. 2 is a circuit diagram showing an example of a specific configuration of the _VBB level detection circuit, and FIG. FIG. 4 is a circuit diagram showing an example of a specific configuration of the counter circuit, and FIG. 4 is a time chart according to an example of the memory device of the present invention. FIG. 5 is a circuit diagram showing a main part of another example of the memory device of the present invention. 1,51 ...... set-up circuit 2, 52 ...... V _BB level detection circuit 3, 53 ...... counter circuit 4, 54 ...... Clock signal generator circuit 5,6,7,55,56,57 ...... switch 70 ...... Setup completion signal output circuit

Claims (1)

(57) [Claims] 1. An initialization signal generating means for outputting a clock signal generated by said clock signal generating means as an initializing signal to an initializing signal input section via a first switch means and a second switch means. Means, first switch control means for controlling the first switch means based on detection of the substrate voltage level, and second control means based on a clock signal supplied via the first switch means. A second switch control means for controlling the other of the switch means to be turned on after being turned on for a predetermined period, and a second switch control means.