JP2580557B2 - Test method and apparatus for distributed system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributed system testing method and apparatus, and more particularly, to a switching system using a computer,
Distributed communication systems such as transmission systems and information processing systems
The present invention relates to a test method (hereinafter simply referred to as a “distributed system”) and an apparatus therefor.

[0002]

2. Description of the Related Art Conventionally, as a distributed system as described above, there is a system as shown in FIG. This system is a system in which a plurality of modules including a control device, an interface unit, and a test circuit are connected via a bus. As a test method of each module constituting this system, a specific module (for example, module Q) is designated, and this module Q includes not only the control device 10 but also a test circuit 12 necessary for testing each module. In addition, the above-described control device 10 is provided with a program necessary for executing a test, necessary data, and the like.
Using this, the interface unit 11, i1 (i = 2,
(3,..., P), when the test of each module i is independently executed and the test of the entire system is performed, the above-described module Q randomly selects the modules 1 to P or
The test was performed by selectively selecting the modules and specifying the order. Specifically, the test execution program of the control device 10 of the module Q described above gives information necessary for a test including a test environment setting to each module, and sequentially executes a test of the module itself. The test between modules was performed in the order of 1 and module 2 or between module 3 and module P.

[0003]

In the test method shown in the above prior art, the total time from the start of the module test to the end of the test is the sum of the respective test times. As the number of constituent modules increases and the number of connections between modules also increases, there is a problem that the test time greatly increases. Further, in the conventional technology, when a module is composed of a plurality of functional blocks, each functional block is tested in the same manner as the module, and the module in the system and the module are tested. Even when the function blocks in the middle have a hierarchical structure, no attitude was found to actively use this. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a first object of the present invention is to solve the above-described problems in the related art, and to perform a test such as a test of a module in a system or a test of a functional block in a module. To provide a test method for a distributed system that enables a parallel test from a higher-level control device, and a device therefor, by making the test complete within a module or a functional block. A second object is to provide a distributed system in which a module in a system and a functional block in the module form a hierarchical structure, and the same test method is applied using the hierarchical structure. To provide a test method and a device therefor.

[0004]

The object of the present invention is to provide a plurality of lower function block devices, a higher function block device, an interface device for connecting them, and a plurality of connections for connecting the plurality of lower function block devices. In a module including links, when a command for testing the entire module is received, the upper function block device tests the normality of the higher function block device itself, the interface device and the plurality of lower functions. After testing the normality of the interface units of the block device and the higher-level function block device, the test of the plurality of lower-level function block devices and the test between the plurality of lower-level function block devices are respectively performed in parallel. This is achieved by a distributed system testing method and apparatus therefor.

[0005]

In the distributed system test method according to the present invention, when a command for testing the entire module is received from a higher-level device, the test is performed according to the following procedure to confirm the normality of the entire module. Test of upper functional block itself Test of interface device and interface section of each functional block Test of lower functional blocks (parallel processing) Test between lower functional blocks (parallel processing) Perform the test according to the same procedure. In this case, for the functional blocks in each module, the above-described test procedure is used as it is.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a diagram showing the configuration of the module according to the first embodiment of the present invention. The module shown in the present embodiment includes a plurality of lower function blocks LN (N = 2 to N), an upper function block U, an interface device T for connecting the upper function block U and the lower function block LN, It is composed of lower functional block connection links Y connecting LNs. The upper function block U includes a control device A1 capable of performing multiplex processing, a test circuit B1 in the higher function block U, and the control device A1.
An interface (I / F) unit E12 for connecting the test circuit B1 to the interface device T; a test circuit C1 for testing the interface unit E12 and the interface device T; For storing the connection information of the links Y between the two, the fault position determination information of the interface device T, the fault position determination information in the function block U, the fault position determination information of the link Y between the lower function blocks LN, and the like. It is composed of a device D1. The above devices are connected to each other as shown in FIG. 2 through a connection line inside the upper function block U.

The lower functional block LN (N = 2)
To N) are a control device AN capable of multiplex processing, an interface unit EN2 for connecting the lower functional block LN and the interface device T, and a test between the interface unit EN2 and the interface device T. Test circuit CN, a main device EN1 for realizing the function of the lower functional block LN, and a main device EN1
And a lower functional block L for testing
N, an interface section EN3 between N, a test circuit EN for testing the interface section EN3, fault position determination information on the lower function block device LN, fault position determination information on the plurality of connection links Y, and between the lower function block LN. It comprises a storage device DN for storing fault position determination information and the like. In addition, each of the above devices is provided with a lower function block LN.
As shown in FIG. 2, they are connected to each other through internal connection lines. The control device A1 of the upper function block U includes a test management function for controlling the upper function block U and the lower function block LN, a function for performing test control on a plurality of lower function blocks LN, and a plurality of lower function blocks. A test function for a link Y connecting the LNs and an access function for storing information in the storage device D1 are provided.

Hereinafter, the operation of the present embodiment configured as described above will be described with reference to the operation flow shown in FIG. First, an outline will be described. From a higher-level device not shown,
The module according to the present embodiment (hereinafter, referred to as “module M”) via an interface (not shown)
Next, when the control device A1 of the upper functional block U receives a command for testing the entire module M (step 11), the test is performed according to the following procedure to confirm the normality of the entire module M. Test of upper functional block U itself (Step 12) Test of interface device T and interface section of each functional block (Step 13) Test of lower functional block LN (Steps 14 to 17) Test between lower functional blocks LN (Steps 18 to 18) 21) The details of the above test are described below. Is mainly composed of the control device A1 of the upper function block U and the test circuit B1.
Is used to confirm the normality of the control device A1.

The test communication is performed from the control device A1 to the control device AN in each functional block. At this stage, the normal operation of the interface unit E12 in the upper functional block U and the interface unit EN2 in each lower functional block is performed. The test is performed by using test circuits C1 and CN, respectively. The specific method of the above test includes each test circuit E
There are test means for transmitting / receiving information for a continuity test, missing information, and checking for errors between the N nodes, but details are omitted. This test result is processed by the control device A1 and stored in the storage device D1 in the upper functional block U. Is to test the function blocks themselves, and uses the function of test-controlling the plurality of lower function blocks LN themselves. The control device A1 of the upper function block U
Performs only a test start synchronization process for each functional block, and the control device AN in each functional block is the main device. In addition to the control device AN, the main device EN1 is a test circuit B
Using N, a test circuit CN performs a test between the interface unit EN2 and the interface device T, and a test circuit EN performs a test using the test circuit EN. This process is characterized in that each function block performs the process in parallel.

In the next test, a link test control function for connecting the plurality of lower function blocks LN described above is used. That is, a test is performed between two or more functional blocks, and the upper functional block U also performs a synchronization process between the functional blocks. Here, the upper-level function block U performs a conflict process so that duplication does not occur in a combination of tests. In the same way, the test is applied to the part where the test can be performed in parallel. , Are stored in the storage device D1 in the upper function block U. The test process is performed by the storage device D in each functional block.
N, the test results are reported to the upper function block U, and temporarily stored in the storage device D1, and the control device A1 of the higher function block U uses this to report to the upper device. Also, when the host device instructs not a test of the entire module but a test of a plurality of selected function blocks or a test between the function blocks, the upper function block U
The control device A1 checks whether or not parallel processing of the combinations to be tested is possible, and performs the synchronization processing. Thereafter, a test is started for each functional block. The result is also reported from each functional block to the upper functional block U, and based on this, the report to the upper device is made.

Next, a test method when a failure occurs will be described. The failure is detected by the lower functional block LN or the upper functional block U. When a failure is detected in the lower-level functional block LN, the control device An in the lower-level functional block LN responds to the failure detection result by using the test circuits Bn, C
A test is performed by n, En or the control device An itself, and the fault location is identified. This result is transmitted to the control device A1 of the upper function block U, stored in the storage device D1, and reported to the higher device. When a fault is detected in the upper function block U, the control device A1 performs a test in the test circuits B1 and C1 or the control device A1 according to the fault detection result, and identifies the location of the fault. This result is stored in the storage device D1 and is reported to the host device. When a failure between lower functional blocks LN is detected, a failure detected between two or more functional blocks is reported to the upper functional block U, and when a failure is uniquely determined, Is stored in the storage device D1. If it cannot be uniquely determined, a test is performed in the same manner as in the above-described processing to identify a faulty part. This result is stored in the storage device D1 and reported to the host device.

The above-mentioned processing, that is, the failure in the interface unit is also performed by testing the test circuits of the interface unit in the upper function block U and the interface unit in the lower function block LN with the control unit A1 in the upper function block U and the lower function unit. The control device AN in the block LN cooperates and performs a test in the same test procedure as above. The test results are stored in the storage device D
1 and the result is reported to the host device. According to the above embodiment, the test circuit in the functional block is shared and its startup control is performed, regardless of whether the command is received from the host device and the test in the module is performed or the test is performed autonomously when a failure occurs. Is performed from the upper functional block, an effect that parallel processing becomes possible is obtained. FIG.
FIG. 9 is a diagram showing a configuration example of a module according to another embodiment of the present invention. In the present embodiment, the link Y between the lower function blocks shown in FIG. 2 and the interface device T for connecting the upper function block U and the lower function block LN are shared by the link T, and the interface section EN3 of the lower function block LN is used. Are connected to the link T. The test method is the same as in FIG. Note that the interface units EN3 and EN2 of the lower function block LN can be integrated.

FIG. 4 is a diagram showing a configuration example of a system according to still another embodiment of the present invention. This system is configured by combining a plurality of modules shown in FIG. 2 or FIG. Here, the system is a higher-level module M
U, a plurality of lower modules MLG (G = 1 to g), an interface device X for connecting the upper module MU and the lower modules MLG, and an inter-module link Z for connecting the lower modules MLG. ing. The above-mentioned upper module MU includes a control device UE capable of performing multiplex processing and testing in the upper module MU, an interface unit U1 for connecting the upper module MU and the interface device X, and an interface unit U1. A test circuit U2 for testing between the interface devices X, an interface unit U3 for connecting the host system and the module MU, a test circuit U4 for testing between the interface unit U3 and the host system, and the plurality of connections; A storage device I for storing connection information of the links Z, fault location determination information of the interface device X, and fault location determination information of the plurality of connection links Z.
, And the storage device I is connected to the control device UE.

The plurality of lower modules MLG
Are a control device MLGE capable of multiplex processing, an interface unit MLG1 connecting the lower module MLG and the interface device X, and an interface unit MLG
1 and a test circuit M for testing between the interface device X
LG2, an interface section MLG3 between the plurality of lower modules MLG, a test circuit MLG4 for testing the interface section MLG3, and the lower module ML.
G, and a storage device MLGI for storing the fault position determination information for the plurality of connection links Z, and the storage device MLGI is configured to store the fault position determination information for the plurality of connection links Z.
Connected to GE. Note that the above upper module M
The U control device UE has a test management function for controlling the upper module MU itself and the lower module MLG, a function for test-controlling a plurality of lower modules MLG,
A test function for the links Z connecting the plurality of lower modules MLG and an access function for storing information in the storage device I are provided. Hereinafter, an outline of the operation of the present embodiment configured as described above will be described. When a command for testing the entire system is transmitted from a higher-level device (not shown) to the system according to the present embodiment via an interface (not shown), the test is performed in the following procedure. Check the normality of.

Test of upper module MU itself Test of interface unit X and interface of each module Test of lower module MLG Test between lower modules MLG The details of the above test will be described below. Is for the control device UE of the upper module MU to confirm its own normality. The interface unit U3 with the host device is tested with an interface unit (not shown) in the host device using a test circuit U4. Is the control device MLGE in each module MLG from the control device UE.
Test communication with the upper module M at that stage.
Interface unit U1 in U and each lower module MLG
The normality of the interface unit MLG1 in the
This is confirmed using the test circuit U2 and MLG2. Each interface unit U
Although there are test means for transmitting and receiving information for a continuity test between the MLG 1 and the MLG 1, checking for missing information, checking for errors, and the like, details thereof are omitted. This test result is processed by the control device UE,
The data is stored in the storage device I in the upper module MU.

The function module itself tests the function module itself, and uses a function of testing and controlling the plurality of lower function modules MLG themselves in the upper module MU.
Performs only the test start synchronization process for each module MLG, and controls the control device ML in each module MLG.
The GE is the main component. In addition to the control device MLGE, the interface unit MLG1 performs a test using a test circuit MLG2, and the interface unit MLG3 performs a test using a test circuit MLG4. As described above, this processing is characterized in that each functional block performs the processing in parallel. The next test uses the link test control function for connecting the plurality of lower modules MLG described above. That is, a test between two or more modules is performed, and the upper module MU also performs a synchronization process between the modules. Here, the upper module MU performs a conflict process so that duplication does not occur in a combination of tests. In the same way, the test is applied to the part where the test can be performed in parallel. , And the processing combination order is stored in the storage device I in the upper module MU. In the test process, the test results are stored in the storage device MLGI in each module. These test results are reported to the upper module MU, temporarily stored in the storage device I, and used by the control device UE of the higher module MU. To the host device.

In addition, even when the higher-level device instructs not a test of the entire system but a test of a plurality of selected modules or a test between modules, the control device UE of the higher-level module MU also determines the combination of the combinations to be tested. It checks whether parallel processing is possible or not and performs the synchronization processing. Thereafter, a test is started for each module. As a result,
Each functional block reports to the upper module MU, and based on this, a report to the upper device is made. FIG. 5 is a diagram illustrating a configuration example of a system according to another embodiment of the present invention.
In this embodiment, the lower module link Z shown in FIG.
The interface X for connecting the upper module MU and the lower module MLG is shared by the link X, and the test method is the same as that of FIG. In addition,
As described above, the interface unit MLG1 and the MLG3 of the lower module MLG can be integrated. The connection information of the connection links Z between the lower modules MLG and the failure information of the interface device X are stored in the storage device MLG in the lower module MLG.
It is also possible to store in I.

According to the above embodiment, when a command is received from a higher-level device and a test in the system is performed, a test circuit in the module is shared and its startup control is performed from the higher-level module. An effect is obtained that a parallel processing test of a module or a functional block in the module becomes possible. The above embodiments are merely examples of the present invention, and it goes without saying that the present invention is not limited to these embodiments.

[0019]

As described above in detail, according to the present invention, a test such as a test of a module in a system or a test of a functional block in a module is completed within the module or the functional block. In this manner, a remarkable effect is achieved in that a distributed system test method and a device therefor that enable a parallel test from a higher-level control device can be realized.

[0020]

[Brief description of the drawings]

FIG. 1 is an operation flowchart showing details of a module test method according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a module according to a first embodiment.

FIG. 3 is a diagram illustrating a configuration of a module according to a second embodiment.

FIG. 4 is a diagram illustrating a configuration of a system according to a third embodiment.

FIG. 5 is a diagram illustrating a configuration of a system according to a fourth embodiment.

FIG. 6 is a diagram illustrating a configuration example of a conventional module.

[Explanation of symbols]

U: upper functional block, T: interface device, LN
(N = 2 to N): lower functional blocks, Y: connection links between lower functional blocks, A1: control device, B1, C1: test circuit, E12: interface unit, D1: storage device, E
N2: interface unit, CN, BN, EN: test circuit, EN1: main unit, EN3: interface unit, D
N: storage device, MU: upper module, X: interface device, MLG (G = 1 to g): lower module, Z:
Lower module connection links, UE: control device, U
1: Interface unit, U2, U4: Test circuit, U3:
Interface unit, I: storage device, MLGE: control device, MLG2, MLG4: test circuit, MLG1: interface unit, MLG3: interface unit, MLGI:
Storage device.

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-305652 (JP, A) JP-A-62-98445 (JP, A) JP-A-62-245362 (JP, A) JP-A-61-245362 283954 (JP, A) JP-A-3-186958 (JP, A) JP-A-4-207820 (JP, A) Yoshizo Takahashi, "Parallel processing mechanism" (issued August 25, 1989), Maruzen Co., Ltd. 252−254

Claims (5)

(57) [Claims] 1. A plurality of lower function block devices, a higher function block device, an interface device for connecting these devices,
In a module including a plurality of connection links for connecting the plurality of lower functional block devices, when a command for testing the entire module is received, the upper functional block device is configured to execute the higher functional block device itself. After testing the normality of the interface device and the normality of the interfaces of the interface device and the plurality of lower function block devices and the upper function block device, testing the plurality of lower function block devices and the plurality of lower functions A test method for a distributed system, wherein tests between block devices are performed in parallel. 2. A plurality of lower function modules, an upper function module, an interface device for connecting them, and a plurality of connection links for connecting the plurality of lower function modules with the module according to claim 1 as a constituent unit. When a command for testing the entire system is received, the higher-level function module performs a test of the normality of the higher-level function module itself,
After testing the normality of the interface unit and the interface sections of the plurality of lower function modules and the higher function module, the test of the plurality of lower function modules and the test between the plurality of lower function modules are respectively performed in parallel. A test method for a distributed system, characterized in that: 3. The test of the plurality of lower-level function modules and the test between the plurality of lower-level function modules include: a higher-level functional block device of each of the plurality of modules tests a normality of the higher-level functional block device itself; After testing the normality of the interface units and the interfaces of the plurality of lower functional block devices and the upper functional block devices, the test of the plurality of lower functional block devices and the test between the plurality of lower functional block devices are performed in parallel. 3. The method for testing a distributed system according to claim 2, wherein 4. A plurality of lower functional block devices LN (N =
2 to n), a higher function block device U, an interface device T connecting them, and a plurality of connection links Y connecting the plurality of lower function block devices LN. The device U can be multiplexed with a control device A1, a test circuit B1 in the upper function block device U, an interface unit E12 connecting the test circuit B1 and the interface device T, an interface unit E12, A test circuit C1 for testing between the interface devices T, connection information of the plurality of connection links Y, fault location determination information of the interface device T, failure location determination information of the upper function block device U, and the plurality of connection links A storage device D1 for storing the fault location determination information of the class Y, and the storage device D1 Control device A1 and the control device A
1 and the two test circuits B1 and C1 and the interface unit E12 via a connection line in the upper functional block device U, and the plurality of lower functional block devices LN are connected to a control device AN capable of multiplex processing. And an interface unit EN2 connecting the lower functional block device LN to the interface device T; a test circuit CN for testing between the interface unit EN2 and the interface device T; and a function of the plurality of lower functional block devices LN. A main unit EN1 to be realized, a test circuit BN for testing the main unit EN1, an interface unit EN3 between the lower functional block units LN, and the interface unit EN
3 and a storage device DN for storing fault position determination information for the lower-level functional block device LN and fault position determination information for the plurality of connection links Y, and the storage device DN The control device AN;
Further, the control device AN and the three test circuits CN, B
N, EN, the main unit EN1, and the interface units EN2, EN3 are connected via a connection line in the lower functional block unit. 5. A system in which a plurality of modules M according to claim 4 are connected, wherein a plurality of lower modules MLG are provided.
(G = 1 to g), an upper module MU, an interface device X for connecting them, the plurality of lower modules ML
In a system composed of a plurality of connection links Z connecting G to each other, the upper module MU is multiplexed, and a control device UE capable of performing a test in the upper module MU; An interface unit U1 for connecting to the interface device X;
A test circuit U2 for testing between the interface unit U1 and the interface device X, an interface unit U3 for connecting a higher system and the higher module MU, and a test circuit U4 for testing between the interface unit U3 and the higher system. A storage device I for storing the connection information of the plurality of connection links Z, the failure position determination information of the interface device X, and the failure position determination information of the plurality of connection links Z, and Is connected to the control device UE, and the control unit MLGE capable of multiplexing the plurality of lower modules MLG, an interface unit MLG1 connecting the lower module MLG and the interface device X, and an interface unit MLG1. A test circuit MLG2 for testing between the interface devices X; Serial interface section MLG3 between a plurality of lower-level modules MLG, the interface unit M
A test circuit MLG4 for testing LG3; a storage device ML for storing fault position determination information on the lower module MLG and fault position determination information on the plurality of connection links Z;
A test apparatus for a distributed system, comprising a GI, and wherein the storage device MLGI is connected to the control device MLGE.