JP2576345B2 - Multi-bit all match detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiple bit full match detection circuit, and more particularly to a multiple bit full match detection circuit used for testing a semiconductor random access memory.

[0002]

2. Description of the Related Art In order to simplify the description of a multi-bit all-match detection circuit of this kind, an all-match detection circuit having a 4-bit signal will be described as an example.

Referring to FIG. 7, this all match detection circuit includes a 4-bit input NAND circuit NAND3 for detecting all "1" of each 4-bit signal (1, 2, 3, 4), and an all "0". A 4-bit input NOR circuit NOR1 for detecting
Inverter circuit I for inverting the output of NOR circuit NOR1
NV2, NAND circuit NAND3 and inverter circuit IN
Two-input NAND circuit N that receives each output of V2
AND2. Table 1 shows the truth table.

[0004]

[Table 1]

FIG. 8 is an overall view showing an example of the layout of the 4-bit all-match detection circuit having the CMOS structure, and FIGS. 17, 18 and 19 are partial views. The area indicated by the dots indicates the polysilicon layer, the area indicated by the diagonally upward slanted line indicates the first aluminum wiring layer, and the area indicated by the diagonally upper right diagonal line indicates the second aluminum wiring layer.

Referring to FIG. 17, first, a first aluminum wiring AV
DD is connected to the P-type diffusion region P1 via the contact C1, and the polysilicon gates POLY4, POLY
3, POLY2 and POLY1 are connected to the aluminum wiring A1 via the contact C5. P-type diffusion region P1 and polysilicon gates POLY4, POLY
3, PLY is added to the overlapping part of POLY2 and POLY1.
MOS transistors QP4, QP3, QP2 and QP
1 are arranged and the first aluminum wiring AGND is connected to the contact C
2 and connected to the N-type diffusion region N1 and traverses the polysilicon gate POLY4 to the aluminum wiring A1 via the contact C7, and similarly from the contact C3 to the aluminum wiring traverses the polysilicon gate POLY3 and the contact C7. A1 is connected to the aluminum wiring A1 from the contact C3 across the polysilicon gate POLY2 via the contact C6, and is connected to the aluminum wiring A1 from the contact C4 across the polysilicon gate POLY1 via the contact C6. N-type diffusion region N1 and polysilicon gates POLY4, POLY3, POLY2
Similarly, NMOS transistors QN4, QN3, QN2 and QN1 are arranged in a portion overlapping with POLY1. Expressed in a transistor equivalent circuit diagram, it becomes a 4-input NOR as shown in FIG.

Referring also to FIG. 19, the first aluminum interconnection AGND is connected to the N-type diffusion region N1 via a contact C8, and a polysilicon gate POLY9,
It is connected to the aluminum wiring A5 via the contact C9 across the POLY10, POLY11 and POLY12. N-type diffusion region N1 and polysilicon gate POLY
9, POLY10, POLY11 and POLY12 overlap NMOS transistors QN9 and QN1.
0, QN11 and QN12 are arranged, connected from the first aluminum wiring AVDD to the P-type diffusion region P1 via the contact C10, traverse the polysilicon gate POLY9, and contact the aluminum wiring A5 via the contact C13. C11 to polysilicon gate POLY
10 and aluminum wiring A via contact C13
5, from the contact C11 to the polysilicon gate POL.
Y11 traverses to the aluminum wiring A5 via the contact C14 and from the contact C12 to the polysilicon gate PO.
It crosses LY12 and is connected to the aluminum wiring A5 via the contact C14. P-type diffusion region P1 and polysilicon gates POLY9, POLY10, POLY1
PMO1 and POLY12
S transistors QP9, QP10, QP11 and QP
12 are arranged. Expressed in a transistor equivalent circuit diagram, it becomes a 4-input NAND as shown in FIG.

[0008] Referring also to FIG.
A PMOS transistor QP5 is arranged at a portion where Y5 and the P-type diffusion region P1 overlap, and an NMOS transistor QN5 is arranged at a portion where POLY5 and the N-type diffusion region N1 overlap. From the first aluminum wiring AVDD to the contact C1 → PM
OS transistor QP5 is connected to first aluminum interconnection A2 via contact C16, and first aluminum interconnection AGN
From D to contact C2 → NMOS transistor QN5 →
It is connected to the first aluminum wiring A2 via the contact C17, and contacts C2 → N from the first aluminum wiring AGND.
MOS transistor QN5 is connected to first aluminum wiring A2 via contact C17, and is connected to first aluminum wiring A1.
Through the contact C15 to the polysilicon gate P
Connected to OLY5. This means that the signal of the first aluminum wiring A1 has an inverter function (logic inversion function).

Further, similarly, PMOS transistors QP7 and QP8 are arranged at a portion where polysilicon gates POLY7 and POLY8 overlap P-type diffusion region P1, and polysilicon gates POLY7 and POL8 are provided.
NMOS transistors QN7 and QN8 are arranged at a portion where Y8 and N type diffusion region N1 overlap, and are connected from first aluminum wiring AVDD of the power supply to first aluminum wiring A4 via contact C20 → PMOS transistor PQ7 → contact C22. , Also the first aluminum wiring A of the power supply
From VDD to contact C10 → PMOS transistor Q
P7 → first aluminum wiring A4 via contact C22
And the first aluminum wiring A4 to the through hole T2
Through the contact C8 → NMO from the ground first aluminum wiring AGND.
S transistors QN8 and QN7 → contact C19
Through the first aluminum wiring A3, through the through hole T1, from the first aluminum wiring A3 to the second aluminum wiring A20, and from the first aluminum wiring A2 through the contact C18 to the polysilicon gate. POLY7 and from the first aluminum wiring A5 to the polysilicon gate POLY8 via the contact C21.

As a result, a signal having a two-input NAND function is provided for the signals on the first aluminum wiring A2 and the first aluminum wiring A5.

Contacts C30, C31 and C32
From the first aluminum wiring AVDD of the power supply to the polysilicon gates POLYOP, POLY6P and POLY13P
And the source / drain regions of the adjacent PMOS transistors are separated by PMOS transistors QP0, QP6 and QP13.
3, C34 and C35 are connected to the polysilicon gates POLYON, POL from the ground first aluminum interconnection AGND.
NMO connected to Y6N and POLY13N
The source / drain region of the S transistor is separated by NMOS transistors QN0, QN6 and QN13.

The polysilicon gates POLY1 and POLY
12 via a contact C41, a first aluminum interconnection A11 and a contact C42, and a polysilicon gate P
OLY2 and POLY11 are connected to the contact C43, the first
The polysilicon gates POLY3 and POLY10 are connected by an aluminum wiring A12 and a contact C44, and the polysilicon gates POLY3 and POLY10 are connected by a contact C45, a first aluminum wiring A13 and a contact C46.
OLY9 is connected to contact C47 and first aluminum wiring A1.
4. Connect with contact C48.

From the above description, the layout diagram of the all match detection circuit shown in FIG. 8 has the function of the circuit diagram shown in FIG.

Generally, in the layout of FIG. 8, the horizontal direction (the direction perpendicular to the gate) is 1 at the wiring grid interval of the second aluminum.
Requires 3 pitches. For a larger number (n) of bits instead of four, the horizontal dimension can be expressed as:

[Horizontal size] = 2 × n + 5 pitch (1) Further, the number of gates of the PMOS and NMOS transistors connected to each bit is two each.

[0016]

As described above, in the conventional multi-bit all-match detection circuit described above, as the number of bits for which all-match detection is performed increases, the area occupied by the layout on a chip for realizing the same is increased. And the yield of chips has been reduced.

[0017]

According to the present invention, there is provided a multi-bit all-match detection circuit comprising n-bit (n is a natural number) all "0" detection and all-bit "1" detection means. in, connected in series to the power supply terminal (n + 1) 1 No. from the power supply terminal side of the number of PMOS transistors
An n-bit signal is connected to each of the gates of the first to nth PMOS transistors, and a control signal (or an inverted signal of the control signal) is connected to the gate of the (n + 1) th PMOS transistor from the power supply terminal side. An NMOS load transistor for applying a power supply potential to a gate is connected between the drain of the (n + 1) th PMOS transistor and a ground terminal, and the (n + 1) th PMOS transistor is connected.
All "0" s that output a signal from a connection point between the drain of the transistor and the drain of the NMOS load transistor
A detection circuit is connected in series to the ground terminal (n +
1) The n-bit signal is connected to each of the gates of the first to n-th NMOS transistors from the ground terminal side of the NMOS transistors, and the (n + 1) th NMOS transistor is connected to the (n + 1) -th NMOS transistor from the ground terminal side. Connecting an inverted signal of the control signal (or the control signal), connecting a PMOS load transistor for applying a ground potential to the gate between the drain of the (n + 1) th NMOS transistor and the power supply terminal, and connecting the (n + 1) th with the drain of the NMOS transistor and all "1" detector circuit for outputting a signal from a connection point between the drain of the PMOS load transistors, said power supply
(N + 1) th PMOS transistor from the terminal
Is the first from the power terminal side corresponding to the control signal.
PMOS transistor to n-th PMOS transistor
Block the current flowing through each of the
The (n + 1) th NMOS transistor from the
First from the ground terminal side in response to the control signal
NMOS transistor to nth NMOS transistor
In this configuration, the current flowing through each of the stars is cut off .

[0018]

[0019]

[0020]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a multi-bit, all-match detection circuit according to a first embodiment of the present invention.

The multi-bit, all-match detection circuit of this embodiment includes (n + 1) PMOS transistors connected in series from a power supply.
The transistors Q11 to Q1n and Q1E and the NMOS transistor Q1L having a power supply potential applied to the gate as a load between the drain and the ground terminal of the PMOS transistor Q1E.
The gates of 1 to Q1n and Q1E are connected to a multi-bit signal and a control signal (in this case, functioning at the time of "L" level).
And the connection point between the drain of the NMOS transistor Q1L and the drain of the NMOS transistor Q1L is set as the output B. The truth table of the output B has a NOR function as shown in Table 2. That is, the circuit is an all-zero detection circuit.

[0023]

[Table 2]

However, "1" of the output B means the on-resistance R11 of each of the transistors Q11 to Q1n and Q1E.
１R1n, R1E means a voltage determined by the ratio of the series resistance of the transistor Q1L to the ON resistance R1L, and “0” of the output B is the value of the ground potential.

The (n +) connected in series from the ground terminal
1) NMOS transistors Q21 to Q2n and Q
PMO having a ground potential applied to its gate as a load between the power supply terminal and the drain of NMOS transistor Q2E and NMOS transistor Q2E.
A multi-bit signal and a signal obtained by inverting a control signal by an inverter circuit INV1 are connected to the gates of the NMOS transistors Q21 to Q2n and Q2E, respectively. The drain of the NMOS transistor Q2E and the PMOS transistor Q2L Are connected to the output A at the drain connection point. The truth table of the output A has a NAND function as shown in Table 3. That is, all "1" detection circuits are provided.

[0026]

[Table 3]

However, "0" of the output A means that the on-resistance R2L of the transistor Q2L and the transistors Q2E and Q2
1 to Q2n, the respective on-resistances R2E, R21 to R2
This is a voltage determined by the ratio of the series resistance of n, and “1” of the output A is the value of the power supply voltage.

Therefore, unless the relationship between the threshold voltage of the inverter circuit INV0 and the threshold voltage of the NAND circuit NAND1 using the signals of the outputs B and A is not satisfied, the logical function will not be performed correctly.

[“A” voltage of output A] <[threshold voltage of NAND1] (2) [“1” voltage of output B><[threshold voltage of INV0] (3) CMOS The threshold voltage Vth of the inverter is P
MOS transistor threshold value Vtp, beta βp and N
The threshold value Vth of the MOS transistor and beta βn are expressed as follows.

[0030]

Generally, CMOS has Vtp = -Vtn,
In many cases, βn = βp, and in this case,

[0032]

## EQU1 ## Β is the dielectric constant in a vacuum of ε ₀ , the relative dielectric constant is ε ₀ x, and the effective carrier mobility μ is
ess, gate oxide film pressure Tox, MOS transistor channel length L, MOS transistor channel width W
When expressed using

[0034]

And the conductance gm is beta β,
Expressed by the gate-source voltage V _G and the threshold voltage Vt of the transistor,

[0036]

The ON resistance value of the transistor is the reciprocal of this.

Specifically, in order to set the threshold value Vth of the inverter INV0 to Vth = Vdd / 2, a PMOS
Channel length Lp, channel width Wp and N
Channel length Ln and channel width W of MOS transistor
n is 1 μm, 12 μm, 0.8 μm and 8
If it is μm, the threshold value of the NAND NAND1 is as follows.

[0039]

When Vtp = −Vtn, βn = βp, 9
The formula is as follows.

[0041]

Power supply voltage Vdd = 5V, Vth = 0.8V
Equation (10) gives 3.15 V, and Vdd /
Over two. Substituting the relationship of βn = βp into equation (7) yields equation (11).

[0043]

The "0" voltage of the output A is represented by the following equation.

[0045]

When the threshold value of the inverter is Vdd / 2, the on-resistance Rop of the PMOS transistor and the on-resistance Ron of the NMOS transistor of the inverter are approximately obtained.
Are almost the same, and equation (12) is approximated as follows. Note that the on resistances R2E, R21, R
, R2n are the same channel length Ln and channel width W
Suppose n. Therefore, the voltage of the output A “0” is

[0047]

Here, the ON resistance R1L, that is, the channel length Lp 'and the channel width Wp' of the load PMOS transistor may be determined so as to satisfy the relationship of the expression (2). For example, Vdd = 5V, Vtn = 0.8V, Lp = 1μ
m, Wp = 12 μm, Ln = 0.8 μm, Wn = 8 μ
m, Lp ′ = 1 μm,

[0049]

Similarly, the voltage of "1" of the output B is expressed by the following equation.

[0051]

When the threshold value of the inverter is Vdd / 2, the ON resistance Rop of the PMOS transistor and the ON resistance Ron of the NMOS transistor of the inverter are approximately obtained.
Are almost the same, and equation (15) is approximated as follows. Note that the on resistances R1E, R11, R
, R1n are the same channel length and channel width W
Suppose n.

[0053]

Here, the ON resistance R1L, that is, the channel length Ln 'and channel width Wn' of the load NMOS transistor may be determined so as to satisfy the relationship of the expression (3). Specifically, Vdd = 5V, Lp = 1 μm, Wp = 12 μ
m, Ln = 0.8 μm, Wn = 8 μm, Ln ′ = 1 μm
Then

[0055]

Is as follows.

When the channel length L and channel width W of each transistor are determined in this manner, the function of the circuit diagram shown in FIG. 1 operates, but when all "0" coincidences are detected and all "1" coincidences are detected. In some cases, a through current flows through the circuit in a DC manner. Therefore, when the all match detection circuit is not operated, the potential of the control signal is controlled (high level in FIG. 1) to prevent the through current. That is, power consumption is suppressed.

Next, FIG. 4 showing the entire layout when the number of bits of the signal is 4, and FIG.
The on-chip and layout of this embodiment will be described with reference to FIGS.

Referring first to FIG. 11, an inverter circuit INV1 having a polysilicon gate POLY1 as an input is provided.
Is connected from the first aluminum wiring AVDD of the power supply to the contact C6.
1 → PMOS transistor QP1 → Contact C64 from first aluminum wiring AGND via contact C62
→ NMOS transistor QN1 → Connected to first aluminum wiring A31 via contact C63, and connected to second aluminum wiring A51 via through hole T20.

Next, referring also to FIG. 12, all "1" s
The detection circuit is connected from the first aluminum wiring AVDD of the power supply to the first aluminum wiring A32 via the contact C67 → the PMOS transistor QP3 → the contact C66 and the contact C68 from the ground first aluminum wiring AGND →
NMOS transistors QN7, QN6, QN5, QN4
And the gates of QN3 are made of polysilicon POL.
Y3P, POLY7, POLY6, POLY5, POL
Y4 and POLY1 and polysilicon POLY3
P is connected to the ground first aluminum wiring via the contact C82 → the first aluminum wiring A42 → the through hole T24 → the second aluminum wiring A52 → the through hole T41.

Further, the all "0" detection circuit is provided for the first power supply.
Aluminum wiring AVDD to contact C67 → PMOS transistors QP4, QP5, QP6, QP7 and QP
8 → First aluminum wiring A33 via contact C70
Connected to the first aluminum wiring A33 via the contact C68 → the NMOS transistor QN8 → the contact C69 from the ground first aluminum wiring AVND, and the PMOS transistors QP4, QP5, QP6, Q
P7 and QP8 and NMOS transistor QN8
Gates are polysilicon POLY4, POL4
Y5, POLY6, POLY7, POLY8N,
The polysilicon POLY8N is contact C83 → first.
It is connected to the first aluminum wiring of the power supply via the aluminum wiring A44 → the through hole T25 → the second aluminum wiring A53 → the through hole T40. The polysilicon POL
Y8P has a through hole T from the second aluminum wiring A51.
21 → first aluminum wiring A41 → signal via contact C81, and a signal connected to polysilicon POLY1 is a control signal (inverted En in FIG. 1).

Referring also to FIG. 13, the inverter INV0 having an inverter function (logic inversion function) for the signal of the first aluminum wiring A33 is the first power supply.
The aluminum wiring is connected to the first aluminum wiring A34 via the contact C73 → PMOS transistor QP10 → contact C71, and the first aluminum wiring A34 from the ground first aluminum wiring via the contact C74 → NMOS transistor QN10 → contact C72. , And connected to the polysilicon gate POLY10 from the first aluminum wiring A33 via the contact C78.

First aluminum wiring A34 and second aluminum wiring A
On the other hand, a NAND circuit NAND1 having a function of a two-input NAND is configured such that a contact C
73 → PMOS transistor QP11 → contact C7
5 and connected to the first aluminum wiring A35, and from the first aluminum wiring of the power supply to the contact C75 → PMOS.
The transistor QP12 is connected to the first aluminum wiring A35 via the contact C75, and the contact C74 is connected to the NMOS transistor QN from the ground first aluminum wiring.
11 and QN12 → First via contact C77
The second aluminum wiring A50 is connected to the aluminum wiring A35, and is connected from the first aluminum wiring A35 through the through hole T11.
It is connected to the. Further, the first aluminum wiring A34 (output of the inverter circuit INV0) is connected to the polysilicon gate POLY11 via the contact C79, and the second aluminum wiring A54 (output of all "1" detecting portions) is connected to the through hole T23. 1 Aluminum wiring A43 → Contact C
It is connected to the polysilicon gate POLY12 via 84.

The contacts C50, C51, C52 and C53 are connected from the first aluminum wiring AVDD of the power supply to the polysilicon gates POLYOP, POLY2P, POLY9P.
And POLY13P, the source / drain regions of adjacent PMOS transistors are separated by PMOS transistors QP0, QP2, QP9 and QP13. Similarly, the contacts C54, C55, C56 and C57 are connected to the ground first aluminum wiring. AGND to polysilicon gate POLYON, POLY2N, POLY
9N and POLY13N connected to adjacent NMOS
The source / drain regions of the transistors are separated by NMOS transistors QN0, QN2, QN9 and QN13.

Further, in the equations (14) and (17), n =
The transistors QP3 and QN8 are laid out using the channel lengths Lp ′ and Ln ′ and the channel widths Wp ′ and Wn ′ of the transistor obtained as No. 4. In this case, in the layout of FIG. 4, 13 pitches are required in the horizontal direction (perpendicular to the gate) at the wiring grid interval of the second aluminum. For a larger number of bits instead of four, the horizontal dimension is expressed as:

[Lateral size] = 1 × n + 9 pitch (18) Further, the number of gates of the PMOS and NMOS transistors connected to each bit is one each.

As described above, as compared with the conventional circuit / layout, the size in the horizontal direction is n ≧ 4 and the present invention can be made smaller, and the number of input transistors becomes smaller irrespective of n.

FIG. 5 is a diagram showing another layout of the first embodiment of the present invention. FIG. 5 shows the arrangement intervals of the transistors QP4, QP5, QP6, QP7 and QP8 and QN3, QN4, QN5, QN6 and QN7 of the transistors of all "0" detection circuits and all "1" detection circuits as compared with FIG. Since there is no contact, the arrangement is relatively the same except that the size in the horizontal direction is smaller than that in FIG.

In the layout shown in FIG. 5, the horizontal direction (direction perpendicular to the gate) is 13-
Requires 5/3 pitch. For a larger number (n) of bits instead of four, the horizontal dimension can be expressed as:

[Lateral Size] = (4 × n + 28) / 3 Pitch (19) The 5/3 pitch is a value in the process of FIG. 5 when n = 4, and is smaller. The size X is expressed by the following equation.

[0071]

Next, a second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram of a second embodiment of the present invention. FIG. 2 showing the second embodiment is the same as FIG. 1 of the first embodiment.
However, since only the control signal for controlling the operation / non-operation of the all match detection circuit is changed to active high (all match detection operation at a high level), the same operation as in the first embodiment is performed. However, detailed description is omitted only for illustration.

FIG. 3 is a circuit diagram of a third embodiment of the present invention. In this embodiment, the logic of the output A of all "1" detection circuits and the output B of all "0" detection circuits is changed so that the NOR circuit is used without using the NAND circuit. The detailed description is omitted.

FIG. 6 is a circuit diagram of a fourth embodiment of the present invention. This embodiment is different from the first embodiment only in that an inverter for inverting the control signal En is removed.

In the above embodiment, the channel lengths Lp 'and Ln' and the channel widths Wp 'and Wn' of the load transistors Q1L and Q2L used for all "1" detection circuits and all "0" detection circuits are varied. , The load transistors Q1L used for all “1” detection circuits and all “0” detection circuits
A method may be adopted in which the dimensions of Q2L and Q2L are the same as normal ones, and the threshold value of the next-stage logic circuit is changed. In this case, the “1” potential of the output B and the “0” potential of the output A are obtained by the equations (12) and (15).
The dimensions of the transistor can be determined from equations (9) and (21) so as to satisfy the condition of equation (3).

[0077]

[0078]

As described above, the multi-bit all-match circuit of the present invention is connected in series from the power supply to the (n +
1) A multi-bit signal is connected to each of the first to n-th PMOS transistors counted from the power supply terminal side of the gates of the PMOS transistors, and counted from the power supply terminal side (n
A control signal is connected to the (+1) th PMOS transistor, and the (n + 1) th PMO counting from the power supply terminal side
An NMOS transistor to which a power supply potential is applied is connected as a load between the drain of the S transistor and the ground, and a signal is output as a signal connected between the drain of the (n + 1) th PMOS transistor and the drain of the NMOS transistor as a load. All “0” detection circuits and 1 to n counting from the ground side among the gates of (n + 1) NMOS transistors connected in series from the ground terminal
A multi-bit signal is connected to the nth NMOS transistor, and the (n + 1) th Nth counting from the ground terminal side
Connect the inverted signal of the control signal to the MOS transistor,
(N + 1) th NMO counting from the ground terminal side
A PMOS transistor to which a ground potential is applied is connected as a load between the drain of the S transistor and the power supply, and a signal in which the drain of the (n + 1) th NMOS transistor is connected to the drain of the PMOS transistor as a load is output. By having all "1" detection circuits, the number of input load transistors of many bits is reduced from four to two, and the area occupied on the layout on the chip is set relatively small even if n increases. Further, when the circuit function is not used, it is also possible to stop the through current by the input data by the control signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an all-matching circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an all-matching circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an all-matching circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a layout of the circuit shown in FIG. 1;

FIG. 5 is a diagram showing another layout for realizing the circuit of FIG. 1;

FIG. 6 is a circuit diagram of an all-matching circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional all matching circuit.

FIG. 8 is an example of a layout for realizing the circuit shown in FIG. 7;

FIG. 9 is a diagram showing a relationship between a NOR circuit and a CMOS transistor circuit diagram.

FIG. 10 is a diagram showing a relationship between a NAND circuit and a CMOS transistor circuit diagram.

FIG. 11 is a diagram showing a part of the layout shown in FIG. 4;

FIG. 12 is a diagram showing another part of the layout shown in FIG. 4;

FIG. 13 is a diagram showing still another part of the layout shown in FIG. 4;

FIG. 14 is a diagram showing a part of the layout shown in FIG. 5;

FIG. 15 is a diagram showing another part of the layout shown in FIG. 5;

FIG. 16 is a diagram showing a part of the layout shown in FIG. 5;

FIG. 17 is a diagram showing a part of the layout shown in FIG. 8;

FIG. 18 is a diagram showing another part of the layout shown in FIG. 8;

FIG. 19 is a diagram showing still another part of the layout shown in FIG. 8;

[Explanation of symbols]

AGND First aluminum wiring of ground AVDD First aluminum wiring of power supply A20, A50 to A54 Second aluminum wiring C1 to C22, C30 to C35, C41 to C48, C5
0 to C57, C61 to C79, C81 to C84 Contact (hole) T1 to T2, T11, T20 to T25, T40 to T41
Through holes POLY1-POLY12, POLY4 '-POLY
7 ', POLYON, POLYOP, POLY2N, P
OLY2P, POLY6N, POLY6P, POLY8
N, POLY8P, POLY9N, POLY9P, PO
LY13N, POLY13P, POLY3P Polysilicon (wiring) QP0 to QP13 PMOS transistor QN0 to QN13 NMOS transistor P1, P2, P3 P-type diffusion region N1, N2, N3 N-type diffusion region INVφ, INV1, INV2, INV3, INV4
INV5 Inverter circuit NAND0, NAND1, NAND2, NAND3
NAND circuit NOR1, NOR2 NOR circuit 1, 2,..., N Many-bit input signal En control signal (active high) Inverted control signal (active low) Q1E, Q2L, Q11-Q1n PMOS transistors Q2E, Q1L, Q21-Q2n NMOS transistor

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication // G11C 29/00 303

Claims (3)

(57) [Claims] 1. An (n + 1) PMOS transistors connected in series to a power supply terminal in a multi-bit, all-match detection circuit having all "0" detection means and all "1" detection means of n bits (n is a natural number). first from the power supply terminal side of the
An n-bit signal is connected to each of the gates of the nth to nth PMOS transistors, and a control signal (or an inverted signal of the control signal) is connected to the gate of the (n + 1) th PMOS transistor from the power supply terminal side; An NMOS load transistor for applying a power supply potential to the gate is connected between the drain and the ground terminal of the (n + 1) th PMOS transistor, and the (n + 1) th PMOS transistor is connected.
All "0" s that output a signal from a connection point between the drain of the transistor and the drain of the NMOS load transistor
A detection circuit is connected in series to the ground terminal (n +
1) The n-bit signal is connected to each of the gates of the first to n-th NMOS transistors from the ground terminal side of the NMOS transistors, and the (n + 1) th NMOS transistor is connected to the (n + 1) -th NMOS transistor from the ground terminal side. Connecting an inverted signal of the control signal (or the control signal), connecting a PMOS load transistor for applying a ground potential to the gate between the drain of the (n + 1) th NMOS transistor and the power supply terminal, and connecting the (n + 1) th with the drain of the NMOS transistor and all "1" detector circuit for outputting a signal from a connection point between the drain of the PMOS load transistors, said power supply
(N + 1) th PMOS transistor from the terminal
Is the first from the power terminal side corresponding to the control signal.
PMOS transistor to n-th PMOS transistor
Block the current flowing through each of the
The (n + 1) th NMOS transistor from the
First from the ground terminal side in response to the control signal
NMOS transistor to nth NMOS transistor
A multi-bit, all-match detection circuit for interrupting a current flowing through each of the transistors. 2. The multi-bit, all-match detection circuit according to claim 1, further comprising a NAND circuit to which an output of said all- "1" detection circuit and an inverted signal of an output of said all- "0" detection circuit are respectively input. 3. A NOR circuit having an inverted signal of the output of all the “1” detection circuits and an output of the “0” detection circuit as inputs, and an inverter circuit for inverting the output of the NOR circuit. 2. A multiple bit all match detection circuit according to 1.