JP2575797B2 - Ion beam deflection width detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion beam deflection width detection circuit useful for ion implantation of, for example, a semiconductor wafer or the like with an ion beam.

[Conventional technology]

FIG. 5 is a schematic view of a conventional ion implantation apparatus. In this figure, reference numeral 1 denotes a triangular wave, which is applied to the electrostatic deflecting plate 21. An ion beam 22 is deflected by the electrostatic deflecting plate 21. An outer box 23 is grounded via a resistor 24. twenty five
Is a current flowing to the ground when the ion beam 22 hits the outer case 23, 10 is an I monitor signal that extracts a voltage generated on the non-ground side of the resistor 24 by the current 25, 26 is placed on the outer case 23 A semiconductor wafer 27 is a mask having holes of the same dimensions as the semiconductor wafer 26.
The ion beam 22 in other places is prevented from hitting the outer box 23.

6A and 6B are a top view and a side view showing the relationship between the semiconductor wafer 26 and the mask 27. FIG. FIG. 7 shows a state where the deflection width of the ion beam 22 is appropriate, and FIG. 8 shows a state where the deflection width of the ion beam 22 is not appropriate.

 Next, the operation will be described.

The ion beam 22 deflected by the electrostatic deflecting plate 21 impinges on the semiconductor wafer 26 by the mask 27. This semiconductor wafer 26
The ion beam 22 hits the outer box 23 to generate a current 25.

The ion implantation amount at this time has a relationship of Q∝ implantation amount,
Q = ∫I _B dt (I _B is the value of the current 25). However, outer box 23
This holds only when the inflow amount of the ion beam 22 into the ion beam 22 is constant. Therefore, to meet this condition,
The mask 27 is provided with a hole of the size of the semiconductor wafer 26.

Now, as shown in FIG. 7, there is no problem if the deflection width of the ion beam 22 is larger than the size of the surface to be implanted of the semiconductor wafer 26, but as shown in FIG. If the size is smaller than the size of the surface to be implanted of the semiconductor wafer 26, the above formula is not satisfied, and the distribution of the amount of implanted material on the surface to be implanted is not averaged. Conventionally, to prevent this,
The operator of the device had checked before injection.

[Problems to be solved by the invention]

In the conventional method as described above, the operator must confirm the beam deflection width, but cannot completely monitor the deflection width of the ion beam 22 during ion implantation during the implantation time. Therefore, if the deflection width is small as shown in FIG. 8, there is a problem that the ion implantation cannot be performed uniformly on the entire surface of the semiconductor wafer 26.

The present invention has been made to solve such a problem, and an object of the present invention is to provide an ion beam deflection width detection circuit capable of monitoring that the deflection width of an ion beam is equal to or larger than a predetermined reference.

[Means for solving the problem]

An ion beam deflection width detection circuit according to the present invention detects an inflection point of an AC signal for deflecting an ion beam so as to scan over a region to be implanted on a semiconductor wafer, and transitions to an activated state. Timing setting means for outputting a timing signal whose state width is controllable; deflection width judging means for outputting a detection signal indicating whether or not the ion beam is hitting the region to be implanted; and Holding means for holding the detection signal when in the activated state. The timing setting means includes: a first comparator for comparing whether or not the AC signal is at or above a first level;
And a gate for outputting the logical sum of the outputs of the first and second comparators.

[Action]

In the present invention, the inflection point of the AC signal for deflecting the ion beam is detected by the timing setting means and output as a timing signal, and the deflection width determination means indicates whether or not the ion beam hits the outside of the semiconductor wafer. A detection signal is detected. The width of activation of the timing signal can be controlled by setting the first and second levels. Therefore, by examining the detection signal held by the holding means when the timing signal is input, it is possible to detect whether the deflection width of the ion beam is larger than the diameter of the region to be implanted.

〔Example〕

FIG. 1 is a basic circuit diagram showing an embodiment of an ion beam deflection width detecting circuit according to the present invention.

5, the same reference numerals as those in FIG. 5 denote the same components, and 2 denotes an operational amplifier for comparing the positive half wave of the triangular wave 1; 3 denotes an operational amplifier for comparing the negative half wave of the triangular wave 1; Is a variable resistor for setting the comparison reference value V ₁ of the operational amplifier 2, 4 a is a timing signal output by comparing the upper half wave of the triangular wave 1, 5 is the comparison reference value of the operation amplifier 3 A variable resistor for setting V ₂ , 5 a is a timing signal output by comparing the lower half wave of the triangular wave 1, 6 is a Zener diode for changing the voltage to the voltage level of the digital IC, 7 is a current A suppression resistor, 8 is a NOR gate that takes the inverted OR of a signal obtained by comparing the positive half wave and the negative half wave of the triangular wave 1, 9 is a timing signal output from the NOR gate 8, and 11 is the timing signal output from the NOR gate 8. Comparing I monitor signal 10 Over preparative to the operational amplifier, 12 a comparison variable resistor for setting the reference value V _3, the detection signal is output is the comparator in the operational amplifier 11 13 of the operational amplifier 11, 14 as a holding means The latch circuit latches the detection signal 13 according to the timing signal 9. 100 is a timing setting means, and 200 is a deflection width determining means.

FIG. 2 is a diagram showing a configuration block of the ion beam deflection width detection circuit shown in FIG. 1, and the same reference numerals as those in FIG. 1 indicate corresponding parts.

Next, FIGS. 3 (a) to (e) and FIGS. 4 (a),
The operation will be described with reference to the waveform diagram of FIG.

When the ion beam 22 hits the mask 27 at the inflection point of the changing triangular wave 1 as shown in FIG.
Does not hit the ion beam 22, the I monitor signal 10 becomes 0V. That is, the deflection width of the ion beam 22 is
In order to detect that the size is larger than the size of the injection surface 26, it is sufficient to detect that the I monitor signal 10 is 0V at the inflection point of the triangular wave 1. Therefore, in order to take the timing to detect the triangular wave 1 first, the triangular wave 1 is compared with the reference value near the maximum value of the triangular wave 1 as shown in FIG.
When comparison is performed with V ₁ and V ₂ , waveforms as shown in FIGS. 3 (c) and 3 (d) appear. When these timing signals 4a and 5a pass through the NOR gate 8, a timing signal 9 indicating an inflection point as shown in FIG. 3 (e) is obtained.

Further, in order to detect that I monitor signal 10 is 0V, it may be Comparator an I monitor signal 10 in 0.1V~0.5V about higher comparison reference value V ₃ than 0V.

If the deflection width of the ion beam 22 is normal, the fourth
As shown in FIG. 4A, the I monitor signal 10 is shown in FIG.
Should fall in response to the inflection point of the triangular wave 1 shown in FIG. 7, when the timing signal 9 is at the “L” level (0 V
), The detection signal 13 should be at the “L” level (0 V). Conversely, when the deflection width is insufficient, the detection signal 13 becomes “H” level (5 V). Therefore, the detection signal 13 output from the deflection width determining means 200 by the latch circuit 14 is changed to the timing signal 9 output from the timing setting means 100.
If the level of the detection signal 13 is checked by latching according to the above, it is possible to determine whether or not the deflection width of the ion beam 22 is normal.

In the above embodiment has been using a variable resistor 4,5,12 to a circuit for setting the comparison reference value _{V 1, V 2, V 3} , may use other voltage sources.

Although the triangular wave 1 having only the AC component is shown as the AC signal, the signal may be a DC-biased signal, and the same applies to other signals. Further, the I monitor signal 10 may be a signal that changes according to the deflection width of the ion beam 22.

〔The invention's effect〕

As described above, the present invention detects an inflection point of an AC signal that deflects an ion beam so as to scan over a region to be implanted of a semiconductor wafer, and transitions to an activated state. Timing setting means for outputting a controllable timing signal; deflection width determining means for outputting a detection signal indicating whether or not the ion beam has hit the region to be implanted; and the timing signal being in the activated state Holding means for holding the detection signal at a time, wherein the timing setting means outputs the first
And a second comparator for comparing whether the AC signal is higher than the first level or not.
And a gate for outputting the logical sum of the outputs of the first and second comparators, so that the width of the activation of the timing signal is first and second. The control can be performed by setting the second level, and a simple and inexpensive circuit configuration can stably detect whether the deflection width of the ion beam is above a certain reference. And the timing signal can be adjusted.
It can operate even if the frequency of the vertical triangular wave is significantly different. Further, there is an effect that the configuration can be made using only the X and Y scan signals and the I monitor signal which are provided as standard in the ion implanter.

[Brief description of the drawings]

FIG. 1 is a basic circuit configuration diagram showing one embodiment of an ion beam deflection width detection circuit of the present invention, FIG. 2 is a diagram showing a configuration block of the ion beam deflection width detection circuit shown in FIG. 1,
3 and 4 are waveform diagrams of main signals for explaining the operation of the present invention, FIG. 5 is a schematic diagram of a conventional ion implantation apparatus, and FIG. 6 shows a positional relationship between a mask and a semiconductor wafer. FIGS. 7 and 8 are views showing the deflection state of the ion beam. In the figure, 1 is a triangular wave, 2, 3 and 11 are operational amplifiers, 5 and 12 are variable resistors, 6 is a Zener diode, 7 is a resistor, and 8 is
NOR gate, 9 is a timing signal, 10 is an I monitor signal, 1
3 is a detection signal, 14 is a latch circuit, 100 is timing setting means, and 200 is deflection width determination means. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. An inflection point of an AC signal for deflecting an ion beam so as to scan over a region to be implanted on a semiconductor wafer, and transition to an activated state, and the width of the activated state is controllable. Timing setting means for outputting a certain timing signal, deflection width determining means for outputting a detection signal indicating whether or not the ion beam has hit the region to be implanted, and detecting when the timing signal is in the activated state. Holding means for holding a signal, wherein the timing setting means includes: a first comparator for comparing whether the AC signal is at or above a first level;
A second comparator for comparing whether the AC signal is at or below a second level lower than the first level;
A gate for outputting a logical sum of outputs of the first and second comparators.