JP2574796B2 - Communication control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a communication control technology and a technology particularly effective when applied to serial communication between microprocessors.
For example, in a serial communication system using a modem (MODEM), the present invention relates to a technique effective for use in a serial communication device that performs communication according to a byte synchronization protocol.

[Prior Art] Conventionally, communication LSIs such as μPD7201A manufactured by NEC Corporation have been provided to enable serial communication between microprocessors. FIG. 3 shows an example of a system using the communication LSI μPD7201A.

That is, the system bus B is added to the microprocessor CPL.
The DMA controller DMAC and the serial communication LSI SIO are connected to the memory MEM via the US. Between the serial communication LSI SIO and the communication line, there is provided a modem MODEM for modulating and demodulating transmitted / received data and forming a clock from received data.

By the way, in communication according to a byte synchronization type protocol called BISYNC, a synchronization pattern SYN called a SYNC character or a flag pattern as shown in FIG. 2, a text area TXT containing data to be communicated, and an error detection called a CRC character. When transmitting a message (frame) consisting of a check code area BCC containing a code, an idle pattern PAD called a pad character is used to confirm that the first and last characters of one transmission have been correctly transmitted to the modem. Has been added.

Conventionally, a communication LSI such as the μPD7201A has a 2-byte control register for storing a SYNC character (flag pattern), and a synchronization pattern (SYNC character) and an idle pattern (pad character) are stored using this control register. (NEC Corporation issued 1984, “μPD7201A MPSC
User's Manual, page 70 to page 73).

[Problems to be Solved by the Invention] In a conventional communication LSI capable of serial communication in accordance with the BISYNC protocol, a synchronous pattern and an idle pattern are transmitted using the same control register. And the synchronization pattern must be rewritten. In particular, when transmitting a message of a plurality of frames, it is necessary to rewrite an idle pattern and a synchronization pattern every frame, and there is a problem that a control sequence (microprogram) becomes complicated.

An object of the present invention is to simplify a control sequence at the time of transmission in serial communication between microprocessors.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in the communication LIS, a register for setting an idle pattern to be transmitted at idle before transmission is provided separately from a register for setting a synchronization pattern added to the head of data to be transmitted. is there.

[Operation] According to the above means, at the time of system startup, if the synchronization pattern and the idle pattern are set in separate registers, it is not necessary to rewrite the register each time a message is transmitted, thereby making it possible to transmit the message at the time of transmission. Can be achieved.

 Hereinafter, an embodiment of the present invention will be described with reference to FIG.

[Embodiment] In this embodiment, the present invention is applied to a serial communication unit as a communication LSI. The serial communication unit 10 includes a transmission unit and a reception unit,
FIG. 1 shows the configuration of the transmitting section.

The transmitting unit includes a transmission data FIFO 11 in which data to be transmitted is stored in a plurality of bytes, a shift register 12 for extracting the transmission data stored in the transmission data FIFO 11 byte by byte, converting the data into serial data, and outputting the serial data. 2-byte flag pattern register that can set synchronization pattern
Has 13 Data to be transmitted to the transmission data FIFO 11 by the microprocessor or the DMA controller via the interface circuit 14 is sequentially transferred from the system memory. Although not particularly limited, in this embodiment, the synchronization pattern set in the flag pattern register 13 is configured to be directly output on the transmission line.

The communication LSI 10 of this embodiment is provided with an idle pattern register 15 for setting an idle pattern to be inserted before and after a frame to be transmitted, and the idle pattern set in the idle pattern register 15 is provided. Is transferred to the shift register 12 for transmission,
It is configured to be exchanged for a serial signal and output.

The idle pattern register 15 stores the SYNC at the beginning of the frame.
It is composed of two bytes so that different patterns can be set as an idle pattern inserted before the byte (synchronous pattern) and an idle pattern inserted after the check code at the end of the frame.

In the communication LSI of this embodiment, a synchronization pattern is set in the flag pattern register 13 and an idle pattern is set in the idle pattern register 15 before starting transmission. When a transmission enable signal instructing transmission is input from the microprocessor, the preceding idle pattern in the idle pattern register 15 is immediately transferred to the shift register 12, and the idle pattern is transmitted. Then, when the transmission data is sent from the system memory and enters the FIFO 11, the transmission of the idle pattern is interrupted, and the 2-byte synchronization pattern in the flag pattern register 13 is output instead. And. When the transmission of the 2-byte synchronization pattern ends, the transmission data
The first transmission data in the FIFO 11 is transferred to the shift register 12, and is transmitted continuously in a synchronous pattern.

In addition to the shift register 12, the transmission data stored in the transmission data FIFO 11 is a CRC calculator 1 for calculating an error detection code called CRC (cyclic code check).
When the transmission of one frame of transmission data is completed, a check code is transmitted from the CRC calculator 16. Subsequently, the post-write idle pattern in the idle pattern register 15 is transferred to the shift register 12, converted into a serial signal, and output.

Transmission control according to the above-described procedure is executed by a control signal output from the control unit 17 of, for example, a microprogram control method.

In the above embodiment, the synchronization pattern set in the flag pattern register 13 is configured to be directly output on the transmission line. However, the synchronization pattern in this register is also temporarily transferred to the shift register 12 like the idle pattern. The transmission can be performed after the transmission.

Further, in addition to the BISYNC protocol, the communication LSI may have a configuration in which communication according to, for example, an HLDC (High Level Data Link Control) protocol can be performed by one LSI. Can be applied to such a communication LSI.

As described above, the above-described embodiment sets the idle pattern to be transmitted at the time of idle before transmission, separately from the register for setting the synchronization pattern added to the head of the data transmitted in the communication LIS. Since registers are provided, when the system starts up, if the synchronization pattern and idle pattern are set in separate registers,
Since there is no need to rewrite the register each time each message is transmitted, there is an effect that the control sequence at the time of transmission in serial communication between microprocessors is simplified.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in the above embodiment, the idle pattern register 15 has been described as being composed of two bytes. However, if the leading idle pattern and the trailing idle pattern are the same, the idle pattern register 15 must be composed of one byte. Is also possible.

In the above description, the invention made by the inventor was mainly applied to a communication LSI for performing communication in accordance with the BISNC protocol, which is the field of application, but the present invention is not limited to this. The present invention can be generally used for communication LSIs according to a protocol requiring an idle pattern other than a pattern (flag pattern).

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the communication control device that performs communication according to the BISYNC protocol, it is not necessary to rewrite the idle pattern and the synchronization pattern, thereby simplifying a control sequence at the time of transmission in serial communication between microprocessors.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the configuration of a receiving unit when the present invention is applied to a serial communication LSI, and FIG. 2 is a diagram showing an example of a frame configuration of each received data of a byte synchronous protocol. FIG. 3 is a block diagram showing a configuration example of a microprocessor system using a communication LSI. 10 communication LSI, 11 transmission data FIFO, 12 shift register, 13 flag pattern register, 15 idle pattern register, 16 CRC calculator, 17 control unit, CPU Microprocessor, SIO …… Communication LSI
(Serial communication unit), MEM …… Memory, MODEM ……
modem.

Claims (2)

(57) [Claims] A CPU and a DMA interconnected to a system bus.
A serial communication controller for performing serial communication between the system bus and a communication line in a communication system including a C and a memory, wherein the FIFO stores data transferred from the memory by the CPU or the DMAC. A shift register for converting the data of the FIFO into a serial signal, and whether or not the beginning and end of transmission of one transmission frame including a synchronization pattern, a text area for entering communication data, and an error detection check code have been correctly transmitted. Communication control, comprising: a first register for setting the synchronization pattern and a second register for setting the idle pattern so that an idle pattern for confirming whether the idle pattern is added to the transmission frame and transferred. apparatus. 2. The communication control device according to claim 1, wherein said idle pattern set in said second register is converted into a serial signal by said shift register.