JP2571049B2 - Analog-to-digital converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an analog-to-digital converter,
In particular, the present invention relates to a device in which the offset of the built-in amplifying means is compensated.

<Prior Art> As an analog-to-digital converter, a device called a double integral type is well known. This applies the analog signal Es predetermined time T ₁ to the integrator, then the reference voltage -eR of opposite polarity is applied to the integrator and Es, the output of the integrator from when applying -eR 0 Is counted by a counter, and the count value is used as a digital signal of Es. Tx is In the calculated, eR, since T ₁ are both known, Tx is proportional to Es, the count value of Tx can be said digital value of Es.

By the way, when Es has a very small value such as an output from a strain gauge type load cell, it is supplied to an integrator after being amplified by an amplifier. However, when the signal is amplified by the amplifier, the digital signal is affected by the offset voltage of the amplifier. In particular, if there is a change in temperature or a change with time, the offset voltage becomes large, and the effect cannot be ignored.

Therefore, it has been proposed to eliminate the influence of the offset voltage by configuring as shown in FIG. 8 (see Nikkei Electronics, February 16, 1981, pages 254 to 255). In the figure, when an analog signal Es is supplied, the control circuit 2
Close the analog switch 4,5,6,7,8, open the analog switch 9,10,11,12,13, close the 1/2 T ₁ has elapsed after the analog switches 10, 11, 12, 13, the analog switch 5 , 6, 7, and 8 are opened. After a further 1/2 T ₁ elapsed, open the analog switch 4, closing the analog switch 9. Then, the counting in the control circuit 2 is started, and the counting is continued until the comparator 15 detects that the output of the integrator 14 has become 0. In addition, 16 and 17 are preamplifiers, and 18 is an inverting amplifier.

During the first T _1/2, the input signal of the preamplifier 16, 17 Es +
ΔV, which is amplified as it is by the inverting amplifier 18,
The output signal of K (Es + ΔV) is supplied to the integrator 14.
Here, K is the total gain of the preamplifiers 16 and 17 and the inverting amplifier 18, and ΔV is the offset voltage of the preamplifiers 16 and 17.
During the next T _1/2, the input signals of the preamplifiers 16 and 17 are −Es + △
V, but this amplified signal is inverted by the inverting amplifier 18,
The integrator 14 is supplied with K (Es- 器 V). As a result Tx
Is And the offset voltage ΔV can be compensated.

<Problems to be Solved by the Invention> In order to perform A / D conversion accurately with the above technology, Es + △ V and E
it is necessary to supply to the preamplifier 16, 17 s-△ and V by T _1/2 hour. However, due to the influence of the C and R distribution constants inside the preamplifiers 16 and 17 and the C and R for phase compensation, Es + △ V
When the voltage is switched from Es to ΔV, an excessive response delay occurs as shown in FIG. 9 and A / D conversion cannot be performed accurately.

<Means for Solving the Problems> A first invention for solving the above problems is a device for amplifying an analog signal and an output of the amplifying device, which are analog to the above-described conventional device. A first output obtained by amplifying a value obtained by adding an offset amount ΔV to the signal in a positive direction;
Switching means provided in the amplifying means so as to switch to a second output obtained by amplifying a value obtained by adding the offset amount ΔV to the analog signal in the negative direction; conversion means for converting the output of the amplifying means into a digital signal; The first and second outputs based on the reference analog signal supplied to the means are respectively converted by the conversion means to obtain an offset amount digital signal corresponding to the offset amount based on the difference between the first and second reference digital signals. (1) adding or subtracting a digital signal obtained by converting one of first and second outputs based on a measured analog signal different from the reference analog signal by a converting means and an offset amount digital signal, Second to calculate a digital signal corresponding to the measured analog signal
When the offset amount digital signal is calculated by the calculating means and the first calculating means, the first and second outputs are selectively supplied to the converting means, and a predetermined time has elapsed since the selective supply was performed. And control means for causing the conversion means to perform the conversion after each lapse.

The second invention, like the first invention, has an amplifying means, a switching means, an exchanging means, a control means, and a means for calculating a digital signal corresponding to an offset amount. Further, a digital signal corresponding to a predetermined drift amount is added to or subtracted from the previous offset amount digital signal in accordance with the magnitude of the offset amount digital signal and the previous offset amount digital signal to calculate a drift amount compensation offset digital signal. And a digital signal obtained by converting one of the first and second outputs based on a measured analog signal different from the reference analog signal by the converting means and a drift compensation offset amount digital signal by adding or subtracting the digital signal. Means for calculating a digital signal corresponding to an analog signal.

<Operation> In the first invention, assuming that the reference analog signal is E and the offset amount is ΔV, the reference analog signal is supplied to the amplifying means, and the first and second outputs are controlled by controlling the switching means. Are obtained, which are K (E + ΔV) and K
(E−ΔV). K is the gain of the amplifying means. Here, for example, after a predetermined time has elapsed since the switching means was switched so as to generate the first output, digital conversion is performed by the conversion means. Similarly, the second
After a lapse of a predetermined time from the switching of the switching means so as to generate the above-mentioned output, digital conversion is performed by the converting means. Since the conversion is performed after a lapse of time after the switching is performed, neither the first output nor the second output to be converted is affected by the transient response of the amplifying unit due to the switching. . Therefore, this first
And the second reference digital signal is DK (E + ΔV) and
DK (E-ΔV). The difference between the first and second reference digital signals is ± 2DK △ V. And this is 1/2
± DK △ V becomes an offset amount digital signal corresponding to the offset amount. This is calculated by the first calculation means. Assuming that the measured analog signal is Ex, this is supplied to the amplifying means, and the switching means is controlled by the control means, whereby one of the first and second outputs K (Ex ± △ V) is obtained. . By converting this by the conversion means, DK (E _x ± △ V) is obtained. Therefore, when DK △ V is used as the offset amount digital signal,
(Ex + ExV) or subtract DK △ V from DK (Ex- △ V)
DKEx obtained by digitizing the measured analog signal Ex without being affected by the offset. When -DK △ V is used, this is changed to DK (Ex + △ V)
Or by subtracting -DK @ V from DK (Ex- @ V), a digitalized DKEx can be similarly obtained without being affected by the offset of the measured analog signal Ex.

In the second invention, an offset amount digital number DK # V can be obtained as in the first invention. For example, when obtaining the DK △ V, when the previous offset amounts digital signal and DK △ V _1, in the case towards the DK △ V is large, the it can be seen that the offset amount is due connexion increased to drift, obtaining a drift amount compensating offset voltage DK △ V ₂ by adding a predetermined drift amount corresponding digital signal DK △ d in DK △ V _1. DK △ V
And There DK △ V ₁ is smaller than, since it is understood that the offset amount is due connexion reduced drift, by subtracting DK △ d from DK △ V _1, to obtain a DK △ V _2. Then, when the reference analog signal Ex is supplied to the amplifying means, the offset amount at that time becomes ΔV ₂
Therefore, DK (Ex + ΔV ₂ ) is obtained as one of the digital signals of the first and second outputs. Hereinafter, DKEx is obtained in the same manner as in the first invention.

<Effects> As described above, in the present invention, instead of switching the analog signal while the conversion unit is performing the conversion operation,
An offset amount digital signal is obtained based on a digital signal of an amplified signal obtained by adding an offset amount to a reference analog signal in a positive direction and an amplified signal added in a negative direction, and the offset amount digital signal is included in the digital signal of the measured analog signal. The offset amount is compensated by the offset amount digital signal. In addition, when calculating the offset digital signal, the conversion means converts the two amplified signals to which the positive or negative offset is added into digital signals, so that the amplification means to which the positive or negative offset is added is converted. In the present invention, switching is performed by the switching means at predetermined time intervals rather than conversion by the conversion means. In the present invention, when the conversion means performs the conversion, the switching of the amplification means is performed. The effects such as the transient response delay occurring in the output have converged. As a result, the transient response delay caused by the switching does not affect the digital signal, so that accurate conversion can be performed, and the conversion can be performed promptly and accurately.
Moreover, in order to avoid the influence of the transient phenomenon caused by the switching of the switching means, there is no need to separately provide a sample and hold circuit or a circuit for generating a signal for causing a sample to be held after the transient phenomenon is contained in this circuit. , Avoiding the complexity of the circuit.

<Embodiment> FIGS. 1 to 4 show a first embodiment. In this embodiment, as shown in FIG. 3, the present invention is applied to an apparatus for filling a granular material 42 contained in a reservoir hopper 40 into a weighing hopper 44 disposed below the reservoir hopper 40 by a constant weight. Was carried out. The quantitative filling is performed by rotating a screw 46 provided in a reservoir hopper 40 by a motor 48, thereby supplying the granules 42 to the weighing hopper 44, and by using the weight of the supplied granules 42 to a load cell. 50, and when the detected weight reaches a preset target weight value TW, the motor 48
By stopping the operation.

The control of the motor 48 is performed based on a control signal received by the control unit 52 from the CPU 34 shown in FIG. 1 via the I / O port 32. At the beginning of filling the weighing hopper 44, the CPU 34
_{The H} signal is supplied to the control unit 52 to rotate the motor 48 at a high speed to supply a large amount of granular material in a short time as shown by a symbol a in FIG. During this time, the analog weighing signal of the load cell 50 is converted into a digital weighing signal as described later and is input to the CPU 34. When the digital weighing signal becomes the switching weight SW which is smaller than the target weight value TW but is relatively close, the CPU 34 supplies the _VL signal to the control unit 52 to rotate the motor 48 at a low speed. As shown by the symbol b, the supply amount is reduced, the impact applied to the load cell 50 is reduced, and high-precision weighing can be performed. Then, when the digital weighing signal becomes equal to TW, the CPU 34 eliminates the _VL signal and stops the motor 48. When the motor 48 is stopped, there is already powdery material from the reservoir hopper 46 to the weighing hopper 44. After waiting for the time t necessary for the disturbance to settle down (see FIG. 3), the CPU 34 reads the digital weighing signal converted from the stable analog weighing signal, as described later, so that the CPU 34 After storing the accurate weight of the powdery or granular material, the gate opening signal G is supplied to the cylinder 54 for opening the discharge gate 52 provided on the weighing hopper 44, and the articles are discharged from the weighing hopper 44 (the (See FIG. 3, symbol C). Hereinafter, in the same manner as described above, the weighing hopper
44 is filled with the granular material by a constant weight and discharged. Note that the program of the CPU 34 for performing such an operation is publicly known, and thus detailed description is omitted.

When digitizing the analog weighing signal of the load cell 50, since this analog weighing signal is a weak signal,
Only after amplification can it be digitized. Therefore,
As shown in FIG. 1, the analog weighing signals are
After amplification in 7 and 18, integrator 14, comparator 15, counter 3
The digital signal is digitized by a double integrator A / D converter composed of 0 and the like, and the digital signal includes amplifiers 16, 17, and 18.
The offset voltage ΔV is included, and it is necessary to compensate for the offset voltage ΔV.

For example, closing analog switches 5, 6, 7, 8
When the analog signal E is supplied to the amplifiers 16 and 17, the output of the amplifier 18 is K (E + △ V) as described in the section of the prior art.
Becomes Similarly, when the analog switches 10, 11, 12, and 13 are closed and the analog signal E is supplied to the amplifiers 16 and 17,
The output of the amplifier 18 is K (E- △ V). Therefore, K
When the signals obtained by digitizing (E + ΔV) and K (E−ΔV) are DK (E + ΔV) and DK (E−ΔV), DK
By adding (E + ΔV) and DK (E−ΔV) and dividing by 2, the digital signal DKE of the analog signal E can be obtained. As shown in FIG. Compensating for the offset voltage ΔV in this way when the signal is changing requires a relatively long time to obtain the digital signal DKE, making continuous metering impossible.
Speed control and target weight of motor 48 in switching weight SW
There is a possibility that the stop control of the motor 48 in the TW cannot be performed with high accuracy.

Therefore, in this embodiment, as shown by reference numeral d in FIG. 4, when the quantitative filling is completed and the weighing signal E is stable, DK (E + ΔV) and DK (E−ΔV) , And the difference between the two is divided by 2 to obtain a digital signal DK 相当 V corresponding to the offset voltage 、 V. Next, during the filling, which is performed until the quantitative filling is completed and the analog weighing signal is stabilized, the analog weighing is performed. Signals DK (E ₁ + ΔV), DK obtained by digitizing K (E ₁ + ΔV), K (E ₂ + ΔV)... Which are obtained by amplifying signals obtained by adding offset voltages to signals E ₁ , E ₂ . (E ₂ + △ V)… from
.. Are subtracted to obtain DKE ₁ , DKE ₂ ... To compensate for the offset voltage.

Therefore, as shown in FIG.
Flip flop 22, JK flip flop 24,
AND gates 26, 28 and 29 are provided. As shown in FIG. 2, the pulse generator 20 has a predetermined period T ₁ + T ₂ (T ₁ is a predetermined period for supplying the output of the amplifier 18 to the integrator 14, and T ₂ is If -eR is supplied to
To require until the output of the integrator 14 becomes zero and the prediction set somewhat longer than the time which the time) and falls every ▲ ▼ pulse, stand each time the ▲ ▼ pulse has elapsed from the falling connexion T ₂ hours Generates a falling ▲ ▼ pulse. This ▲
The pulse is input to the S terminal of the RS flip-flop 22, and the pulse is input to the R terminal of the RS flip-flop 22. The RS flip-flop 22 outputs the F / F output at the H level when the ▲ ▼ pulse falls, ▲
When the pulse falls, the output is set to the H level. The F / F output is supplied to the analog switch 4 and also to the AND gate 29. The analog switch 4 is closed when the F / F output is at the H level.

The gate open signal is also supplied to the AND gate 29 from the CPU 34 via the I / O port 32. The output of the AND gate 29 is supplied to the input of a JK flip-flop 24. Each time the output of the AND gate 29 supplied to the input falls, the JK flip-flop 24 outputs Q at that time.
Invert output, output. The Q output is supplied to analog switches 5, 6, 7, and 8. These analog switches 5, 6, 7, and 8 are closed when the Q output is at the H level. The output is supplied to the analog switches 10, 11, 12, and 13, and the analog switches 10, 11, 12, and
13 is closed when the output is at the H level.

Returning to the original state, the output of the RS flip-flop 22 is supplied to an AND gate 26 to which the output of the comparator 15 is also supplied. The output of the AND gate 26 is supplied to the analog switch 9, and the analog switch 9
Is closed when the output is at the H level. This and gate
The output of 26 is also supplied to an AND gate 28, which is also supplied with a clock pulse CL. The output of this AND gate 28 is also supplied to a counter 30. When the output of the AND gate 26 is at the H level, the counter 30 outputs a clock pulse supplied through the AND gate 28.
The CL is counted, and the count value is supplied to the CPU 34 via the I / O port 32. The reset of this counter 30 is
This is performed by a reset signal supplied from I / O port 32 from 34. The CPU 34 responds to the fall of the output C of the comparator 15 supplied via the I / O port 32,
The count value is taken in and the counter 30 is reset. The count value supplied to the CPU 34 is calculated in the CPU 34 as described later.

Next, the operation of this device will be described. Now, as shown by the symbol d in FIG. 4, the analog weighing signal E is stable, the Q output of the JK flip-flop 24 is at the H level,
Output is L level, F / F output of RS flip-flop 22 is L level, ▲ ▼ output is H level, AND gate
It is assumed that the gate open signal to 29 is H level and the output of the comparator 15 is L level. As a result, the analog switches 5, 6, 7, 8 are closed, the switches 10, 11, 12, 13 are opened, and the analog switches 4, 9 are also opened. Therefore,
The output of amplifier 18 is K (E + △ V).

In this state, when the pulse falls, the F / F output of the RS flip-flop 22 becomes H level, and the analog switch 4 is closed. As a result, the integrator 14
Is applied with a voltage of K (E + △ V), and the output of the integrator 14 is
IG rises as shown in FIG. Note that when the pulse falls, the analog switches 5 to 8 have already been turned on, and the transient response delays of the amplifiers 16, 17, and 18 have converged. Therefore, K supplied to the integrator 14
The voltage of (E + △ V) is not affected by the above-mentioned transient response delay. ▲ ▼ Comparator from when the pulse falls
The output C of the 15 becomes H level. When T1 time elapses after the ▲ ▼ pulse falls, the ▲ ▼ pulse falls and F /
The F output goes low, and the ▼ output goes high. As a result, the output ▲ ▼ of the AND gate 26
・ C becomes H level, and the analog switch 9 is turned on. As a result, −eR is supplied to the integrator 14 and the integrator 14
The output IG of 14 starts falling. Further, since ▲ and C are also supplied to the AND gate 28, the clock pulse CL is supplied to the counter 30 via the AND gate 28,
The count starts.

On the other hand, when the F / F output of the RS flip-flop 22 becomes L level, the output of the AND gate 29 falls,
That is, the input of the JK flip-flop 24 falls, the Q output becomes L level, the output becomes H level, the analog switches 5 to 8 are opened, and the analog switches 10 to 13 are closed.

Eventually, when the output of the integrator 14 becomes 0, the output C of the comparator 15 becomes 0, the output of the comparator C becomes L level, the analog switch 9 is opened, and the clock pulse CL
Supply to the counter 30 is stopped. At the same time, CPU 34
Since the output C of the comparator 15 is input through the / O port 32, it is known that the output C has become 0, and the count value C1 of the counter 30 (a digital value of K (E + △ V)) is obtained. And the counter 30 is reset.

When the ▲ ▼ pulse falls again, the digital conversion is performed in the same manner as described above, but when the ▲ ▼ pulse falls first, the analog switches 10 to 13 are closed, and the analog switches 5 to 8 are closed. It is K (E- △ V) that is digitally transformed because it is open. Moreover, since the time T2 has elapsed since the analog switches 10 to 13 were turned on, the delay in the transient response generated in the amplifiers 16, 17, and 18 when the analog switches 10 to 13 were turned on was also affected by this. Sometimes they are converging. Therefore, the output K (E-ΔV) of the amplifiers 16, 17, 18 is not affected by the delay of the transient response. This digital conversion signal, that is, the count value C2 of the counter 30 is taken into the CPU.

The CPU 34 subtracts C2 from the acquired count value C1 and divides this subtraction value by two. The division value C3 is obtained by digitizing the offset voltage ΔV as described above.
Then, the CPU 34 subtracts the division value C3 from the count value C1 to obtain a digital value DKE of only the analog signal E in the stationary state. And CPU34 is AND gate 29
The gate open signal being supplied to is set to L level. Thus, even if the F / F output of the RS flip-flop 22 falls thereafter, the Q output and output of the JK flip-flop 24 are not inverted, and the analog switches 5 to 8 are closed. In addition, the state where 10 to 13 are opened is maintained.

Then, as described with reference to FIG. 3, the supply of the granular material to the weighing hopper 44 is started, and when the ▲ ▼ pulse falls, the analog weighing signal E1 and the offset voltage ΔV at that time are amplified. K (E ₁ + ΔV) is analog switch 4
Is supplied to the integrator 14 via the. When the pulse falls, the analog switch 4 is opened and the switch 9 is closed. Then, the counter 30 starts counting the clock pulse CL, and when the output C of the comparator 15 becomes 0, the counting is stopped. Count value C4 at this time
Is a digital version of E ₁ + ΔV, which is taken into the CPU 34. CPU34 subtracts the C3 from C4, to obtain a digital signal DKE1 that digitizing only E _1. Then, the control of the motor 48 is performed by comparing this signal with the SW as described above. Next, the ▲ ▼ pulse falls, followed by ▲ ▼
There the falls, in the same manner, to obtain those digital converts the new analog weighing signal E ₂ and the offset voltage △ V, by subtracting the same manner now C3, analog weight signal E ₂
A signal DKE ₃ obtained by digitizing is obtained. Thereafter, the same operation is performed, and when the supply to the weighing hopper 44 is stopped and the analog weighing signal is stabilized, a signal obtained by digitizing the offset voltage is obtained in the same manner as described above, and used for subsequent weighing.

In the above-described embodiment, the digital value of the offset voltage is set every time the granular material is supplied to the weighing hopper 44 by a constant weight.
C3 is determined and used to compensate for the offset voltage during the next fill. However, the value of the offset voltage itself is about 1 mV, and the offset voltage fluctuates (drifts) between the completion of filling of the weighing hopper 44 with a constant weight and the completion of the next filling of a constant weight. 0.5
It is about μV to 1 μV. By the way, even when the filling is completed, the output of the amplifier 18 may fluctuate more than the fluctuation of the offset voltage due to the influence of the vibration of the foundation supporting the weighing hopper 44 or the wind. Therefore, if C3 obtained on the basis of the output of the amplifier 18 fluctuating beyond the offset voltage is directly treated as the digital value of the offset voltage, the error may be rather increased.

Therefore, in the second embodiment, the CPU 34 determines whether the value obtained by subtracting C1 from C3 or C2 is larger than the value obtained by subtracting C1 from the previous C3 or C2. The subtracted value is increased by a value predicted as a fluctuation value of the offset voltage, and when it is smaller, the value is reduced by a value predicted as a fluctuation value of the offset voltage. For example, when the resolution is set so that one count value of the counter 30 corresponds to 0.5 μV, when the offset voltage drift is about 0.5 μV to 1 μV as described above, the previous offset is used. Digital value of voltage is 1
Just increase or decrease. When this device is operated, the approximate value of the offset voltage, the digital value (200) of 1 mV in the above example, is set by the DK in the initial setting in the CPU 34.
When the first filling is completed, C3 is obtained as described above, and DK △ V is increased or decreased by 1 depending on whether C3 is larger or smaller than DK △ V, and when the next filling is completed. , C3, and then increases or decreases DK △ V by 1 depending on whether it is larger or smaller than DK △ V at that time. Hereinafter, the same operation is performed.

A third embodiment is shown in FIG. 5 and FIG. In this embodiment, as shown in FIG. 6, a successive approximation type A / D converter is used, and the output of the inverting amplifier 18 is directly input to the A / D converter 60. ing. That is, the analog switches 4 and 9 provided in the first embodiment are removed. The analog switches 5 to 8 are closed when the analog switch signal supplied from the CPU 34 via the I / O port 32 is at the H level, and the analog switches 10 to 13 are closed.
Is closed when the analog switch signal inverted by the inverter 62 is at H level. When the predetermined weight of the granular material is filled in the weighing hopper 44 as shown in the first half of FIG. 5 (b), the analog switch signal becomes L level after reaching the H level, The H level is maintained during filling as shown in FIG. Therefore, as shown in FIGS. 5 (b) and 5 (c), when the filling of the weighing hopper 44 with the predetermined weight of the article is completed, the analog switches 5-8,
10 to 13 are closed to each other, and analog switch 5 during filling
8 holds the closed state. Further, the CPU 34 gives an A / D conversion command signal to the A / D converter 60 to
8 is converted into a digital signal. When the A / D conversion command signal has been completely filled as shown in the first half of FIG. Occurs when time elapses and when a certain time elapses after the analog switches 10 to 13 are closed, and occurs at appropriate intervals during filling. Therefore, when the filling is completed, the digital signal DK (E + ΔV) and
DK (E- △ V) is obtained and the digital signal DK
(En + ΔV) is obtained. Here, E is the value of the analog weighing signal during filling, En is the value of the analog weighing signal during filling, and ΔV is the offset voltage. And these DK
Using (E + ΔV), DK (E−ΔV) and DK (En + ΔV), compensation of the offset voltage is performed in the same manner as in the first or second embodiment.

FIG. 7 shows a fourth embodiment. This embodiment uses an amplifier
Amplifiers 64 and 66 are connected to the outputs of 16 and 17 so that they have opposite polarities, an analog switch 68 is connected between the amplifier 64 and the A / D converter 60, and the amplifier 66 and the A / D converter 60 are connected to each other. An analog switch 70 is provided between the analog switches 5,
When the switch 6 is closed, the analog switch 68 is closed and A /
K (E + ΔV) is supplied to the D converter 60, and when the analog switches 10 and 11 are closed, the analog switch 70 is closed, and K (E−ΔV) is supplied to the A / D converter 60. Supply. The switching timing of these analog switches is the same as in the third embodiment, and the offset voltage can be compensated in the same manner as in the third embodiment.

In each of the above embodiments, the present invention is applied to the fixed-quantity filling device, but the present invention can be applied to other devices such as a weight sorter. In this case, the digital value of the offset voltage is
When there is no article on the weighing conveyor of the weight sorter, for example, the test piece is transported on the weighing conveyor, and the test piece is obtained in the same manner as in each of the above embodiments.

Further, in each of the above embodiments, the A / D converter is of a double integration type and of a successive approximation type. However, other types, for example, a charge balance type and a tracking comparison type are used. Those and the like can also be used. In the first embodiment, the analog switch is controlled by both the logic circuit and the CPU 34. However, the analog switch may be controlled only by the logic circuit or only by the CPU 34.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of an analog-to-digital converter according to the present invention, FIG. 2 is a waveform diagram of each part of the first embodiment, and FIG. 3 is a diagram of the first embodiment. FIG. 4 is a waveform diagram of the weighing device of the device of FIG. 3, FIG. 5 is a waveform diagram of each part of the third embodiment, and FIG. 6 is a block diagram of the third embodiment. FIG. 7 is a block diagram of the fourth embodiment, FIG. 8 is a block diagram of a conventional analog / digital converter, and FIG. 9 is a waveform diagram of the analog / digital converter of FIG. 5-13: Switching means, 16, 17, 18 ... Amplifying means, 14, 1
5, 30 conversion means, 22, 24, 26, 28, 29 control means 34 first and second calculation means.

Claims (2)

(57) [Claims] Amplifying means for amplifying an analog signal; a first output obtained by adding an output of the amplifying means to the analog signal by adding an offset amount in a positive direction; A switching means provided in the amplifying means so as to switch to a second output amplified in a negative direction; a converting means for receiving an output of the amplifying means and converting the output into a digital signal; An offset amount digital signal corresponding to the offset amount is calculated based on a difference between the first and second reference digital signals obtained by converting the first and second outputs based on the supplied reference analog signal, respectively. A first calculating means, and one of first and second outputs based on a measured analog signal different from the reference analog signal is converted by the converting means Second arithmetic means for adding or subtracting the digital signal obtained and the offset digital signal to calculate a digital signal corresponding to the measured analog signal, and calculating the offset digital signal by the first arithmetic means At this time, control means for selectively supplying the first and second outputs to the conversion means, and for causing the conversion means to perform the conversion after a predetermined time has elapsed after the selective supply is performed, An analog-to-digital conversion device comprising: 2. Amplifying means for amplifying an analog signal, an output of the amplifying means, a first output amplified by adding an offset amount to the analog signal in a positive direction, and an offset amount added to the analog signal. A switching means provided in the amplifying means so as to switch to a second output amplified in a negative direction; a converting means for receiving an output of the amplifying means and converting the output into a digital signal; An offset amount digital signal corresponding to the offset amount is calculated based on a difference between the first and second reference digital signals obtained by converting the first and second outputs based on the supplied reference analog signal, respectively. Calculating means for determining whether or not the last offset amount digital signal is larger or smaller according to the magnitude of the offset amount digital signal and the previous offset amount digital signal. Means for adding or subtracting a predetermined drift-equivalent digital signal to or from the ground signal to calculate a drift-compensated offset digital signal; and first and second outputs based on a measured analog signal different from the reference signal analog signal Means for calculating a digital signal corresponding to the measured analog signal by adding or subtracting a digital signal obtained by converting one of the signals by the conversion means and the drift compensation offset amount digital signal; When the offset amount digital signal is calculated by the calculating means, the first and second outputs are selectively supplied to the converting means, and after a predetermined time has elapsed after the selective supply, the converting means And a control means for performing the above-mentioned conversions respectively. .