JP2570485B2 - Signal interpolation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a signal interpolation circuit, and particularly for a signal including pulse-like noise or noise due to a short-time lack of a signal, interpolates a portion corresponding to the noise generation period with another signal. The present invention relates to improvement of a signal interpolation circuit.

[Prior art]

In video tape recorders and the like, audio signals are frequency-modulated and recorded on a deep part of a magnetic medium, and then a video signal is recorded on the surface layer of the medium. And frequency-multiplexed recording. In such a helical scan video tape recorder in which sound is recorded by FM, switching noise generated when switching the head reproduction output signal in synchronization with the rotation of the rotating head during reproduction (in the following description, the lack of reproduction signal An appropriate signal interpolation circuit is used for the purpose of reducing the noise caused by the signal interpolation. FIG. 4 shows an example of such a signal interpolation circuit. This conventional example is disclosed in Japanese Patent Publication No. 1-24433. FIG. 5 shows waveforms of main parts in the apparatus of FIG. In these figures, an input terminal 10 receives, for example, a signal a (see FIG. 5 (A)) on which a switching noise 30 is superimposed. This signal a is amplified by the input amplifier 12 having a low output impedance, and thereafter, is switched.
Supplied to A switching signal b (see FIG. 1B) generated by a known method is also supplied to the switch circuit 14 through an input terminal 16. Switching signal b
Is a signal generated by detecting these signals at the time of switching the reproduction signal of the rotary magnetic head or at the time of lack of the reproduction signal. During the period in which the switching noise 30 does not occur, the switching signal b has the logical value “H”. Therefore, the switch circuit 14 is closed, and the output of the input amplifier 12 passes through the switch circuit 14 as it is. The passed signal charges and discharges the hold capacitor 18 on the one hand, and an output amplifier with high input impedance on the other hand.
Output from 20. On the other hand, during the period in which the switching noise 30 occurs, the switching signal b has the logical value “L”, and the switching circuit 14
Is opened. Therefore, the voltage value held in the hold capacitor 18 immediately before the input of the switching noise 30 is output from the output amplifier 20. The output signal c of the output amplifier 20 (see FIG. 3C) is output from the output terminal 22 on one side, and is supplied to the slope prediction circuit 24 on the other side. The slope prediction circuit 24 generates and outputs a slope prediction voltage d (see FIG. 3D) in which the slope of the input signal c is predicted by differentiating the signal. The slope prediction voltage d is delayed by the minute time τ by the delay circuit 26 and supplied to the voltage-current conversion circuit 28. In the voltage-current conversion circuit 28, the slope predicted voltage d after the delay is converted into the corresponding current e (see FIG. 9E). The converted current signal e is supplied to a hold capacitor 18 in order to correct a signal during a hold period (a period during which noise is generated). In this case, when the switch circuit 14 is closed, the impedance of the switch circuit 14 and the output impedance of the input amplifier 12 are sufficiently low, so that the current e flows through them and flows into the hold capacitor 18. There is no. However, during the hold period when the switch circuit 14 is in the open state, the impedance of the switch circuit 14 becomes sufficiently high together with the input impedance of the output amplifier 20. Therefore, the current e flows into the hold capacitor 18. That is, immediately after the start of the hold period, a current based on the slope prediction voltage d predicted from the input signal a at the time before (past) by the delay time τ flows into the hold capacitor 18. Accordingly, the current f flowing through the hold capacitor 18 is as shown in FIG. 5 (F) as a whole. In the example shown in the figure, since the slope of the input signal a immediately before the input of the switching noise 30 is negative, the current f is also negative. This causes the hold capacitor 18 to discharge. Therefore, when the current f does not flow, the hold voltage held at a constant potential changes at a slope predicted from the input signal a immediately before the input of the switching noise 30, whereby the signal is interpolated. Becomes This change in the hold voltage is supplied again from the output amplifier 20 to the gradient prediction circuit 24, and the gradient is predicted. However, since the change in the differential value immediately after the start of the hold period is small, the slope prediction voltage d output from the slope prediction circuit 24 has substantially the same value (see 32 in FIG. 3D). The predicted slope voltage d again supplies the current f to the hold capacitor 18 via the delay circuit 26 and the voltage-current conversion circuit 28. Therefore, the interpolation with the gradient predicted from the input signal a immediately before the input of the switching noise 30 is continued. Hereinafter, the same operation is repeated, and the predicted slope information goes through a loop of hold capacitor 18 → output amplifier 20 → slope prediction circuit 24 → delay circuit 26 → voltage-current conversion circuit 28 → hold capacitor 18. During the noise interpolation period (hold period T), the slope is almost the same (34 in FIG.
), The signal is interpolated. As a result, output terminal 22
Has a waveform similar to a waveform obtained by removing the switching noise 30 from the input signal a. Next, another conventional example is shown in FIG. FIG. 8 shows a signal waveform of a main part of this example. In these figures, switching noise 30
Is superimposed on the input terminal (see FIG. 8 (A)).
It is assumed that the signal is input to the sample-and-hold circuit 38 via the signal 36. The switching signal m (see (E) in the figure), which has the logical value “H” during a certain period including the period during which the switching noise 30 is generated, is supplied from the timing generator 40 to the sample-and-hold circuit 38. Outside the fixed period, the switching signal m has the logical value “L”. Therefore, the signal k is output as it is while being sampled. On the other hand, switching noise
During a certain period including the 30 occurrence period, the switching signal m
Becomes the logical value “H”. For this reason, the signal voltage sampled immediately before the input of the switching noise 30 is held and output during the hold period T. The output signal n of such a sample and hold circuit 38
The input signal k is input to the inverting input terminal and the non-inverting input terminal of the differential amplifier 42, respectively, where the error detection is performed. The detected error signal is supplied to the sample and hold circuit 44. The switching signal o (see (F) in the same figure), which has the logical value “H” of the period T / 2 immediately before the end of the hold period T, is supplied from the timing generator 40 to the sample-hold circuit 44. . For this reason, while the switching signal o has the logical value “L”, the sampling of the error signal is performed. However, when the switching signal o becomes the logical value “H”, the error signal voltage sampled immediately before the end of the hold period T is held and output for T / 2. As a result, the error t between the output signal n and the input signal k of the sample / hold circuit 38 immediately before the end of the hold period T (see FIG. 7B), that is, the amount of change in the signal voltage during the noise interpolation period is extracted. The output of the sample and hold circuit 44 is supplied to a pulse generator (PG) 46. The pulse generator 46 outputs a "0" V potential when the switching signal o input from the timing generator 40 has a logical value "L", and samples and holds only while the logical value is "H". The voltage from the circuit 44 is output as it is. Accordingly, a correction pulse i having a width T / 2 and a height t ((C) in FIG.
Is generated and output by the pulse generator 46. This correction pulse i is added to the output signal n of the sample-and-hold circuit 38 by the adder 48 and the correction is performed.
The signal is output from the output terminal 50 as an output signal j (see FIG. 3D). The signal n has a missing portion α corresponding to the difference between the signal originally required in the hold period T and the hold voltage (see the broken line in FIG. 3B), and the missing portion α is approximated by a triangle. Correction pulse i having the same area β as the area
However, the interpolation of the signal is performed by supplementing during the hold period T / 2. When the output signal j output from the output terminal 50 passes through a low-pass filter (not shown), the lower frequency components are delayed, and the higher frequency components are attenuated. Therefore, the signal j comes closer to the signal waveform that should originally exist, like the signal p shown in FIG. 8 (G).
In addition, since the energy amounts of the portions deviated in the positive direction and the negative direction from the original signal waveform are almost equal to each other and cancelled, the effect of correcting the audibility is enhanced.

[Problems to be solved by the invention]

However, the above conventional techniques have the following disadvantages. First, in the signal interpolation circuit shown in FIG. 4, if the loop gain of the hold capacitor 18 → the output amplifier 20 →... → the current-voltage conversion circuit 28 → the hold capacitor 18 is not appropriate, FIG. As shown by II, signal interpolation is not performed well. Therefore, it is necessary to appropriately adjust the loop gain. However, due to variations in circuit characteristics that occur when the circuit is formed into an IC, the loop gain becomes inappropriate and the interpolation effect also varies. Further, since the slope prediction circuit 24 is constituted by a differentiating circuit, a high-frequency noise component is emphasized, and as a result, there is a disadvantage that excessive interpolation of a signal may be performed. This remarkably occurs particularly in a video tape recorder in which an FM audio signal is recorded. Next, in the signal interpolation circuit of FIG. 7, since the signal interpolation is performed after the hold period T, the waveform reproducibility is not always good. Further, as shown in FIG. 9, when the correction portion cannot be approximated by a triangle, the correction cannot be performed (see FIG. 9A) or the correction cannot be completed (FIG. 9B).
Reference). SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and absorbs variations in correction characteristics due to variations in circuit characteristics, effectively suppresses erroneous interpolation due to noise components, and performs good waveform reproduction without interpolation errors. It is an object of the present invention to provide a signal interpolating circuit capable of performing the above.

[Means for Solving the Problems]

The present invention provides a signal interpolation circuit for performing signal interpolation based on a gradient predicted by a gradient prediction means during a period of occurrence of an instantaneous noise included in an input signal, wherein the input signal and the gradient prediction are performed. Error detection means for obtaining an error from the interpolation signal performed; correction signal generation means for generating a correction signal having an area corresponding to the interpolation error detected thereby; and correcting the area of the interpolation error with the correction signal Correction means; noise level detection means for continuously detecting the level of noise contained in the input signal; comparison means for comparing the detected noise level with a predetermined reference level; Attenuating means for attenuating an interpolation amount of signal interpolation by the inclination predicting means when it is determined that the reference level exceeds the reference level. Is shall.

[Action]

According to the present invention, an error between an input signal and an interpolated signal subjected to slope prediction interpolation during a noise occurrence period is first detected. Next, based on the detection result,
A correction signal having an area corresponding to the degree of the error is generated. Then, the correction signal is used to correct the signal area for the interpolation signal. Further, the level of noise continuously contained in the input signal is detected and compared with a predetermined reference level. As a result, when the noise level exceeds a predetermined reference level, the signal interpolation amount based on the slope prediction is attenuated. This suppresses excessive interpolation when the noise level is high.

【Example】

Hereinafter, an embodiment of a signal interpolation circuit according to the present invention will be described with reference to the accompanying drawings. Note that the same reference numerals are used for components that are the same as or correspond to those of the above-described conventional example. FIG. 1 shows a configuration of a main part of the present embodiment. In this embodiment, as shown in the figure, first and second sample-and-hold circuits are provided. First, the input amplifier 12, the switch circuit 14, the hold capacitor 18, and the output amplifier 20 constitute a first sample / hold circuit 52. Of these, the output sides of the input amplifier 12 and the output amplifier 20 are connected to the non-inverting input side and the inverting input side of the error detection amplifier 42, respectively. The error detection amplifier 42 outputs an interpolation signal c (hereinafter, referred to as an output signal c) from the output amplifier 20.
An error between the "primary interpolation signal") and the input signal a is obtained, and an error signal g is output. Next, a switch circuit is provided on the output side of the error detection amplifier 42.
A second sample-and-hold circuit 58 constituted by 54, a hold capacitor 56, and a pulse generator 46 is connected. The input terminal 16 is connected to the input side of the timing generator 40, and its output side is
The switch circuit 54 and the pulse generator 46 are connected to each other. Thus, the switching signal h generated by the timing generator 40 based on the switching signal b is supplied to the switch circuit 54 and the pulse generator 46, respectively. The switching signal b is a signal generated by detecting these signals by a known means, for example, when switching the reproduction signal of the rotary magnetic head or when the reproduction signal is missing. Next, the switching signal h is applied for a predetermined period, for example, immediately before the end of the hold period T with respect to the hold period T, for example.
The signal becomes a logical value "L" during T / 2 and a logical value "H" in other periods. When the switching signal h is "H", the switch circuit 54 is closed, and the error signal output from the error detection amplifier 42 charges and discharges the hold capacitor 56. When the switching signal h becomes "L", the switch circuit 54 is opened, the error signal voltage output immediately before is held by the hold capacitor 56 for the hold period of T / 2, and output to the pulse generator 46. It is supposed to be. The switching signal h is similarly supplied from the timing generator 40 to the pulse generator 46. The pulse generator 46 outputs a 0V potential while the switching signal h is “H”, and outputs a hold voltage input from the hold capacitor 56 only while the switching signal h is “L”. Each output side of the sample and hold circuits 52 and 58 is connected to an input side of an adder 48 that performs quadratic interpolation of a signal. The output side of the adder 48 is an output terminal
Connected to 50. By the way, for example, a frequency-modulated audio signal reproduced by a magnetic head of a video tape recorder is frequency-demodulated by a demodulation circuit (not shown). In ordinary frequency demodulation, a low-pass filter having a low cutoff frequency that allows only the audio signal band to pass is provided at the subsequent stage of the demodulation circuit, and the demodulated signal passes through this filter. However, in such a circuit, noise such as switching noise is integrated by the low-pass filter, and the noise superimposed period is longer than the actual noise generation period, so that signal interpolation becomes difficult. Therefore, by setting the cutoff frequency of the low-pass filter after the frequency demodulation higher than the frequency band of the audio signal (for example, about several hundred KHz), interpolation is performed in a short period. In the present embodiment, the output signal of the low-pass filter set as described above is supplied to the input terminal 10 as an input signal to the interpolation circuit. Then, as described in the description of the conventional example, the output signal of the interpolation circuit is an output signal that has passed through a low-pass filter that passes almost only the audio signal band. In such a case, if the input signal of the interpolation circuit contains many noise components other than the audio signal band, an erroneous slope prediction may be performed and accurate switching noise interpolation may not be performed. Means for preventing such inconvenience due to continuous noise will be described below. In FIG. 1, a noise level detection circuit 64 constituted by a band-pass filter 60 and a detection circuit 62 is connected to the input terminal 10 described above. As a result, a noise component of a predetermined band not including the audio signal band is extracted from the input signal a, and its DC detection is performed to detect a noise level.
For example, in a helical scan video tape recorder that performs FM audio recording, when switching head removal output signal noise is removed, a noise component level of 50 kHz to 250 kHz is detected. Next, a comparison circuit 66 is connected to the output side of the noise level detection circuit 64, and the detected noise level is compared with a predetermined reference level. As a result, when the noise level exceeds the reference level, a signal having a logical value “H”, for example, and when the noise level is lower than the reference level, a signal having a logical value “L” is output. On the other hand, an attenuation circuit 68 is connected between the output side of the delay circuit 26 and the ground. This attenuation circuit 68
The configuration is such that a capacitor 70 and a switch circuit 72 are connected in series, and the switch circuit 72 is supplied with the comparison output of the comparison circuit 66. The switch circuit 70 is configured to be in an open state when the comparison output has a logical value “L”, and to be in an open state when the logical value is “H”.
As a result, when the noise level included in the input signal a becomes equal to or higher than a certain value, the switch circuit 72 is closed, a part of the output of the delay circuit 26 is grounded, and the loop gain for the slope prediction is attenuated. It has become. The other components are the same as those of the above-described conventional technology. Next, the overall operation of the present embodiment configured as described above will be described with reference to the time chart of FIG. a. When the noise level is low First, the level of the noise continuously or always included in the input signal a, especially its high frequency component is low, the comparison output of the comparison circuit 66 is "L", and the switch circuit 72 is opened. Will be described. As in the case of the above-described prior art, assuming that the switching noise 30 is superimposed on the input signal a (see FIG. 2A), the first sample and hold circuit 52 outputs the signal of FIG. Switching noise in the same operation as the conventional example
The primary interpolation signal c subjected to the slope prediction interpolation during the 30 occurrence period is output (see FIGS. 3B to 3F). here,
At the end of the switching noise generation period (end of the hold period T) due to variations in circuit characteristics, etc.
Suppose that a primary interpolation error indicated by Δt in FIG. The primary interpolation signal c including the primary interpolation error Δt is input to the error detection amplifier 42 together with the input signal a, where the difference between the two is detected. The detected error signal g is input to the switch circuit 54 of the sample and hold circuit 58. Next, in the sample and hold circuit 58, the timing signal h normally supplied from the timing generator 40 is used.
Is a logical value "H", the output signal i of the pulse generator 46 is "0" (see FIG. 1I). But,
Since the switch circuit 54 is closed, the input error signal g is supplied to the hold capacitor 56. However, in a period of T / 2 immediately before the end of the period in which the switching noise 30 is generated, the switching signal h has the logical value “L”. Therefore, the error signal voltage sampled immediately before the end of the period during which the switching noise 30 is generated is held by the hold capacitor 56, and this is
It will be output from the generator 48. The output pulse at this time has a width T / 2 and a height Δt. The correction pulse is supplied to the adder 48 together with the primary interpolation signal c, where they are added to obtain a secondary interpolation signal j (see FIG. 10 (J)). Then, the secondary interpolation signal j is output from the output terminal 50. The above-mentioned primary interpolation signal c has an erroneous interpolation part Δα between the original signal in the hold period T (see the broken line in FIG. 2C). However, in the secondary interpolation signal j, a correction pulse having an area Δβ corresponding to an area obtained by approximating the erroneous interpolation part Δα with a triangle is added. For this reason, if a filter or the like is used, the erroneous interpolation portion Δα included in the primary interpolation signal c can be removed satisfactorily, and better signal interpolation can be achieved as a whole. b. When the Noise Level is High Next, the case where the level of the noise continuously included in the input signal a is high will be described. At this time, the noise level detected by the noise level detection circuit 62 exceeds the reference level, and the switch circuit 70 of the attenuation circuit 66 is closed based on the comparison result of the comparison circuit 66. Therefore, the input of the voltage-current conversion circuit 28 is appropriately attenuated. For this reason, even if the slope prediction circuit 24 has a large amount of high-frequency noise components and outputs an excessive slope prediction signal d, the voltage-current conversion circuit
The input at 28 becomes appropriately small, and no interpolation error due to excessive slope prediction interpolation occurs in the primary interpolation signal c. In other words, the intermediate interpolation between the gradient prediction interpolation and the interpolation based on the previous value hold is performed as the primary interpolation by the attenuation of the loop gain. The relatively small interpolation error caused by the primary interpolation is further reduced by the second sample-and-hold circuit described above.
It is corrected by quadratic interpolation by 58 and adder 48. Therefore, the interpolation error when there is a lot of high-frequency noise is effectively suppressed as a whole. As described above, according to the present embodiment, first, the primary interpolation signal is obtained by the slope prediction interpolation, and the secondary interpolation signal is obtained by performing the correction by adding the pulse of the area approximation by the signal hold. The interpolation error due to the variation in the circuit characteristics generated in the primary interpolation signal by the interpolation is corrected and absorbed by the secondary interpolation, the interpolation error is reduced favorably, and the waveform reproducibility is improved. In addition, since the gain of the slope prediction interpolation loop is attenuated according to the noise level continuously included in the input signal, erroneous interpolation due to excessive slope prediction interpolation is satisfactorily suppressed even when there are many high band noise components. Will be done. The present invention is not limited to the above-described embodiment. For example, if there is an appropriate signal delay without the delay circuit 26, the delay circuit 26 may be omitted. Further, the period during which the logic value of the switching signal h generated by the timing generator 40 is “H” is not limited to 1/2 of the switching noise interpolation period T, but is 1, 1 /
Other values such as 8 may be used. In this case, the error detection amplifier 44
In this case, an amplifier 74 having a gain of 2 times, 4 times or the like may be provided on the output side of the pulse generator 42 as shown in FIG. That is, the area Δα of the erroneous interpolation part of the primary interpolation signal c and the area Δβ of the interpolation pulse may be substantially the same (Δα ≒ Δβ = (T / 2) · Δt). Furthermore, the attenuation circuit 66 may be connected to any of the slope prediction circuits 24 provided that it can attenuate the slope prediction loop gain, such as being provided on the input side or output side of the slope prediction circuit 24.
In addition, various design changes can be made to achieve the same operation.

【The invention's effect】

As described above, according to the signal interpolation circuit of the present invention, the signal area is corrected by the correction signal of the area corresponding to the error of the interpolation signal with respect to the interpolation signal by the slope prediction interpolation. Therefore, even if an interpolation error occurs due to a variation in circuit characteristics in the interpolation signal based on the inclination prediction, the interpolation is effectively performed by the area, and the interpolation error is effectively reduced, and the waveform reproducibility is improved. At the same time, when the level of noise continuously included in the signal increases, the amount of interpolation in the slope prediction interpolation is attenuated, so that the occurrence of erroneous interpolation due to excessive slope prediction is effectively suppressed. There is.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a signal interpolation circuit according to one embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the embodiment, FIG.
FIG. 4 is a configuration diagram of a main part showing a modification of the above embodiment, FIG. 4 is a configuration diagram showing an example of a conventional signal interpolation circuit, and FIGS. 5 and 6 show operations of the conventional example of FIG. FIG. 7 is a configuration diagram showing another conventional example, FIG. 8 is a waveform diagram showing the operation of the conventional example of FIG. 7, and FIG. 9 is an explanatory diagram showing inconvenience in the conventional example of FIG. is there. 18, 56… hold capacitor, 24… slope prediction circuit, 26… delay circuit, 28… voltage-current conversion circuit, 40…
… Timing generator, 42… Error detection amplifier,
48 ... adder, 52 ... first sample and hold circuit,
58: second sample and hold circuit, 64: noise level detection circuit, 66: comparison circuit, 68: attenuation circuit.

Claims (1)

(57) [Claims] 1. A signal interpolation circuit for performing signal interpolation based on a gradient predicted by a gradient predicting means during a period of occurrence of an instantaneous noise included in an input signal. Error detection means for obtaining an error from the interpolation signal subjected to the correction, correction signal generation means for generating a correction signal having an area corresponding to the interpolation error detected thereby, and correcting the area of the interpolation error with the correction signal A noise level detecting means for continuously detecting a level of noise continuously included in the input signal; a comparing means for comparing the noise level detected thereby with a predetermined reference level; Attenuating means for attenuating the amount of signal interpolation by the inclination predicting means when it is determined that the predetermined reference level has been exceeded. A signal interpolation circuit characterized by the following.