JP2570264B2 - Solid-state imaging device - Google Patents
Solid-state imaging deviceInfo
- Publication number
- JP2570264B2 JP2570264B2 JP61169482A JP16948286A JP2570264B2 JP 2570264 B2 JP2570264 B2 JP 2570264B2 JP 61169482 A JP61169482 A JP 61169482A JP 16948286 A JP16948286 A JP 16948286A JP 2570264 B2 JP2570264 B2 JP 2570264B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- imaging device
- solid
- film
- state imaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003384 imaging method Methods 0.000 title claims description 57
- 230000002093 peripheral effect Effects 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- 239000005360 phosphosilicate glass Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000002161 passivation Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02162—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors
- H01L31/02164—Coatings for devices characterised by at least one potential jump barrier or surface barrier for filtering or shielding light, e.g. multicolour filters for photodetectors for shielding light, e.g. light blocking layers, cold shields for infrared detectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】 A.産業上の利用分野 本発明はビデオカメラ等に用いられる固体撮像装置に
関する。The present invention relates to a solid-state imaging device used for a video camera or the like.
B.発明の概要 本発明は撮像領域と周辺回路領域を有する固体撮像装
置において、上記撮像領域上の平坦化膜の膜厚を上記周
辺回路領域上の平坦化膜の膜厚よりも薄く（ゼロも含
む）したことにより、配線抵抗の低域，配線切れの防止
を図ることができ、かつスミアの低減を図ることができ
るようにしたものである。B. Summary of the Invention The present invention relates to a solid-state imaging device having an imaging region and a peripheral circuit region, wherein the thickness of the planarization film on the imaging region is smaller than the thickness of the planarization film on the peripheral circuit region (zero). ), It is possible to prevent a low range of the wiring resistance, prevent the disconnection of the wiring, and reduce the smear.
C.従来の技術 従来より、ビデオカメラ等に用いられる固体撮像装置
が知られている。一例を第４図を参照しながら説明す
る。シリコン基板101には撮像領域102aと周辺回路領域1
02bが設けられている。撮像領域102a上には絶縁膜103を
介して配線用のポリシリコン層104aが形成されており、
更に、平坦化膜105を介して遮光用のAl層106aが形成さ
れている。また、周辺回路領域102b上には絶縁膜103を
介して配線用のポリシリコン層104bが形成されており、
更に、平坦化膜105を介して配線用のAl層106bが形成さ
れている。C. Prior Art Conventionally, a solid-state imaging device used for a video camera or the like has been known. An example will be described with reference to FIG. The silicon substrate 101 has an imaging area 102a and a peripheral circuit area 1
02b is provided. On the imaging region 102a, a polysilicon layer 104a for wiring is formed via an insulating film 103,
Further, a light-shielding Al layer 106a is formed via a flattening film 105. A polysilicon layer 104b for wiring is formed on the peripheral circuit region 102b with an insulating film 103 interposed therebetween.
Further, an Al layer 106b for wiring is formed via the flattening film 105.
第５図に周辺回路領域102b側の構造を拡大して示す。
図示のように、配線用のポリシリコン層104bにより基板
101上には凹凸が生じている。配線用のAl層106bは一般
に蒸着によって形成されるが、下地に凹凸が有ると、そ
の段差部分にてAlが蒸着され難く、配線抵抗の増大、ま
た配線切れ等が生じる。平坦化膜105は、これを防ぐた
めに、ポリシリコン膜104bとAl層106bの間に設けられて
いる。この平坦化膜105には、一般にPSG（リンシリケー
トガラス）等が用いられており、例えばCVD法（化学的
気相成長法）による堆積の後、熱処理でのリフローによ
り平坦化が施される。平坦化膜105が薄いと、下層のポ
リシリコン層104bによる凹凸の影響を受け易く、段差部
107にて上層のAl層106bのカバレージが悪くなり、配線
抵抗が増加したり、配線切れ等の虞れがある。このた
め、周辺回路領域102bにとっては、平坦化膜105は薄い
方が望ましい。FIG. 5 shows an enlarged view of the structure on the peripheral circuit region 102b side.
As shown in the figure, the polysilicon layer 104b for wiring
There are irregularities on 101. The wiring Al layer 106b is generally formed by vapor deposition. However, if the underlying layer has irregularities, it is difficult for Al to be vapor-deposited at the step, which increases the wiring resistance and cuts the wiring. The planarizing film 105 is provided between the polysilicon film 104b and the Al layer 106b to prevent this. The flattening film 105 is generally made of PSG (phosphosilicate glass) or the like. For example, after deposition by a CVD method (chemical vapor deposition), flattening is performed by reflow in a heat treatment. If the flattening film 105 is thin, it is easily affected by the unevenness due to the underlying polysilicon layer 104b, and
At 107, the coverage of the upper Al layer 106b is deteriorated, and there is a possibility that the wiring resistance increases, the wiring is cut off, or the like. Therefore, for the peripheral circuit region 102b, it is desirable that the planarization film 105 be thin.
また、第６図に撮像領域102a側の構造を拡大して示
す。シリコン基板101には、CCDレジスタ部108,光電変換
ダイオード部109,チャンネルストップ部110等が形成さ
れており、撮像領域102aが構成されている。ポリシリコ
ン層104aは電荷転送用のゲート電極となっており、平坦
化膜105を介して遮光用のAl層106aが設けられている。C
CDレジスタ部108に光が入射すると、転送中の電荷に該
入射光により光電変換された電荷が加わりスミアが発生
し画質の劣化を生じる。上記Al層106aは、このCCDレジ
スタ部108への光の入射を防止するために設けられてい
るものである。しかし、平坦化膜105が厚いと、撮像装
置表面の凹部での屈折による入射IA,斜め入射IB,多重反
射入射IC等により、CCDレジスタ部108に光が入射しスミ
アが増加してしまう。このため、撮像領域102aにとって
は、平坦化膜105は薄い方が望ましい。FIG. 6 shows an enlarged view of the structure on the imaging region 102a side. On the silicon substrate 101, a CCD register unit 108, a photoelectric conversion diode unit 109, a channel stop unit 110, and the like are formed, and an imaging area 102a is formed. The polysilicon layer 104a serves as a gate electrode for charge transfer, and a light-shielding Al layer 106a is provided via a flattening film 105. C
When light is incident on the CD register unit 108, the electric charge that is photoelectrically converted by the incident light is added to the electric charge being transferred, causing smear and deteriorating the image quality. The Al layer 106a is provided to prevent light from entering the CCD register unit 108. However, when the flattening film 105 is thick, light is incident on the CCD register unit 108 due to incidence I A due to refraction at the concave portion of the imaging device surface, oblique incidence I B , multiple reflection incidence I C and the like, and smear increases. I will. For this reason, it is desirable for the imaging region 102a that the flattening film 105 be thin.
D.発明が解決しようとする問題点 ところが、従来の撮像装置では、平坦化膜105の膜厚
が一定であり、配線抵抗の低減，配線切れの防止とスミ
アの低減を両立させることは困難であった。D. Problems to be Solved by the Invention However, in the conventional imaging device, the thickness of the flattening film 105 is constant, and it is difficult to achieve both reduction of wiring resistance, prevention of disconnection of wiring, and reduction of smear. there were.
そこで、本発明は上述した従来の問題点に鑑みて提案
されたものであり、配線抵抗の低減，配線切れの防止を
図ることができ、かつスミアの低減を図ることができる
ような固体撮像装置を提供することを目的とする。In view of the above, the present invention has been proposed in view of the above-described conventional problems, and is a solid-state imaging device capable of reducing wiring resistance, preventing disconnection of wiring, and reducing smear. The purpose is to provide.
E.問題点を解決するための手段 本発明に係る固体撮像装置は、上述した目的を達成す
るために、撮像領域と周辺回路領域を有する固体撮像装
置において、上記周辺回路領域上及び上記撮像領域上に
それぞれ第１配線層が形成され、上記周辺回路領域上に
形成された上記第１の配線層上には、平坦化膜を介して
第２の配線層が形成され、上記撮像領域上に形成された
上記第１の配線層上には、上記周辺回路領域上に形成さ
れた平坦化膜より薄い平坦化膜を介して遮光層が選択的
に形成したものである。E. Means for Solving the Problems The solid-state imaging device according to the present invention is a solid-state imaging device having an imaging region and a peripheral circuit region in order to achieve the above-described object. A first wiring layer is formed on the first wiring layer, and a second wiring layer is formed on the first wiring layer formed on the peripheral circuit region via a flattening film. A light shielding layer is selectively formed on the formed first wiring layer via a flattening film thinner than a flattening film formed on the peripheral circuit region.
F.作用 本発明によれば、周辺回路領域上においては、第１配
線層による段差部での第２配線層のカバレージが良好と
なり、撮像領域上においては、スミアの原因となる不要
な光の入射が防止される。F. Function According to the present invention, the coverage of the second wiring layer at the stepped portion of the first wiring layer is improved on the peripheral circuit region, and unnecessary light causing smear is generated on the imaging region. The incidence is prevented.
G.実施例 以下、本発明の実施例について図面を参照しながら詳
細に説明する。G. Examples Hereinafter, examples of the present invention will be described in detail with reference to the drawings.
第１図に一実施例の固体撮像装置を示す。この第１図
において、シリコン基板１には撮像領域2aと周辺回路領
域2bが設けられている。上記撮像領域2aにおいて、シリ
コン基板１には、図示を省略するが、前述したようなCC
Dレジスタ部，光電変換ダイオード部，チャンネルスト
ップ部等が形成されている（第６図参照）。この撮像領
域2a上には、絶縁膜３を介して第１配線層であるポリシ
リコン層4aが形成されており、更に、該ポリシリコン層
4a上の絶縁膜3aを介して遮光層であるAl層6aが形成され
ている。一方、上記周辺回路領域2b上には絶縁膜３を介
して第１配線層であるポリシリコン層4bが形成されてお
り、更に、該ポリシリコン層4b上の絶縁膜3bおよび平坦
化膜5bを介して第２配線層であるAl層6bが形成されてい
る。FIG. 1 shows a solid-state imaging device according to one embodiment. In FIG. 1, a silicon substrate 1 is provided with an imaging area 2a and a peripheral circuit area 2b. In the imaging region 2a, although not shown, the silicon substrate 1 has the CC as described above.
A D register section, a photoelectric conversion diode section, a channel stop section, and the like are formed (see FIG. 6). On this imaging region 2a, a polysilicon layer 4a, which is a first wiring layer, is formed with an insulating film 3 interposed therebetween.
An Al layer 6a, which is a light shielding layer, is formed via an insulating film 3a on 4a. On the other hand, a polysilicon layer 4b as a first wiring layer is formed on the peripheral circuit region 2b with an insulating film 3 interposed therebetween, and the insulating film 3b and the planarizing film 5b on the polysilicon layer 4b are further formed. An Al layer 6b, which is a second wiring layer, is formed therethrough.
このような固体撮像装置の製造方法について概略的に
説明する。まず、第２図（Ａ）に示すように、シリコン
基板１上に例えばSiO2からなる絶縁膜３をLOCOS法（局
所酸化法）あるいはCVD法等により形成した後、該絶縁
膜３上に配線用のポリシリコン層4a,4bを形成する。次
に、熱酸化あるいはCVD法等によりポリシリコン層4a,4b
の表面に絶縁膜3a,3bを形成する。次に、ポリシリコン
層4bによる凹凸を充分少なくするのに必要な膜厚の平坦
化膜となるPSG膜５をCVD法等により形成する。この平坦
化膜の材料としては、上記PSGの他に、AsSG（ヒ素シリ
ケートガラス）,BPSG（ボロンリンシリケートガラス）
等を用いることができる。次に、フォトリソグラフィ技
術により周辺回路領域2b上のみレジスト７を残し、これ
をマスク（保護膜）としてPSG膜５の撮像領域2a上の部
分をエッチング液にてエッチングする。A method for manufacturing such a solid-state imaging device will be schematically described. First, as shown in FIG. 2A, an insulating film 3 made of, for example, SiO 2 is formed on a silicon substrate 1 by a LOCOS method (local oxidation method) or a CVD method, and then a wiring is formed on the insulating film 3. Forming polysilicon layers 4a and 4b. Next, the polysilicon layers 4a and 4b are formed by thermal oxidation or CVD.
The insulating films 3a and 3b are formed on the surface of the substrate. Next, a PSG film 5 serving as a flattening film having a film thickness necessary for sufficiently reducing unevenness due to the polysilicon layer 4b is formed by a CVD method or the like. As a material for the flattening film, in addition to the above PSG, AsSG (arsenic silicate glass), BPSG (boron phosphorus silicate glass)
Etc. can be used. Next, the resist 7 is left only on the peripheral circuit region 2b by a photolithography technique, and the portion of the PSG film 5 on the imaging region 2a is etched with an etchant using the resist 7 as a mask (protective film).
次に、レジスト７を除去し、熱処理でのリフローを施
すことにより、第２図（Ｂ）に示すような平坦化された
PSG膜からなる平坦化膜5bを周辺回路領域2b上に得るこ
とができる。Next, by removing the resist 7 and performing reflow by heat treatment, it was flattened as shown in FIG.
A planarizing film 5b made of a PSG film can be obtained on the peripheral circuit region 2b.
そして、再び第１図に示すように、遮光用のAl層6aお
よび配線用のAl層6bを蒸着により形成し、固体撮像装置
が完成される。Then, as shown in FIG. 1 again, the Al layer 6a for shielding and the Al layer 6b for wiring are formed by vapor deposition, and the solid-state imaging device is completed.
このような固体撮像装置によれば、ポリシリコン層4b
による凹凸を充分少なくするのに必要な膜厚の平坦化膜
5bが周辺回路領域2b上に形成されているため、上層のAl
層6bのカバレージは良好であり、配線抵抗の低減，配線
切れの防止を図ることができる。また、撮像領域2a上に
は平坦化膜を設けないようにしているため、不要な光の
入射が防止され、スミアの低減を図ることもできる。According to such a solid-state imaging device, the polysilicon layer 4b
Film with a thickness necessary to sufficiently reduce unevenness due to
5b is formed on the peripheral circuit region 2b, so that the upper layer Al
The coverage of the layer 6b is good, and it is possible to reduce wiring resistance and prevent disconnection of wiring. In addition, since no flattening film is provided on the imaging region 2a, unnecessary light is prevented from entering, and smear can be reduced.
ここで、この第１図の例においては、撮像領域2a上の
平坦化膜の膜厚をゼロ、すなわち平坦化膜を設けないよ
うにしていたが、周辺回路領域2b上の平坦化膜5bより薄
い平坦化膜を設けるようにしても良い。Here, in the example of FIG. 1, the thickness of the flattening film on the imaging region 2a is zero, that is, no flattening film is provided. A thin flattening film may be provided.
すなわち、撮像領域2a上のAl層6aは遮光用であるた
め、カバレージはある程度悪くても良いが、ポリシリコ
ン層4aによる段差部でAlが切れてしまうと、その部分か
ら光が入射しスミアの原因となることがある。そこで、
撮像領域2a上においてもAl層6aの上記段差部でのカバレ
ージをある程度良くするために、薄く平坦化膜を形成す
ることが望ましい。また、PSGによりバッシベーション
効果も得られるため、撮像領域2a上においてもある程度
の膜厚のPSG膜（平坦化膜）が必要な場合もある。これ
らの改善を図るべく、第３図に示すような構造の固体撮
像装置を本発明の他の実施例として挙げることができ
る。That is, since the Al layer 6a on the imaging region 2a is used for shielding light, the coverage may be poor to some extent. However, if Al is cut off at a step portion due to the polysilicon layer 4a, light enters from the portion and smear is generated. May cause. Therefore,
It is desirable to form a thin flattening film on the imaging region 2a in order to improve the coverage of the Al layer 6a at the step portion to some extent. Further, since a passivation effect can be obtained by PSG, a PSG film (flattening film) having a certain thickness may be required even on the imaging region 2a. In order to achieve these improvements, a solid-state imaging device having a structure as shown in FIG. 3 can be cited as another embodiment of the present invention.
第３図において、撮像領域2a上にはAlのカバレージ改
善およびバッシベーション効果に必要な膜厚のPSGから
なる平坦化膜８が形成されており、周辺回路領域2b上に
は平坦化膜5bの上層に上記平坦化膜８が形成されてい
る。撮像領域2a上の平坦化膜８の膜厚は、図示からも明
らかなように、周辺回路領域2b上の平坦化膜5bおよび平
坦化膜８の膜厚よりも薄くなっている。In FIG. 3, a flattening film 8 made of PSG having a film thickness necessary for improving the coverage of Al and a passivation effect is formed on the imaging region 2a, and a flattening film 5b is formed on the peripheral circuit region 2b. The flattening film 8 is formed as an upper layer. As is clear from the drawing, the thickness of the flattening film 8 on the imaging region 2a is smaller than the thicknesses of the flattening film 5b and the flattening film 8 on the peripheral circuit region 2b.
この固体撮像装置は、先に第２図（Ａ）を参照しなが
ら説明した製造工程において、PSG膜５を周辺回路領域2
b上のみに残した後の工程を次のように変更することに
より完成される。すなわち、PSG膜５を周辺回路領域2b
上のみに残した後、更に、撮像領域2a上でのAlのカバレ
ージ改善およびバッシベーション効果に必要な膜厚のPS
G膜をCVD法等により形成し、この後に熱処理によるリフ
ローを施し平坦化を行うことにより上記平坦化膜5b,8が
得られる。そして、遮光用のAl層6aおよび配線用のAl層
6bを形成し、第３図のような固体撮像装置が完成され
る。In the solid-state imaging device, in the manufacturing process described above with reference to FIG.
It is completed by changing the process after leaving only on b as follows. That is, the PSG film 5 is transferred to the peripheral circuit region 2b.
After being left only on the upper side, the PS of the film thickness necessary for improving the coverage of Al on the imaging region 2a and for the passivation effect is further provided.
The G film is formed by a CVD method or the like, and thereafter, the reflow by heat treatment is performed to perform flattening, whereby the flattened films 5b and 8 are obtained. Then, the light shielding Al layer 6a and the wiring Al layer
6b is formed, and the solid-state imaging device as shown in FIG. 3 is completed.
このような固体撮像装置によれば、前述した第１図の
固体撮像装置と同様の効果が得られるばかりでなく、ポ
リシリコン層4aによる段差部でAl層6aのカバレージが良
好となりスミアの原因となるAlの切れが排除できると共
に、バッシベーション効果も得られる。According to such a solid-state imaging device, not only effects similar to those of the solid-state imaging device shown in FIG. 1 described above can be obtained, but also the coverage of the Al layer 6a at the step portion formed by the polysilicon layer 4a becomes good, which causes smear. Al breaks can be eliminated and a passivation effect can be obtained.
上記実施例は、CCD固体撮像装置の場合について説明
したが、MOS形固体撮像装置や増幅型固体撮像装置等に
おいても本発明は適用できる。Although the above embodiment has been described with reference to a CCD solid-state imaging device, the present invention can be applied to a MOS solid-state imaging device, an amplification type solid-state imaging device, and the like.
H.発明の効果 上述した実施例の説明から明らかなように、本発明の
固体撮像装置によれば、撮像領域上の平坦化膜の膜厚を
周辺回路領域上の平坦化膜の膜厚よりも薄く（ゼロも含
む）しているため、配線抵抗の低減，配線切れの防止を
図ることができ、かつスミアの低減を図ることができ
る。H. Effects of the Invention As is clear from the above description of the embodiment, according to the solid-state imaging device of the present invention, the thickness of the flattening film on the imaging region is larger than the thickness of the flattening film on the peripheral circuit region. Since the wiring is thin (including zero), wiring resistance can be reduced, wiring can be prevented from being cut, and smear can be reduced.
第１図は本発明に係る固体撮像装置の一実施例を示す断
面図、第２図（Ａ）および第２図（Ｂ）は上記一実施例
の固体撮像装置の製造方法を説明するための各断面図、
第３図は本発明に係る固体撮像装置の他の実施例を示す
断面図である。 第４図は従来の固体撮像装置の一例を示す断面図、第５
図は上記従来例の固体撮像装置における周辺回路領域側
の構造を拡大して示す断面図、第６図は同じく撮像領域
側の構造を拡大して示す断面図である。 2a……撮像領域 2b……周辺回路領域 4a,4b……ポリシリコン層 5b,8……平坦化膜 6a,6b……Al層FIG. 1 is a sectional view showing an embodiment of a solid-state imaging device according to the present invention, and FIGS. 2 (A) and 2 (B) are views for explaining a method of manufacturing the solid-state imaging device according to the embodiment. Each sectional view,
FIG. 3 is a sectional view showing another embodiment of the solid-state imaging device according to the present invention. FIG. 4 is a sectional view showing an example of a conventional solid-state imaging device, and FIG.
FIG. 6 is an enlarged sectional view showing a structure on the peripheral circuit region side of the conventional solid-state imaging device, and FIG. 6 is an enlarged sectional view showing the same structure on the imaging region side. 2a: Imaging area 2b: Peripheral circuit area 4a, 4b: Polysilicon layer 5b, 8: Flattening film 6a, 6b: Al layer
Claims (1)
装置において、 上記周辺回路領域上及び上記撮像領域上にそれぞれ第１
配線層が形成され、 上記周辺回路領域上に形成された上記第１の配線層上に
は、平坦化膜を介して第２の配線層が形成され、 上記撮像領域上に形成された上記第１の配線層上には、
上記周辺回路領域上に形成された平坦化膜より薄い平坦
化膜を介して遮光層が選択的に形成されてなる固体撮像
装置。1. A solid-state imaging device having an imaging region and a peripheral circuit region, wherein a first imaging device is provided on each of the peripheral circuit region and the imaging region.
A wiring layer is formed, a second wiring layer is formed on the first wiring layer formed on the peripheral circuit region via a planarization film, and the second wiring layer is formed on the imaging region. On the first wiring layer,
A solid-state imaging device in which a light-shielding layer is selectively formed via a flattening film thinner than the flattening film formed on the peripheral circuit region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169482A JP2570264B2 (en) | 1986-07-18 | 1986-07-18 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169482A JP2570264B2 (en) | 1986-07-18 | 1986-07-18 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6325969A JPS6325969A (en) | 1988-02-03 |
| JP2570264B2 true JP2570264B2 (en) | 1997-01-08 |
Family
ID=15887353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61169482A Expired - Lifetime JP2570264B2 (en) | 1986-07-18 | 1986-07-18 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2570264B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2738679B2 (en) * | 1987-02-25 | 1998-04-08 | 株式会社日立製作所 | Solid-state imaging device |
| JPH04225566A (en) * | 1990-12-27 | 1992-08-14 | Matsushita Electron Corp | Solid state image sensor |
| JP2780512B2 (en) * | 1991-04-12 | 1998-07-30 | 日本電気株式会社 | Solid-state imaging device |
| JPH05102456A (en) * | 1991-10-04 | 1993-04-23 | Matsushita Electron Corp | Solid-state image sensor and manufacture thereof |
| JP2010040650A (en) * | 2008-08-01 | 2010-02-18 | Fujitsu Microelectronics Ltd | Solid state imaging apparatus |
-
1986
- 1986-07-18 JP JP61169482A patent/JP2570264B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6325969A (en) | 1988-02-03 |
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