JP2567699B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device mounted on a data processing device for use.

[Conventional technology]

FIG. 3 is a block diagram of a conventional semiconductor memory device.
This semiconductor memory device is used by mounting it on a data processing device (not shown). Therefore, the power input line 10, address bus 11, write enable signal line connected to the data processing device
12, an output enable signal line 13, a chip enable signal line 14 and a data bus 15.

The power supply input line 10 is connected to a power supply control circuit 6 that outputs a voltage when the input voltage reaches a predetermined value, an address bus buffer 2, an address decoder 4, and a power supply terminal of a 3-state bidirectional buffer (hereinafter referred to as bidirectional buffer) 5. It is also connected to the internal power supply line 24 via the power supply control circuit 6. The power input line 10 is grounded via an input resistor 22, and is connected to the write enable signal line 12, the output enable signal line 13, and the chip enable signal line 14 via pull-up resistors 21, 21, 21 separately. It The internal power supply line 24 is connected to the three-state unidirectional buffer (hereinafter referred to as unidirectional buffer) 3, each power supply terminal of the semiconductor memories 1a ... 1n composed of static RAM, and the cathode of the backflow prevention diode 9. The anode of the diode 9 is connected to the battery 7 via the current limiting resistor 8.
Is connected to the positive electrode and the negative electrode is grounded. Further, the internal power supply line 24 is connected to each gate terminal of the unidirectional buffer 3, the address decoder 4 and the bidirectional buffer 5 via the pull-up resistor 20. The address bus 11 is connected to the input side of the address bus buffer 2 and the selection signal terminal A of the address decoder 4,
It is connected to B and C and is also grounded via a pull-down resistor 23. The output side of the address bus buffer 2 is a semiconductor memory
Connected to each address pin ADD of 1a ... 1n. The write enable signal line 12 and the output enable signal line 13 are separately connected to the write enable terminal ▲ ▼ and the output enable terminal ▲ ▼ of the semiconductor memories 1a ... 1n via the unidirectional buffer 3.

The chip enable signal line 14 is connected to the chip enable terminal ▲ ▼ of the unidirectional buffer 3. The protection signal line 16 of the power supply control circuit 6 is connected to each gate terminal G of the unidirectional buffer 3 and the address decoder 4, and is also grounded via the pull-down resistor 23. 19n of the address decoder 4 are separately connected to the chip enable terminals ▲ ▼ of the semiconductor memories 1a ... 1n. The data terminals DATA of the semiconductor memories 1a ... 1n are connected to the data bus 15 via the bidirectional buffer 5. The semiconductor memory 1a
The direction control signal line 18 connected to the output enable terminal ▲ ▼ of is the direction control signal terminal of the bidirectional buffer 5.
Connected with DIR.

 Next, the operation of this semiconductor memory device will be described.

When the semiconductor memory device is removed from the data processing device (not shown), the voltage of the battery 7 is applied to the internal power supply line 24 through the current limiting resistor 8 and the backflow prevention diode 9. Further, since the power supply to the power supply input line 10 is cut off, the protection signal line 16 of the power supply control circuit 6 becomes "L" and the unidirectional buffer 3
And the address decoder 4 is in a disable (non-operation) state. As a result, all the chip selection signal lines 19a ... 19n of the address decoder 4 become "H", and the semiconductor memory 1a
1n chip enable terminals (1) are disabled, and the semiconductor memories 1a ... 1n hold a standby state. At this time, the current consumption of the semiconductor memories 1a ... 1n is extremely small, and the battery 7 holds the stored data for a long time.

On the other hand, when the semiconductor memory device is attached to the data processing device, power is supplied from the data processing device to the power input line 10, so that the power control circuit 6 operates and the power input line 10 and the internal power line 24 are electrically connected. , The voltage of the power input line 10 is applied to the internal power line 24. Then, the protection signal line 16 becomes "H", and the unidirectional buffer 3 and the gate terminal G of the address decoder 4 are enabled. At this time, since the voltage of the internal power supply line 24 is higher than the voltage of the battery 7, the current of the battery 7 does not flow through the backflow prevention diode 9. When data is read or written between the data processing device and the semiconductor memories 1a ... 1n, the signal of the address bus 11 is applied to the selection signal terminals A, B and C of the address decoder 4 and the chip corresponding to the signal is applied. The semiconductor memories 1a ... 1n are selected by the selection signals 19a ... 19n. When a signal is given to the output enable signal line 13, the direction control signal line 18 to which the direction control signal is given from the unidirectional buffer 3 becomes "L" level, and the data transmission direction of the bidirectional buffer 5 is from the X terminal. Toward the Y terminal,
The storage data read from the semiconductor memories 1a ... 1n are output to the data bus 15. Further, by giving a signal to the write enable signal line 12, the direction control signal line 18 becomes "H" level, the data transmission direction of the bidirectional buffer 5 is changed from the Y terminal to the X terminal, and is given to the data bus 15. The data stored in the semiconductor memory 1a ... 1n
… The data will be written to 1n.

The input resistance 22 holds the input level of the unidirectional buffer 3 at a predetermined value. The pull-down resistors 23, 23 hold the input level of the address decoder 4 at a predetermined value.

On the other hand, in Japanese Patent Laid-Open No. 60-207991, only when the personal identification number output by the operation of the external device matches a predetermined personal identification number, the external device stores the data stored in the memory in the card attached to the external device. The personal identification card that is intended to be read is shown.

[Problems to be Solved by the Invention]

As described above, the semiconductor memory device is composed of a memory, a buffer IC, etc., which are passive functional parts, and therefore, when mounted on a data processing device and given an output enable signal or a write enable signal, the memory is stored from the semiconductor memory. Data can be read or data can be written.

Therefore, if there is a data processing device that can be mounted and the data format is the same, the data can be freely read / written to / from the semiconductor memory device, the confidentiality of the memory data cannot be held, and the memory data is destroyed. There is a problem that it may be The personal identification card disclosed in Japanese Patent Laid-Open No. 60-207991 is stored in the cart when the personal identification number output from the external device matches the personal identification number stored in the personal identification card. Since the data can be read, the storage data in the card can be read by an external device other than the specific external device, and there is a problem that the reading of the storage data is not limited to the specific data processing device.

In view of such a problem, it is an object of the present invention to provide a semiconductor memory device capable of accessing a semiconductor memory and reading / writing stored data only in a specific data processing device.

[Means for solving the problem]

A semiconductor memory device according to the present invention has a built-in semiconductor memory, and in a semiconductor memory device mounted and used in a data processing device, the data processing device outputs the semiconductor memory so as to access the semiconductor memory device. A CPU for receiving the identification data for specifying via a signal line, a protection means for enabling / disabling the reading / writing of the stored data with respect to the semiconductor memory, and the signal between the CPU and the data processing device. A state in which data can be transmitted and received via a line, when the password data matches with the password data stored in advance by the CPU, between the semiconductor memory and the data processing device via the signal line. A switching means for switching to a state in which data can be transmitted and received, and a state in which data can be transmitted and received between the semiconductor memory and the data processing device by the switching means. If switched to is characterized in that to the semiconductor memory by said protection means are constituted to be capable of forming a read / write memory data.

[Action]

The CPU receives, via the signal line, personal identification data that the data processing device outputs to access the semiconductor memory and that specifies the data processing device. When the personal identification data received by the CPU and the personal identification data stored in advance by the CPU match, the CPU and the data processing device are switched to a state in which data can be transmitted and received via the signal line. When the semiconductor memory and the data processing device are switched to a state in which data can be transmitted and received via the signal line, the protection means enables reading / writing of stored data with respect to the semiconductor memory.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing its embodiments.

FIG. 1 is a block diagram of a semiconductor memory device according to the present invention. Since this semiconductor memory device is mounted on a data processing device (not shown) and used, a power input line 10, an address bus 11, a write enable signal line 12, an output enable signal line 13, and a chip enable connected to the data processing device are used. It has a signal line 14 and a data bus 15. Power input line
Reference numeral 10 is connected to a power supply control circuit 6 for outputting a voltage whose input voltage is a predetermined value, an address bus buffer 2, an address decoder 4, and a power supply terminal of a 3-state bidirectional buffer (hereinafter referred to as bidirectional buffer) 5. And is connected to the internal power supply line 24 via the power supply control circuit 6. Also power input line
10 is grounded via an input resistor 22 and pull-up resistors 21,2
Write enable signal line 12, output enable signal line 13, chip enable signal line 14 via 1 and 21 separately
Connected to The internal power supply line 24 is connected to the three-state unidirectional buffer (hereinafter referred to as unidirectional buffer) 3, each power supply terminal of the semiconductor memories 1a ... 1n composed of static RAM, and the cathode of the backflow prevention diode 9. The anode of the diode 9 is connected to the positive electrode of the battery 7 via the current limiting resistor 8, and the negative electrode thereof is grounded. Further, the internal power supply line 24 is connected to each gate terminal (1) of the unidirectional buffer 3, the address decoder 4 and the bidirectional buffer 5 via the pull-up resistor 20. The address bus 11 is connected to the input side of the address bus buffer 2 and the selection signal terminals A, B and C of the address decoder 4, and is grounded via the pull-down resistor 23.

The output side of the address bus buffer 2 is the semiconductor memory 1a ...
Connected to each 1n address pin ADD. The write enable signal line 12 and the output enable signal line 13 are connected via the unidirectional buffer 3 to the write enable terminal ▲ ▼ and the output enable terminal ▲ ▼ of the semiconductor memories 1a ... 1n. Chip enable signal line 14
Is connected to the chip enable terminal ▲ ▼ of the unidirectional buffer 3. The protection signal line 16 of the power supply control circuit 6 is an AND circuit 3
1 is connected to one input terminal 31a, and its output terminal 31c is connected to each gate terminal G of the unidirectional buffer 3 and the address decoder 4.
And is grounded via a pull-down resistor 23. 19n to which the address decoder 4 gives a chip selection signal are separately connected to the respective chip enable terminals ▲ ▼ of the semiconductor memories 1a ... 1n. The interrupt signal line 29 for outputting the interrupt signal of the address decoder 4 is the CPU 25
Connected to the interrupt terminal DV of. The clock of the clock generation circuit 27 is given to the clock terminal CK of the CPU 25, and the reset signal is given from the reset circuit 28 to the reset terminal RS. The reset signal is output for a predetermined time after the semiconductor memory device is attached to the data processing device. The output terminal OP is connected to the other input terminal 31b of the AND circuit 31. This CPU 25 is, for example, a 1-chip microcomputer with a built-in memory or an external memory connectable 1
A chip microcomputer is used. After the CPU 25 is powered on, the output terminal OP and the input / output terminal IOP are in a floating state after the reset is released. Semiconductor memory 1a ... 1
The data terminal DATA of n is connected to the data bus 15 via the bidirectional buffer 5. Data line 15 of data bus 15
a is connected to the changeover contact 26c of the changeover switch 26. The one-side fixed contact 26a of the changeover switch 26 has the first data line 15b ₁
Via the input / output terminal IOP of the CPU 25. Further, the first data line 15b ₁ is connected to the power supply input line 10 via the pull-up resistor 21. The second data line 15b ₂ connected to the other side fixed contact 26b of the changeover switch 26 is connected to the data line terminal to which the data line 15a should be connected to the bidirectional buffer 5. Further, the secret security signal line 30 to which the gate terminal GT for giving a signal to switch and control the switching contact 26c is connected is grounded via the pull-down resistor 23 and is also connected to the output terminal OP of the CPU 25. Changeover switch 26 has its gate GT
When the signal of "H" is given to, the switching contact 26c switches to the other side fixed contact 26b side, that is, the bidirectional buffer 5 side,
When the "L" signal is given, the one side fixed contact 26a side, that is, C
Switch to PU25 side.

Next, the operation of the semiconductor memory device thus configured will be described.

When the semiconductor memory device is removed from the data processing device (not shown), the voltage of the battery 7 is applied to the internal power supply line 24 via the current limiting resistor 8 and the backflow prevention diode 9. Further, since the power supply to the power supply input line 10 is cut off, the protection signal line of the power supply control circuit 6 becomes "L", and the unidirectional buffer 3 and the address decoder 4 are disabled. Line 19a ... 1
All 9n become "H", each chip enable terminal ▲ ▼ of semiconductor memory 1a ... 1n becomes disable state,
The semiconductor memories 1a ... 1n hold a standby state. At this time, the current consumption of the semiconductor memories 1a ... 1n is extremely small, and the battery 7 holds the stored data for a long time.

Further, in the CPU 25, since the clock generation circuit 27 and the reset circuit 28 do not operate, the security signal line 30 is set to the ground level by the pull-down resistor 23.

Next, when the semiconductor memory device is attached to the data processing device, a voltage higher than a predetermined voltage is applied to the power input line 10.
The power supply control circuit 6 operates and the power supply input line 10 and the internal power supply line
24 becomes conductive, the protection signal line 16 becomes "H" level, and one input terminal 31a of the AND circuit 31 becomes "H". Further, since the CPU 25 is once reset by mounting the semiconductor memory device and the secret protection signal line 30 is at “L” level after the reset is released, the other input terminal 31b of the AND circuit 31 is at “L” level, The output terminal 31c becomes "L" level. Therefore, the unidirectional buffer 3 and the address decoder 4 are in the disable state, and the semiconductor memories 1a ... 1n are not selected.
At this time, since the gate terminal GT of the changeover switch 26 is at the "L" level, the changeover contact 26c is switched to the one-side fixed contact 26c side and remains connected to the CPU 25. … Inaccessible 1n.

However, it becomes possible to send and receive data between the CPU 25 and the data processing device.

Next, description will be given with reference to the flowchart of FIG. 2 showing a control procedure when the semiconductor memory device is attached to the data processing device.

When the semiconductor memory device is attached to the data processing device, the data processing device detects the voltage between the connection terminals and confirms that it is attached (S1). After that, the data processing device uses the CPU 25 to access the semiconductor memory of the semiconductor memory device.
Send secret data to (S2). The CPU 25 collates the previously stored personal identification data with the given personal identification data, and determines whether to permit access to the semiconductor memories 1a ... 1n (S3). To allow reading of stored data (S
4), from the CPU 25, via the changeover contact 26c of the changeover switch 26 and the data line 15a, transmits data permitting access to the semiconductor memories 1a ...
U25 provides the "H" level signal to the security signal line 30.
As a result, the other input terminal 31b of the AND circuit 31 becomes "H" and its output terminal 31c becomes "H". Security signal line 30
Is changed to “H”, the changeover switch 26 becomes a changeover contact.
26c is switched to the other side fixed contact 26b side, and all bits of the data bus 15 are connected to the bidirectional buffer 5 (S6).

In this state, the data processing device is changed to the semiconductor memory 1a.
1n can be accessed, and the data processing device can read the storage data of the semiconductor memories 1a 1n.

On the other hand, if the CPU 25 determines that the data processing device cannot permit the reading of the stored data due to the mismatch of the password data (S5), the secret security signal line 30 is kept at the "L" level. Then, the changeover contact 26c of the changeover switch 26 is C
The semiconductor memory 1a ...
It becomes impossible to access 1n from the data processing device, and the secret of the stored data of the semiconductor memories 1a ... 1n is preserved.

When the data permitting access is transmitted as described above, the changeover contact 26c of the changeover switch 26 is switched to the one-side fixed contact 26a side, so that data transmission / reception cannot be performed between the data processing device and the CPU 25. Becomes Therefore, when it is desired to transmit data from the data processing device to the CPU 25 after that, when the data processing device provides the address bus 11 with a signal capable of outputting the interrupt signal, the address decoder 4 causes the interrupt signal line 29 to generate the interrupt signal. Will be given. Thereby, the CPU 25 can know that the data processing device requests transmission and reception of data with the CPU 25. Then, the CPU 25 sets the confidentiality protection signal line 30 to the “L” level to change the contact of the changeover switch 26.
26c and is connected to the data line 15a is switched to the one-side contact side 26c and the second data line 15b ₂ is, it is possible to send and receive data between the CPU25 and the data processing device.

Note that, so far, the reading of the stored data has been described, but the same can be performed when writing the stored data to the semiconductor memory and further when reading and writing the stored data.

In this way, the signal line and the number of terminals for the interface between the data processing device and the semiconductor memory can be provided as they are in the conventional manner to provide the confidentiality retaining function of the stored data.

Although the data line 15a is one data bit line in this embodiment, all the bit lines may be connected to the CPU 25 through the changeover switch 26 and the input / output terminal IOP.
Although the clock generating circuit 27 is built in the CPU 25, an external clock may be obtained from the data processing device. Further, an external interrupt signal may be given from the data processing device instead of the interrupt signal given to the CPU 25. Furthermore, the semiconductor memories 1a ... 1n are static RAM, but EPROM, OTPROM or E
It may be EPROM. In this case, the battery 7, the current limiting resistor 8 and the backflow prevention diode 9 are unnecessary.

〔The invention's effect〕

As described in detail above, according to the present invention, the semiconductor memory can be accessed only by a specific data processing device, the stored data in the semiconductor memory can be kept secret, and the stored data can be prevented from being destroyed. Further, since the signal lines and terminals for the conventional interface can be used as they are, the structure does not become complicated, the stored data is kept secret, and the semiconductor memory device which does not destroy the stored data can be provided at a low cost. Play.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to the present invention, FIG. 2 is a flowchart showing a control procedure when the semiconductor memory device is attached to a data processing device, and FIG. 3 is a block diagram of a conventional semiconductor memory device. is there. 1a ... 1n ... Semiconductor memory, 3 ... 3-state unidirectional buffer, 4 ... Address decoder, 5 ... 3-state bidirectional buffer, 6 ... Power control circuit, 7 ... Battery, 10
...... Power input line, 11 ...... Address bus, 12 ...... Write enable signal line, 13 ... Output enable signal line,
14 …… Chip enable signal line, 15 …… Data bus, 24
...... Internal power supply line, 25 ... CPU In the figures, the same symbols indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A semiconductor memory device having a built-in semiconductor memory, which is mounted on and used in a data processing device, wherein the data processing device outputs the password for accessing the semiconductor memory to identify the data processing device. Via a signal line, a protection means for enabling / disabling the reading / writing of stored data with respect to the semiconductor memory, and a signal line between the CPU and the data processing device via the signal line. The state that data can be sent and received
Switching means for switching to a state in which data can be transmitted and received between the semiconductor memory and the data processing device via the signal line when the password data matches the password data stored in advance by the CPU. When the switching means switches to a state in which data can be sent and received between the semiconductor memory and the data processing device, the protection means is configured to enable reading / writing of stored data to / from the semiconductor memory. A semiconductor memory device characterized by the above.