JP2566758B2 - Test signal generation circuit in IC tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial field of application) The present invention is for testing in an IC tester used when a test signal is applied to each terminal of the IC to test the operation of the IC. The present invention relates to a signal generation circuit.

(Prior Art) Conventionally, at a predetermined stage in the manufacture of an IC, an operation test is performed in which a test signal is applied to each terminal of the IC to detect whether or not an output reaction is normal.

FIG. 2 shows the configuration of the test signal generation circuit in the IC tester used in this operation test.

Q _1, Q ₂ and Q _5, Q ₆ drive transistor in the figure, Q _3, Q ₄ and Q _7, Q ₈ denotes a switching transistor, D _1, D ₂ are each four diodes formed by connecting a diode clamp The circuits, U _{1 to} U _3, are line receivers for generating each signal.

DRVINP applied to the line receiver U ₁ is a signal that specifies the width and cycle of the test signal to be applied to the terminals of the IC to be tested (hereinafter referred to as DUT), and DVH is the maximum peak value of the test signal. Signal for setting (H level voltage), DVL is the minimum peak value (L level) of the test signal
Is a signal for setting.

Further, DRVENA is a signal for switching enable / disable of the switching transistor by turning on / off each drive transistor.

When the emitter voltage of the drive transistors Q ₁ , Q ₂ and Q ₅ , Q ₆ is cut off by this DRVENA signal, no current flows in the following switching transistors Q ₃ , Q ₄ and Q ₇ , Q ₈ .

FIG. 3 is a diagram showing waveforms of test signals in the circuit of FIG.

In the figure, DVH indicates the maximum peak value, DVL indicates the minimum peak value, and DRVENA indicates the period during which the switching transistor is enabled.

In the circuit shown in FIG. 2, the maximum peak value DVH and the minimum peak value DVL of the test signal can be adjusted by the signals DVH and DVL.

By the way, switching transistors Q ₃ , Q ₄ and Q ₇ ,
The collector loss at Q ₈ varies greatly depending on the difference between the peak value of the test signal and the power supply ± Vcc.

In Fig. 2, the current flowing through the diode clamp circuit D ₁ is as follows: + Vcc → Transistor Q ₃ → DVH line (current I ₁ ) and DVH line → Transistor Q ₈ → −Vcc (current I ₂ ) Ideally, these currents have the same value.

Similarly, the current flowing through the diode clamp circuit D ₂ is + Vcc → transistor Q ₄ → DVL line (current I ₃ ) and DVL line → transistor Q ₇ → −Vcc path (current I ₄ ). However, it is ideal that these currents have opposite signs and equal values.

Therefore, in this circuit, the value of each element is set so that I ₁ −I ₂ = 0 and I ₃ −I ₄ = 0.

In addition, switching transistors Q ₃ , Q ₄ and Q ₇ , Q
₈ operates as a constant current switch determined by resistors R ₁ and R ₂ , respectively, and the maximum loss P of each transistor P
(Q) is P (Q ₄ ) ≈ [(+ Vcc−I ₃ R ₁ ) −DVL] × I ₃ (1) P when the pulse width of the test signal is instructed to 0 by the signal DRVINP. (Q ₇ ) ≒ [(-Vcc + I ₄ R ₂ ) + DVL] × I ₄ (2) The power P (DRV) during switching operation is P (DRV) when the loss in the diode clamp circuit D ₁ is 0. = (P (Q ₄ ) + P (Q ₇ ) = I ₃ [(+ Vcc−I ₃ R ₁ ) −DVL + (− Vcc + I ₄ R ₂ ) + DVL].

From the above equations (1) and (2), P (Q ₄ ) decreases in inverse proportion to the minimum peak value DVL as the minimum peak value DVL approaches the power supply voltage Vcc. At this time, P (Q ₇ ) is the minimum. Crest value DV
It can be seen that it increases in proportion to L. As described above, in this circuit, I ₃ = I ₄ , so that even if the minimum peak value DVL changes, the total power loss does not change. Therefore, if the minimum peak value DVL = 0, then P (DRV) = I ₃ [(+ Vcc−I ₃ R ₁ ) + (− Vcc + I ₄ R ₂ )] (3) Similarly, P (Q ₃ ), P (Q ₈ ) Power loss P (DR
V) ′ is P (DRV) ′ = I ₁ [(+ Vcc−I ₁ R ₁ ) + (− Vcc + I ₂ R ₂ )] (4) The current I _{1 is} calculated by the above equations (3) and (4). , I ₃ and resistance
Since the voltage drop due to R ₁ and R ₂ has a constant value, it can be seen that it is effective not to increase ± Vcc more than necessary in order to reduce the power.

However, as can be seen from Fig. 2, in the test signal generation circuit in the conventional IC tester, the drive voltage of the switching transistor is fixed to the power supply ± Vcc, so when the peak value of the test signal is adjusted. ,Power supply
The power loss of the switching transistor increases in proportion to the difference from Vcc.

In addition, the withstand voltage required for the switching transistor is increased, and particularly when the switching operation is performed at high speed, the selection of parts is considerably limited.

Further, since the switching operation of the transistor is limited by the storage state of internal carriers, it is desirable to narrow the switching range as much as possible.

(Problems to be Solved by the Invention) The present invention has been made under the circumstances described above.
The switching range of the switching transistor is narrow,
The purpose is to provide a test signal generation circuit for an IC tester that minimizes power loss.

[Configuration of Invention] (Means for Solving Problems) The test signal generating circuit in the IC tester of the present invention is
Maximum peak value indication signal (DV
The first clamp circuit (D ₃ ) for outputting the IC test signal (Drive Out) according to H) and the minimum peak value indication signal (DV) that indicates the minimum peak value of the signal.
Connected to the second clamp circuit (D ₄ ) for outputting the IC test signal (Drive Out) according to L) and the first clamp circuit (D ₃ ) and instructing the signal width and timing. A plurality of maximum peak value switching transistors (Q ₁₁ , Q ₁₅ ) for driving the first clamp circuit (D ₃ ) in response to an instruction signal (DRVINP) to be generated, and the second clamp circuit (D ₄ ) A plurality of minimum peak value switching transistors (Q ₁₂ , Q ₁₆ ) which are connected to the drive circuit and drive the second clamp circuit (D ₄ ) in response to the instruction signal (DRVINP); (DVH) first voltage (VS) required for switching transistor operation added 1st
Voltage (DVH + VS) of the first voltage control means (U ₄ ) and the maximum voltage value indicating signal (DVH) from the predetermined voltage (V
And second voltage control means for generating a second voltage obtained by subtracting the S) (DVH-VS) ( U 10), and outputs a signal corresponding to said maximum peak value as the IC test signal (Drive Out) At this time, a circuit for supplying a drive voltage generated by the first and second voltages (DVH + VS, DVH−VS) to the maximum peak value switching transistors (Q ₁₁ , Q ₁₅ ) and the minimum peak value instruction. The specified voltage (V
S) is added to generate a third voltage (DVL + VS), a third voltage control means (U ₁₁ ), and the minimum peak value instructing signal (DVL),
A fourth voltage control means for generating a fourth voltage obtained by subtracting the S) (DVL-VS) ( U 9), and outputs a signal corresponding to said minimum peak value as the IC test signal (Drive Out) At this time, a circuit for supplying a drive voltage generated by the third and fourth voltages (DVL + VS, DVL-VS) to the minimum peak value switching transistors (Q ₁₂ , Q ₁₆ ) is provided. It is a feature.

(Operation) In the test signal generation circuit in the IC tester of the present invention, the peak value of the drive signal of the switching circuit is adjusted in synchronization with the peak value of the IC test signal, so that the power loss in the switching circuit is extremely small. .

(Example) Hereinafter, the detail of the Example of this invention is described based on drawing.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

In the figure, Q ₉ , Q ₁₀ and Q ₁₃ , Q ₁₄ are drive transistors, and Q ₁₁ , Q ₁₂ and Q ₁₅ , Q ₁₆ are switching transistors. D ₃ and D ₄ are diode clamp circuits composed of four diodes, U _{5 to} U ₈ are line receivers for generating each signal, and U _{9 to} U ₁₁ are operational amplifiers for generating each voltage signal.

In the circuit of this embodiment, from the source voltage (+ VS) obtained from the voltage dividing resistors R ₃ and R ₄ , the source voltage (−VS) obtained from the voltage dividing resistors R ₅ and R ₆ , and the peak value indicating signals DVH and DVL, , Voltage DVH
+ VS, voltage DVH-VS, voltage DVL + VS, voltage DVL-VS are created and used as the drive voltage for each switching transistor.

In the circuit of this embodiment, operational amplifiers U ₄ , U ₁₀ and U ₉ , U ₁₁
Causes DVH ± VS and DVL ± VS to be added to each other.

And line receiver U ₅ , transistor Q ₉ , Q
₁₀ (or line receiver U ₈ , transistor Q ₁₃ ,
The circuit composed of Q ₁₄ ) switches the drive voltage of switching transistors Q ₁₁ and Q ₁₂ (or Q ₁₅ and Q ₁₆ ) in synchronization with the ON / OFF cycle of DRVINP. Ie DR
When VINP is ON (+), the voltage from the operational amplifier U ₄ is DVH + VS
Is supplied to transistor Q ₉ and its output is
It becomes the drive voltage of ₁₁ and the current I ₅ flows.
The clamp corresponding to H is executed.

The clamp voltage of DVH becomes a current I ₇ , passes through the transistor Q ₁₅ , and flows to DVH-VS switched by the transistor Q ₁₃ .

When DRVINP is OFF (−), the voltage DVL + VS voltage from the operational amplifier U ₁₁ is supplied to the transistor Q ₁₀ , and its output is supplied to the transistor Q ₁₂ .

Then, the collector current I ₆ of the transistor Q ₁₂ passes through the diode clamp circuit D ₄ and drives out (Drive O
ut) is output.

The sink current I ₈ of the diode clamp circuit D ₄ passes through the transistor Q ₁₆ and is switched by the transistor Q _14, and joins the DVL-VS formed in the operational amplifier U ₉ .

And the switching transistor Q in this circuit
The power loss of ₁₁ , Q ₁₂ and Q ₁₅ , Q ₁₆ is P
(Q ₁₁ ), P (Q ₁₂ ) and P (Q ₁₅ ), P (Q ₁₆ ), P (Q ₁₁ ) = I ₅ [(DVH + VS) − (I ₅ × R ₇ ) −DVH] ... …
(5) P (Q ₁₂ ) = I ₆ [(DVL + VS) − (I ₆ × R ₇ ) −DVL] ......
(6) P (Q ₁₅ ) = I ₇ [(DVH−I ₇ × R ₈ ) − (DVH−VS)] ......
(7) P (Q ₁₆ ) = I ₈ [(DVL-I ₈ × R ₈ )-(DVL-VS)] ......
(8) From the equations (5) to (8), the difference between each I (current) × R (resistance) drop voltage and the source voltage VS is 1 V (collector-emitter voltage of the transistor + forward voltage of the diode). ), I ₅ = I ₆ = I ₇ = I ₈ That is, if the source current and the sink current in the diode clamp circuits D ₃ and D ₄ are made equal, the ON loss of each transistor becomes equal, and P ( Q ₁₁ ) = P (Q ₁₂ ) = P (Q ₁₅ ) = P (Q ₁₆ ) = I × 1 (V). Then, the power loss becomes maximum when the duty is 0% or 100% when either one of the source and the sink of these transistors is operating. Therefore, it can be seen that the maximum value of P (DRV) = 2I × 1 (V).

Thus, in the test signal generation circuit in the IC tester of this embodiment, when the peak value of the test signal applied to each terminal of the DUT is changed, the drive voltage of the switching transistor is changed according to the setting condition of the peak value indicating signal. Therefore, the loss in each transistor can be minimized.

In the test signal generation circuit in the conventional IC tester, if the peak value of the test signal is changed, the power supply voltage Vcc
As the difference between and increases, the heat loss inside the switching transistor increases.

The withstand voltage of the switching transistor (maximum allowable voltage between collector and base, maximum allowable voltage between collector and emitter) is proportional to the difference between the maximum and minimum peak values.
Must also be large.

On the other hand, in the test signal generating circuit in the IC tester of this embodiment, the diode clamp circuits D ₃ and D ₄ and the voltage switching circuit (line receiver U ₅ , transistor Q ₉ , Q ₁₀ / line receiver U ₈ , transistor Q ₁₃ , transistor Q ₁₃ , Q ₁₄ ) and a voltage generator (op amp U ₄ , op amp U ₁₀ , op amp U ₉ , op amp U ₁₁ ) are combined to generate drive out of the test signal.

Also, turn on the diode clamp circuit and voltage switching circuit.
The minimum voltage required to operate (switching transistor collector-emitter voltage + diode forward voltage + I × R drop voltage) is compensated by ± VS.

Subsequently, the power loss in the switching transistor of the circuit of this embodiment and the circuit shown in FIG. 2 will be compared.

Conditions of minimum power losses in the circuit of Figure 2 is when the _{+ Vcc-I 3 R 1 =} DVH -Vcc-I 4 R 2 = DVL. The maximum loss under this condition is 2 × I (DVH−DVL) = P when the loss due to each diode is 0. If I = 50mA, DVH = 13.5V, DVL = −2V, P = 2 × 0.05 [13.5-(-2)] = 1.55W. That is, 1.55W is consumed by the switching transistor for one terminal of the DUT, and 446W is consumed for 288 terminals (the maximum number of DUT terminals that can be tested).

On the other hand, in the circuit of this embodiment, P = 2 × 0.05 × 1 = 0.1 W. In other words, 0.1W is consumed by the switching transistor for one DUT terminal, and even 288 terminals consumes only 28.8W. Therefore, compared with the circuit of FIG. 2, the power consumed by the switching transistor is 1/5.

Further, in the circuit of FIG. 2, the maximum allowable collector-emitter voltage of the switching transistor is at least 20 (V), but in the circuit of this embodiment, about 3 to 5 V is sufficient.

Further, when the power consumption in the high-speed switching stage is suppressed as in the circuit of this embodiment, the stress applied to the device is also reduced, and as a result, the reliability of the IC tester is improved.

Since the power consumption of the entire circuit of this embodiment is determined by the magnitudes of ± Vcc and the test signal, the power consumption seen from the DC power supply is the same as that of the conventional circuit.

The power saved by the switching transistor is
It is consumed by the level setting operational amplifiers U ₄ , U ₁₀ and U ₉ , U ₁₁ , but there is no problem because these operational amplifiers do not perform high-speed switching operation.

In the circuit of this embodiment, if the drive transistor and the switching transistor are separated and the drive transistor is placed outside, thermal design becomes easy (heat generation in the test head is suppressed).

In recent years, the number of DUT pins has tended to increase, but if the power consumption of the test signal generation circuit for each pin is reduced, the IC tester body can be packaged more closely. It is possible to promote simplification of the cooling system, etc.

[Effects of the Invention] As described above, the test signal generating circuit in the IC tester of the present invention uses the IC test signal (Drive) corresponding to the maximum peak value indicating signal (DVH) that indicates the maximum peak value of the signal.
The first clamp circuit (D ₃ ) for outputting (Out) and the minimum peak value indicating signal (DV) that indicates the minimum peak value of the signal.
Connected to the second clamp circuit (D ₄ ) for outputting the IC test signal (Drive Out) according to L) and the first clamp circuit (D ₃ ) and instructing the signal width and timing. A plurality of maximum peak value switching transistors (Q ₁₁ , Q ₁₅ ) for driving the first clamp circuit (D ₃ ) in response to an instruction signal (DRVINP) to be generated, and the second clamp circuit (D ₄ ) A plurality of minimum peak value switching transistors (Q ₁₂ , Q ₁₆ ) which are connected to the drive circuit and drive the second clamp circuit (D ₄ ) in response to the instruction signal (DRVINP); (DVH) first voltage (VS) required for switching transistor operation added 1st
Voltage (DVH + VS) of the first voltage control means (U ₄ ) and the maximum voltage value indicating signal (DVH) from the predetermined voltage (V
And second voltage control means for generating a second voltage obtained by subtracting the S) (DVH-VS) ( U 10), and outputs a signal corresponding to said maximum peak value as the IC test signal (Drive Out) At this time, the first and second switching transistors (Q ₁₁ , Q ₁₅ ) for the maximum peak value
A circuit for supplying a drive voltage generated by the voltage (DVH + VS, DVH-VS), and the predetermined voltage (VVL) to the minimum peak value indicating signal (DVL).
S) is added to generate a third voltage (DVL + VS), a third voltage control means (U ₁₁ ), and the minimum peak value instructing signal (DVL) is applied to the predetermined voltage (V
A fourth voltage control means for generating a fourth voltage obtained by subtracting the S) (DVL-VS) ( U 9), and outputs a signal corresponding to said minimum peak value as the IC test signal (Drive Out) At this time, a circuit for supplying the drive voltage generated by the third and fourth voltages (DVL + VS, DVL-VS) to the minimum crest value switching transistors (Q ₁₂ , Q ₁₆ ), Since the switching operation range of the switching transistor is narrowed, the power loss can be suppressed as much as possible. Also, the withstand voltage of the switching transistor can be small.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of a test signal generation circuit in a conventional IC tester, and FIG. 3 is a test output by the circuit. It is a figure which shows the waveform of the signal for use. Q _{1 to} Q ₁₆ …… Transistors U _{1 to} U ₃ , U _{5 to} U ₈ …… Line receivers U ₄ , U _{9 to} U ₁₁ …… Op Amp D _{1 to} D ₄ …… Diode clamp circuit R _{1 to} R ₈ … …resistance

Claims (1)

(57) [Claims] 1. An IC test signal (Drive Out) corresponding to a maximum peak value indicating signal (DVH) indicating a maximum peak value of the signal.
The first clamp circuit (D ₃ ) for outputting and the minimum peak value indication signal (DV
Connected to the second clamp circuit (D ₄ ) for outputting the IC test signal (Drive Out) according to L) and the first clamp circuit (D ₃ ) and instructing the signal width and timing. A plurality of maximum peak value switching transistors (Q ₁₁ , Q ₁₅ ) for driving the first clamp circuit (D ₃ ) in response to an instruction signal (DRVINP) to be generated, and the second clamp circuit (D ₄ ) Connected to the second clamp circuit (D ₄ ) according to the instruction signal (DRVINP).
And a plurality of minimum peak value switching transistors (Q ₁₂ , Q ₁₆ ) for driving the first peak voltage (VS) and a first voltage (VS) added to the maximum peak value indicating signal (DVH). First voltage control means (U ₄ ) for generating DVH + VS)
From the maximum peak value indication signal (DVH) to the predetermined voltage (V
And second voltage control means for generating a second voltage obtained by subtracting the S) (DVH-VS) ( U 10), and outputs a signal corresponding to said maximum peak value as the IC test signal (Drive Out) At this time, the first and second switching transistors (Q ₁₁ , Q ₁₅ ) for the maximum peak value are
A circuit for supplying a drive voltage generated by the voltage (DVH + VS, DVH-VS) of the above, and the predetermined voltage (VS) to the minimum peak value indicating signal (DVL).
And a third voltage control means (U ₁₁ ) for generating a third voltage (DVL + VS) that is obtained by adding
A fourth voltage control means for generating a fourth voltage obtained by subtracting the S) (DVL-VS) ( U 9), and outputs a signal corresponding to said minimum peak value as the IC test signal (Drive Out) At this time, a circuit for supplying the drive voltage generated by the third and fourth voltages (DVL + VS, DVL-VS) to the minimum peak value switching transistors (Q ₁₂ , Q ₁₆ ). A test signal generation circuit in the characteristic IC tester.