JP2566356B2 - Fault-tolerant multiprocessor computer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to computer systems, and more particularly to a multiprocessor computer system that is fault tolerant to processor siphon cache storage errors.

[0002]

BACKGROUND OF THE INVENTION As personal computers and workstations become more and more powerful, one of the main problems faced by traditional mainframe vendors is the inconvenience of rapidly evolving, relatively small machines from their own machines. It is in the differentiation of medium-sized systems. One important area in which mainframe machines can be differentiated from smaller ones is in the area of fault tolerance.

The problem of processor cache storage errors has been a problem throughout the history of the use of cache memory in mainframe systems. These errors can be caused by alpha particle collisions or transient (or hard) storage element failures, as can main memory errors. In the case system where the present invention finds use, a single bit error in main memory is a dedicated hardware in memory controller that corrects the bit in error before the word associated with the fault is sent to the requesting device. Hides from the visibility of the system. However, processor cache failures are not corrected during cache read activity because the correction hardware is not designed for the processor for many reasons, including the limited integrated circuit area available on VLSI chips.

The benefits of processor cache memory greatly outweigh the complications that arise in the event of a failure. The cache memory provides fast access to the data and instructions that the processor would otherwise have to retrieve from memory for each query. Cache memory typically takes 10-25% of the time required to access main memory, thus cache memory has gained a permanent position in the system's data storage hierarchy.

The computer design effort of incorporating cache memory into its central processing unit architecture must address the following increasing challenges.

1. It is imperative that the processor detect error conditions in the cache, otherwise it will result in data corruption. The cheapest solution to this problem is to do nothing but hang or crash the system when this kind of error occurs, but as a practical matter, this is totally acceptable for mainframes. Absent.

2. A well-equipped machine should support the deconfiguration of failed cache storage elements. By simply deconfiguring the isolated failing element, the processor can continue execution without substantial performance loss. Cache memory is divided into blocks containing many cache storage elements. In this exemplary machine, the block size is 16 words (64 bytes). The cache memory can also be subdivided into more coarse subdivisions, such as levels meaning the entire column of blocks in this context. In the exemplary machine, it is designed with logic that allows its cache blocks and cache levels to be individually deconfigured.

3. A truly fully equipped machine can either retrieve a recent copy of the block in error from main memory when a processor cache error occurs, or somehow correct the block in error. Should be guaranteed. In the exemplary machine, error correction code is incorporated to correct single bit errors in cache blocks that occur only during writes to main memory. However, the design of this machine is
Clear "unnatural" corrections of blocks or resumption of affected instructions were not covered. ("Unnatural"
Is used in the text to indicate that blocks are required to be exchanged for correction, even though the natural replacement algorithm does not dictate such an event on error. ) 4. Store-in cache, such as an exemplary device
The machine can operate very efficiently, but the delay characteristics of writes to main memory that do the work are a burden when other processors are added to the system to further improve processing power. . A multi-processor configuration handles cache errors, that is, blocks in error are in one processor's cache and are requested by more than one processor, and an "updated" copy of the block is in system main memory. Not cache
This is the final challenge in handling errors in operand blocks. This problem for the purposes of the present invention is commonly referred to as the siphon error condition. (What is a siphon?
A term in the art used to define the transfer of cache blocks from one processor of a multiprocessor system to another processor or I / O device. ) Similar problems encountered in uniprocessor systems are described in D. S. Edwa
rds et al. US patent application "Fault Toleran"
Related inventions encompassed by "T Computer System" are the subject of this disclosure.

One store-in cache prior art system corrects errors when data containing errors is read from the cache by adding error correction hardware to each cache to eliminate cache error in the processor. Dealing with problems. This is an effective but expensive solution to the problem.

A second prior art attempt to resolve cache data correction and retry conditions is a store-through
It had a built-in method to conceal the problem by implementing a cache. (In a store-through structure, when a cache block is updated, this cache block is immediately written to both cache and main memory.) Such an attempt causes an error in fetching from the cache. At any time, the processor forces a cache bypass to issue a memory read for the block used both during instruction execution and cache update (restore). The advantage of this solution is that the affected instructions are not impacted and therefore
Ejection from memory is consistent with a cache miss condition so that all such errors can be recovered. This solution takes advantage of the store-through design, which by definition provides the benefit of constantly updating main memory.

Store-in cache design (copy
Known as back cache) is a relatively small amount of main memory traffic that results in less processor-to-memory write activity, and therefore less bottlenecks in the system bus when certain bus designs are realized. Because the resulting store
This is advantageous for performance-oriented systems superior to the through design. Store-in characteristics that provide enhanced performance necessarily result in a cache that often contains only a valid copy of a particular block of data in the system. That is, when a cache block is modified, it is not written back to main memory. Instead,
This is the second active device (CPU or I / O
Device) or until it is written back to main memory when this block must be replaced to make room in the cache for a new block.

One of ordinary skill in the art will, in another attempt, achieve the benefits of these prior art solutions to processor cache error conditions without the cost and complexity associated with prior art solutions. It will be clear that is highly desirable.

[0013]

SUMMARY OF THE INVENTION Accordingly, a broad object of the present invention is to provide a solution to a processor cache error condition that is simple and economical to implement.

A more particular object of the present invention is to provide a solution to a processor's cache error condition in a problem situation when used in a system containing multiple processors that attempt to access the cache memory of the individual processors with each other. It is in.

In summary, the above and other objects of the invention detect a parity error in a cache memory and an information block read / written with respect to a cache memory device, respectively. Then, a fault tolerant computer system including a plurality of central processing units having a cache memory device with a parity error detector for producing a read or write cache error flag. A system bus connects the CPU to the system controller with parity error correction and a memory bus connects the SCU to main memory.
An error recovery control function distributed across the CPU, service processor and operating system software causes the failing block from the sending CPU to the SCU.
Associated with siphoning to transfer the corrected memory block from main memory to the receiving CPU when it is transferred to main memory via (the given failing block is corrected) and then retried. And send CP
Responsive to detection of a read parity error flag at U and a write parity error flag at the receiving CPU.

The subject matter of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. However, for the present invention, both in terms of construction and method of operation,
It will be best understood by referring to the following description in connection with the appended claims and the accompanying drawings.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Reference is first made to FIG. 1 which illustrates an exemplary Central Subsystem Structure (CSS) in which the present invention is incorporated. The system control unit (SCU) 1 centrally controls the scheduling of the system bus 2 and the memory bus 3. In addition, SCU1: A) memory control, single bit
Performs error correction and double-bit error detection, and B)
Controls the memory configuration that exists one per memory unit (MU) 4, and manages the 64-byte block transfer between CPU and MU in connection with the store-in cache structure of C) central processing unit (CPU) 5. And D) corrects single bit errors found in the correction block of the CPU's cache or during data transfers from the CPU, MU or input / output unit (IOU) 6, and E) contains the system calendar clock.

The system bus 2 has 1 to 4 CPUs
And 1 to 4 IOUs are interconnected with each other and with the SCU. This system bus is a 16-byte bidirectional data interface, bidirectional address and command interface, all CPUs and IOUs.
SCU status interface monitored by
U and a few control lines between each CPU and IOU. Data is exchanged on the system bus in groups of 16, 32 or 64 bytes, exchanging data between CPU and MU, IOU and MU, two CPUs, and CPU and I.
It can occur between OUs. The various operations via the system bus 2 are as follows. Read: 16, 32 or 64 bytes-exclusive read: 64 bytes-write from IOU: 16, 32 or 64 bytes-write from CPU (swapping): 64 bytes-interrupt and connect; -read / write register Each system bus operation consists of an address phase and a data phase, which can start every two machine cycles. Consecutive 16-byte data transfers within a group can occur on consecutive machine cycles. IOU
Alternatively, the CPU can wait for up to two request data phases at the same time. The data blocks are transferred in the same order in which the requests were received.

The memory bus 3 connects 1 to 8 MUs with the SCU. This memory bus contains a 16-byte bidirectional data interface, an address and command interface from the SCU to all MUs, and a few control lines between the SCU and each MU. Data is 16, 32 or 64 bytes on the memory bus
Exchanged in groups. The operation via the memory bus 3 is as follows. Read: 16, 32 or 64 bytes Write: 16, 32 or 64 bytes Main memory consists of up to 8 MUs. (The ninth slot, MU4A, is provided to facilitate reconfiguration and repair in case of failure.) Single bit correction,
A double bit detect code is stored for every double word, ie, 8 code bits for every 72 data bits. The code is arranged so that a 4-bit error in a chip is corrected as 4 single-bit errors in 4 different words. The data in the MU is addressed from the SCU in 16 byte (4 word) increments. All bytes in any MU are addressed consecutively, ie no interlacing occurs between MUs operating in parallel. One memory cycle is a machine
Starting from every cycle and as seen by the CPU, one memory cycle is 10 machine cycles, assuming no contention with other devices. The MU4 has 160 dynamic random access memories (DRA).
M) circuits, each having n × 4 bit storage elements, where n = 256, 1024, or 4096.

Each IOU 6 has an input / output bus (IO
B) so that 7 interfaces with one IOU,
It provides a connection between the system bus 2 and two IOBs 7. Therefore, the IOU is a CSS and an I / O not shown in FIG.
Manages data transfer between O subsystems.

The clock and maintenance unit (CMU) 8 is
Generates, distributes, and tunes clock signals for all devices in the CSS, service processor (SP) 9
Interface between the central processing unit, input / output and power supply subsystem, initializes CSS devices, and
Handle errors detected in the S device. CSS is 2
A phase clock system and latched register elements are used in which the trailing edge of clock 1 defines the end of phase 1 and the trailing edge of clock 2 defines the end of phase 2 and thus each phase Is half a machine cycle.

The SP9 may be a commercially available personal computer with an integrated modem for facilitating remote maintenance and operations, with large systems two systems where the system can be dynamically reconfigured for high availability. Including SP.
This SP performs the following four functions. Monitor and control the CSS during initialization, error logging and diagnostic operations; -act as the main operating system console during system boot or at the same time as operator command; -I / O subsystem maintenance channel adapter ( MC
Acts as a console and data server for A) -provides a remote maintenance interface.

Reference is now made to FIG. 2, which is an overall block diagram of one of the CPUs 5 of FIG. The address and execution unit (AX unit) perform all address preparations and
It is a microprocessor engine that executes all instructions except binary arithmetic, binary floating point, and multiply and divide instructions.
Two identical AX chips 10, 10A perform duplicate operations in parallel, and the resulting AX chip outputs are always compared to detect errors. The main functions performed by the AX device include: -Valid and virtual address generation-memory access control-integrity check-register change / use control-basic instruction, shift instruction, integrity instruction, character manipulation, and execution of instructions. Data portion of a word) and a set of associated directory portions that define the main memory location of each 64-byte (16 word) block stored in the cache data portion.
The cache device is physically arranged in an array of 10 DT chips, one cache directory (CD) chip 12 and a copy directory (DD) chip 13.

Specific functions performed by the cache device 11 include: A combination of instruction and operand data storage-a buffer and alignment of instructions and operands-a data interface with the system bus 7 (FIG. 1) -CLIMB secure store file cache write method is "store in" i
nto) ”. If a vertical parity error is detected when reading a portion of the modified block from the cache, then this block is swapped from the cache and the SC
Corrected by U and written to main memory. The corrected block is fetched from main memory again upon retry.

Two copies of the directory information in the cache are maintained on the CD and DD chips, respectively, which implement different logical functions. The two directory copies allow concurrent querying of cache contents from the system bus without interfering with instruction / operand access from the CPU and also provide error recovery. The functions performed by the CD chip 12 include: Cache directory for CPU access management of instructions, operands and store buffers virtual-to-real address translation paging buffers The functions performed by the DD chip 13 include: -Cache directory for system access-System bus control-Distributed connection / interface management-Error recovery of cache directory Effective scientific computing power is achieved by floating point arithmetic (FP) chips 15, 15A Is realized in. The FP chip duplicates all binary floating point operations. Two
These chips, which operate in conjunction with the heavy AX chips 10, 10A, perform scalar scientific computing.

The FP chip 15 (overlapping with FP chip 15A):-performs all binary and fixed and floating point multiplication and division; -calculates a 12x72 bit partial product in one machine cycle; -Compute 8 bits of the quotient for each division cycle, -implement the remainder integrity check of the modulo 15 The functions performed by the FP chips 15, 15A include: -All floating point mantissa operations except multiplication and division-Execution of all exponential operations in binary or hexadecimal format-Preprocessing of operands and postprocessing of results for multiplication and division instructions-Provision of identifiers and state control Special purpose random access memory (FR
AM17 and XRAM18) are built into the CPU. The FRAM chip 17 is an adjunct to the FP chips 15, 15A and serves as the FP control store and decimal integer table index. The XRAM chip 18 is an adjunct to the AX chips 10, 10A, which acts as a scratch pad and provides protective store and patch functions.

The CPU also uses a clock distribution (CK) chip 16 whose functions include: Clock distribution for several chips that make up the CPU-shift path control-maintenance-interface between CMU and CPU-provide clock stop logic for error detection and recovery DN chip 14 (parallel to DN chip 14A) ) Is 10
Executes an extended instruction set (EIS) instruction. It is also a decimal binary (DTB), binary decimal (BTD) conversion EIS command, and numeric move edit (MVNE) EIS.
The instructions are executed in association with the AX chip 10. The DN chip receives the operand from the memory and sends the result via the cache device 11 to the memory.

The AX, DN and FP chips are sometimes collectively referred to as the basic processing unit (BPU). It has already been found that the AX, DN and FP chips are duplicated with a copy machine operating in parallel to obtain a copy result which can be used for protection checking. Therefore, the master and slave K
K is obtained during normal operation of these chips. The master result is the master result bus (MRB) 20.
Are placed in the slave result bus (SRB)
Placed at 21. Both master and slave results are
It is sent to the cache device 11 on the MRB and SRB, respectively. In addition, COMTO bus 22 and CO
The MFROM bus 23 connects the AX chip, the DN device and the FP device together for certain interrelated operations.

The discussion below is that cache store errors are detected in a multiprocessor system and data flow is from the cache of the first CPU to the B of the second CPU.
It concerns events that occur when going to the PU / cache. This is a more complex example of a two cache operand data error scenario and is the problem addressed by the present invention.

The preconditions that must exist for this error to occur are:

1. CPU sends data by BPU request
The block must be read into its cache. The second (or third or fourth) CPU
It still had to request the same block while it was owned by the first CPU, and one bit was changed unexpectedly while in the cache of the first CPU after this block. (Unlike one processor cache for the BPU case, it does not matter if the word in error is the target word, ie, an error in the cache block results in a siphon condition.) Having a block in error condition When the CPU (sending CPU) enters its data transfer phase in response to a siphon request, the main process for handling the error is invoked. This includes the following steps. That is, 1. The sending CPU detects an error when the requested block is read from cache storage. An error signal is also sent when the first quarter block is transferred to the requesting (receiving) CPU (data stream 28A, 28C of FIG. 3). The sending CPU specially identifies this error type and determines its cache control logic (D
A flag for reporting an error will be set on the D chip). The sending CPU's DD sets the BPU stop command to save the row and level information identifying the defective cache block in the siphon history entry of its cache history register bank. The BPU of the sending CPU is placed in a hard stop state.

2. The receiving CPU receives the error signal from the sending CPU and enters the BPU hardware stop state. This CPU sets an alarm to an error condition indicating that it has received an error signal from the sending CPU for the SP to evaluate. It also saves information about the cache storage line and level at which the block was targeted for its cache history register bank for later SP matching.

3. SCU also pays attention to the error signal,
Force the failed block into memory with bad parity (data stream 28A, 28B in FIG. 3). This results in an alarm to the SP and the page address is written to a register reserved specifically for this error type. The SCU returns a bad status signal to the sending CPU that is already in the hard stop state.

4. The SP must analyze these events, i.e. the SCU's alarm is cache set from the second CPU where the siphon error occurred.
This has to be reported because it was reported in connection with a siphon / DT error from one CPU in association with an alarm with a parity error indication. SP is
Through issuing read DD error reports to each other, line and level information regarding cache blocks in error must be retrieved from both the sending and receiving CPUs. The SP then uses this information to invalidate the block held by the receiving CPU. (SP is
This must be read to ensure that the SCU is unlocked, but it effectively ignores the SCU report. ) 5. The SP forces the correction of the erroneous cache block held by the sending CPU via the issuance of the swap command, while specifying the destination memory address of the block to be swapped. Swap results in the defective cache block being written to memory (data move 29A, 29B in FIG. 3). It is during this write that the SCU corrects the single bit failure. The SP disables the storage element of the cache associated with the failed block by invalidating that level after the swap is complete.

6. When the swap is complete, the SP must retrieve some amount of information from the sending CPU's BPU. This information is required by the operating system software as it increases the likelihood that the instruction retry routine will result in a retryable machine condition for the failing instruction.

7. The SP writes the symptom of this failure and records the receiving CPU's data in a dedicated area of main memory for use by the operating system software for later access.

8. The SP issues a failure restart command instructing the sending CPU to restart from its stopped state due to the parity failure. When the CPU restarts, it pushes its state (protected store) from XRAM 18 to cache and enters operating system software fault handling / instruction retry routines.

9. The operating system software notifies the parity accident and examines the information saved in dedicated memory to determine the type of failure. If you see that this is a cache operand error,
Operating system software evaluates the failing instruction to determine if it can be retried. The operating system software will, in some cases, send the CP acquired by the SP to set it to a pre-run state to increase the chance of successful retries.
The U register information will be used.

10. If the operating system software determines that the instruction associated with the failure can be retried, this adjusts the forced state on the protected store stack to pop up the stack entry on the sending CPU. Command to restart the faulty instruction.

11. While the operating system is performing steps 9 and 10, the SP begins the task of restarting the receiving CPU from its halted state. SP is
A certain amount of information must be retrieved from the receiving CPU's BPU. This information is required by operating system software because it increases the likelihood that the instruction retry routine will result in a retryable machine condition for a failed instruction.

12. The SP will write the symptom of the failure and the receiving CPU's register data to a dedicated storage area in main memory for use by operating system software for later access.

13. A failure restart command is issued to instruct the receiving CPU to restart from its stopped state due to a parity failure. When the receiving CPU restarts, it forces its state (protected store) from the XRAM 18 into the cache and enters operating system software fault handling / instruction retry routines.

14. Operating system software signals a parity failure and consults the information saved in dedicated memory to determine the type of failure.
When it is determined that this is a cache operand error, operating system software evaluates the failing instruction to determine if it can be retried. In some cases, the operating system software will use the receiving CPU's register information obtained by the SP to set the preliminary execution state, in order to increase the chance of good retries.

15. If the operating system software determines that the instruction associated with the failure can be retried, it adjusts the state forced on the protected store stack and instructs the receiving CPU to pop up the stack entry. The failure instruction is restarted by issuing an instruction. This restart will result in the corrected block being fetched from main memory (FIG. 3, data move 30A, 30B). The net result is that the affected process is restarted and completely transparent to the error.

If the second or third CPU requests the same block and receives an error signal from the sending CPU, steps 11 to 15 above are repeated for each such receiving CPU.

The responsiveness separation between the CPU, SP and operating system software is an important consideration in the illustrated configuration, and a determination is made first regarding absolute need and then for component strength. It was

Moderate support had to be configured to provide the following functionality to the hardware of the exemplary system. That is, A) error detection B) provision of information about the error (related cache
(Including block identification) C) Freeze (stop) BPU affected by predictable method D) Alarm to SP E) Support directive for 1) Swap cache block 2) Disable cache block (Alternatively, a large cache subdivision such as the level on the example machine) 3) CPU restart, and F) Continuing service system requests throughout error handling (to avoid system downtime) First, CPU hardware Seemed to have to be designed to handle all these roles without SP intervention8. That is, ideally, the CPU itself would automatically swap the block into memory for correction, retrieve the corrected block, and restart the affected instruction. However, those of ordinary skill in the art will appreciate that such attempts are fraught with potential for design error and consume much of the source of system design effort (ie, designer time and silicon space). . By sharing the responsibility among the CPU, SP and operating system software, the entire exemplary system in terms of commercial implementation and development efforts of the hardware (design / implementation responsibility is not concentrated on one key person). Design, development and production costs have been significantly reduced. Furthermore, those skilled in the art will readily appreciate that if bugs are discovered during early system testing, it is easier to modify the software than to create a new version of the hardware VLSI component. This additional flexibility
It gives the segmented approach the advantage over concentrating the process on silicon.

The SP's responsibilities include: That is, A) alarm processing B) monitoring error processing and correction including the following: 1) issuing a command to determine blocks to be swapped 2) issuing a command to swap blocks in error 3) processing exceptions that occur during swapping, ie If the error is unrecoverable (eg double bit failure), the SP is programmed to send this information / state to the operating system C) Instruction retry software affected BP
Derive registers from U D) Ensure that CPU is in flexibility j, which can be restarted via issuance of instructions to execute accordingly SP's responsibility is whether the instruction associated with the failure can be retried It will be understood that the judgment is not included. Several factors prohibit doing this. First, the algorithms required to determine if some of the more complex instructions in the CPU assembly limited instruction set are retryable are very complex (which translates to very large programs). It was determined that no further storage requests should be made to the SP due to expected storage capacity limitations. In addition, the SP is slow compared to the mainframe computers it supports, so this process is much more powerful if retry software is present on the mainframe.

Operating system software responsibility is primarily responsible for determining whether the affected instruction is retryable. This functionality is possible after the affected CPU has been delayed for failure. The operating system software interprets the failure type, and when it is determined that this is the type of error for which the invention is intended, the software enters its parity failure handling procedure.

The analysis that operating system software must perform to determine if an instruction can be retried depends on the type of instruction that failed.
Substantially, the exemplary CPU supports an assembly language instruction set consisting of the following instructions. 1) Load register from cache 2) Write to cache 3) Modify register 4) Read and modify for the same cache word,
Then write 5) move cache data from one place to another, and / or 6) transfer control The operating system software retry component analyzes these types of instructions , Determine if a given instruction can be retried in a given situation. In particular, this looks like a very simple task. For example, if a simple "Load A-Register (LDA)" instruction fails because the data received during the siphon has bad parity, the LDA can be re-executed following the correction of the cache block. Expected to be. However, as a mere example, consider what happens if the LDA has an indirect and associated tally effective address modification. Therefore, the operating
The system software detects this situation and
The word must be restored to its preliminary execution state.
This LDA example is presented to show the well-known fact that it is an expectation for an instruction set that complicates the retry algorithm.

In this example system, the hardware provides some important support for recovering from these errors. This hardware finds the pre-run value for a register and provides shadowing behavior for that register so that it can be used for retries. This truly complex case (eg, double precision arithmetic) benefits the most from this shadowing operation. In such complex cases, operating system software can determine where pre-execution registers are located and use these registers for retry. The shadow operation can effectively optimize instructions that modify registers even when invalid data is read, to the extent that the operation completes, because a preliminary execution copy of the register is available for retries. Is. Without this feature, these instructions are considered non-retryable or C
The execution of the PU will have to be slowed down to ensure that the operation is canceled when invalid data is detected.

When the instruction can be retried, the operating system software returns control to the affected process, which is apparent from the hardware error. If the instruction is not retryable or the cache block failure is uncorrectable, the affected process is terminated.

Attention is now directed to the flow diagram of FIG. This flow diagram is another disclosure of the invention that is particularly useful to a programmer in implementing the invention in an environment similar to that of the exemplary system.

While the principles of the present invention have been clarified in the examples, those skilled in the art will appreciate that structures used in the practice of the invention that are particularly adapted to the particular environment and operating requirements without departing from this principle, Many variations in arrangement, proportions, elements, materials and components will be apparent.

[Brief description of drawings]

FIG. 1 is a very high level block diagram showing the central system structure of an information handling system in which the present invention has application.

FIG. 2 is an overall block diagram showing a central processing unit of the central system structure of FIG.

FIG. 3 is a block diagram similar to FIG. 1 showing certain data movements that occur during practice of the invention.

FIG. 4 is a flow chart of implementing another embodiment of the present invention.

[Explanation of symbols]

 1 system control unit (SCU) 2 system bus 3 memory bus 4 memory unit (MU) 5 central processing unit (CPU) 6 input / output unit (IOU) 7 input / output bus (IOB) 8 clock and maintenance unit (CMU) 9 Service Processor (SP) 10 AX Chip 11 Cache Device 12 Cache Directory (CD) Chip 13 Copy Directory (DD) Chip 14 DN Chip 15 Floating Point Arithmetic (FP) Chip 16 Clock Distribution (CK) Chip 17 FRAM Chip 18 XRAM chip 20 Master result bus (MRB) 21 Slave result bus (SRB) 22 COMTO bus 23 COMFROM bus 33 Cache storage device 34 Error detection device

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor William A. Shelley 85,018 Arizona, USA, East Osborne Road, 4900 (72) Inventor, Jee Chan, 85023, Arizona, USA, Phoenix, North. Thirty Farst Drive 15620 (72) Inventor Minor Inosita 85302, Arizona, USA, West Golden Lane, 5302 Glendale, 5332 (72) Inventor Leonard G. Torbiski, Arizona, USA 85253, Scottsdale, East Horse Shoe Lane 6725 (56) Reference JP-A-1-88676 (JP, A) JP-A-2-17550 (JP, A)

Claims (7)

(57) [Claims] 1. A fault tolerant multiprocessor computer system comprising: A) a first central processing unit including a first cache memory device, the first cache memory device comprising: Cache storage means, and (b) the first
Cache read parity error which is a parity error in the block of information read from the first cache storage means, and a cache write parity error which is a parity error in the block of information written to the first cache storage means. And a first parity error detecting means for issuing a first error flag when the cache write parity error is detected. A second central processing unit including a first central processing unit and B) a second cache memory unit, wherein the second cache memory unit is (a) second cache storage means. And (b) a parity error in the block of information read from the second cache storage means. A second parity error detecting means for detecting a cache read parity error which is a parity error in a block of information written to the second cache storage means. , When the cache read parity error is detected, the second
Second central processing unit for issuing an error flag of the second central processing unit, and C) in response to a siphon request from the first central processing unit. Transfer means for transferring a designated block of information from the cache storage means of the above to the first central processing unit via the first and second parity error detecting means, and D) performing parity error correction. A system controller having a parity error correction device; E) a system bus connecting the first and second central processing units to the system controller; F) a main memory device; G) the system control A memory bus connecting the device and the main memory device, and H) from the second central processing unit requested by the first central processing unit during siphon operation. In fault block distribution of the block, said second parity error detection means detecting a cache read parity error by, and in response to detection of a cache write parity error by said first parity error detection means,
The defective block is corrected from the second cache storage means via the system control unit and transferred to the main memory unit, and the corrected block is transferred from the main memory unit to the first central processing unit. Error recovery control means for transferring to the system control device for detecting the first and second error flags and correcting the faulty block from the second cache storage means in accordance therewith. A fault tolerant multiprocessor computer system comprising: an error recovery control means including a service processor that directs the transfer to the main memory device via the. 2. The fault tolerant multiprocessor computer system of claim 1, wherein each of the first and second central processing units further comprises: A) random access memory; and B) from the service processor. In response to the command of
Prior to retrying the operation resulting in the issuance of the first and second error flags, the random
A fault tolerant multiprocessor computer system including means for pushing protected store information to access memory. 3. The fault tolerant multiprocessor computer system according to claim 1, wherein said error recovery control means further comprises: A) operating system software including an instruction retry routine; and B) said instruction replay. In a trial routine, the presence of the first and second error flags is detected, the presence of the flag and the failure block having been previously transferred from the second cache storage means to the main memory device. Responsive to command a retry of the operation resulting in the issuance of the first and second error flags,
And means for directing the transfer of the corrected block from the main memory unit to the first central processing unit, the fault tolerant multiprocessor computer system. 4. A fault tolerant computer system comprising: A) a central processing unit comprising a cache memory device, a basic processing device, and a transfer means, wherein the cache memory device comprises: (a) cache storage means; b) first parity error detection means for detecting a parity error in a block of information read from the cache storage means, the first error flag being set when the parity error is detected. A first parity error detecting means including means for issuing; and the basic processing device for detecting a parity error in a block of information written from the cache storage means to the basic processing device. A parity error detecting means, wherein the second error flag is detected when the parity error is detected. Second parity error detecting means, including means for issuing a group, wherein the transfer means transfers the block of information read from the cache storage means via the second parity error detecting means. A central processing unit configured to transfer data to the basic processing unit by means of B, a system control unit including B) parity error correction means for performing parity error correction, and C) the central processing unit and the system control unit. A) a system bus connecting D., a) a main memory device, E) a memory bus connecting the system controller and the main memory device, and F. a block of information requested by the basic processing unit. In response to the detection of a parity error by both the first and second parity error detection means in the failed block, the cache Error recovery control means for correcting the defective block from the storage means and transferring the corrected block to the main memory device via the system control device, and transferring the corrected block from the main memory device to the central processing unit. And detecting the first and second error flags and, in response thereto, transferring the failed block from the cache storage means to the main memory device via the system controller for error correction. A fault tolerant computer system comprising: an error recovery control means including a commanding service processor. 5. The fault tolerant computer system of claim 4, wherein said central processing unit further comprises: A) random access memory; and B) in response to instructions from said service processor,
Prior to retrying the operation resulting in the issuance of the first and second error flags, the random
A fault tolerant computer system, including means for pushing protected store information to access memory. 6. The fault tolerant computer system of claim 4 or 5, wherein said error recovery control means further comprises: A) operating system software including an instruction retry routine; and B) in said instruction retry routine. Detecting the presence of the first and second error flags and responding to the presence of the flag and the previous transfer of the failed block from the cache storage means to the main memory device. Means for commanding the retry of the operation resulting in the issuance of first and second error flags and for commanding the transfer of the corrected block from the main memory device to the central processing unit. A fault-tolerant computer system. 7. The fault-tolerant computer system according to claim 4, 5, or 6, wherein the corrected block is returned to and stored in a different block position from the faulty block in the cache storage means. Features a fault-tolerant computer system.