JP2564856B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a semiconductor device formed by epitaxially growing a gallium arsenide (GaAs) compound semiconductor on a silicon substrate.

[Prior art]

Conventionally, gallium arsenide (GaAs) -based III-V compound semiconductors have a high mobility, a direct transition type band structure, a ternary or quaternary structure.
Due to properties such as band gap and variability of lattice constant due to original compound, Hall element, high speed transistor, laser diode, light emitting diode, phototransistor,
Attention is paid to photodiodes, solar cells, and ICs of these elements. However, since a large-diameter single crystal gallium arsenide (GaAs) wafer cannot be easily obtained, there is a problem that the manufacturing cost of the gallium arsenide (GaAs) -based compound semiconductor is high. In addition, sensors such as Hall elements are integrated into the same chip along with the Hall element section for the peripheral circuits for magnetic detection.
IC is preferable for use.

[Problems to be Solved by the Invention]

However, when the magnetic detection part is formed of silicon, there is a problem that the hole mobility and the product sensitivity are small and the unbalance ratio is large because the hole mobility is small. Therefore, an inexpensive IC can be manufactured by using gallium arsenide (GaAs) having a high mobility as a magnetic detection part and forming other peripheral circuits with silicon to compound the materials. However, it is difficult to grow gallium arsenide having good crystallinity on a silicon substrate because the misfit of the lattice constant between silicon and gallium arsenide is large. The present inventors have found that when gallium arsenide is grown directly on a silicon substrate, it is 0.5 μm to 1 μm from the interface with silicon.
It was discovered that the lattice defects are concentrated in the range of and the carrier concentration near the interface between GaAs and Si increases. When the carrier concentration near the interface where the lattice defects are concentrated becomes large, the current is concentrated at that portion, so that the high mobility of gallium arsenide cannot be effectively used in the operation layer of gallium arsenide epitaxially grown on the silicon substrate. Occurs. The present invention has been made to solve the above problems, and an object of the present invention is to improve the characteristics of a semiconductor element using gallium arsenide (GaAs) formed on a silicon substrate as an operating layer. It is to be.

[Means for solving problems]

The structure of the invention for solving the above problems is a buffer layer made of gallium arsenide (GaAs) formed on a silicon (Si) substrate, and gallium arsenide (GaAs) formed on the buffer layer and functioning as a semiconductor element. Provided between the operating layer made of GaAs), the buffer layer, and the operating layer,
Conductivity that electrically insulates the buffer layer and (a) forms a potential barrier against the gallium arsenide (GaAs) of the operating layer (a) gallium aluminum arsenide (Al _x Ga _1-x As). Type (a), (b), (c), (d) of a superlattice containing gallium arsenide (GaAs), (c) zinc selenide (ZnSe), and (d) gallium arsenide (GaAs) And a single insulating layer. The superlattice containing gallium arsenide (GaAs) is made of gallium arsenide (GaAs), aluminum arsenide (AlAs), gallium aluminum arsenide (AlGaAs), gallium indium arsenide (InGaAs), or indium arsenide (InAs). Superlattices can be used. The operating layer made of gallium arsenide (GaAs) is, for example, a Hall element, or the silicon (Si) substrate is provided with a drive circuit for driving a semiconductor element including the operating layer or a signal output from the semiconductor element. A signal processing circuit for processing may be formed. The total thickness of the buffer layer and the insulating layer is not less than the thickness at which dislocations generated at the interface terminate, and is preferably 1 μm to 3.5 μm. Gallium arsenide (GaAs) directly epitaxially grown on silicon
Since the lattice defect of (1) extends from the interface with silicon to about 1 μm, if the operating layer of gallium arsenide (GaAs) is formed at a position 1 μm away from the interface, the lattice defect does not reach the operating layer. On the other hand, when the thickness is 3.5 μm or more, cracks are likely to occur due to the difference in coefficient of thermal expansion with silicon.

【The invention's effect】

The present invention insulates an operating layer made of gallium arsenide (GaAs) on a buffer layer made of gallium arsenide (GaAs) formed on a silicon substrate and gallium arsenide (Ga).
Since the insulating layer that can be made into a single crystal (As) is formed, the high carrier concentration portion formed at the interface between the buffer layer and the silicon substrate can be insulated from the semiconductor element including the operating layer, and the performance of the element can be improved. Can be improved or integrated.

【Example】

First Embodiment This embodiment relates to a Hall IC. As shown in FIG. 2, the circuit configuration of the Hall IC 1 is composed of a constant voltage power supply circuit 30, a Hall element section 10 and a waveform shaping circuit 40. The Hall element section 10 includes an operating layer 11 made of gallium arsenide (GaAs) that serves as a magnetic detection layer and a current electrode.
28a, 28b and output electrodes 29a, 29b, and is supplied from the constant voltage power supply circuit 30 to the operating layer 11 made of GaAs via the current electrodes 28a, 28b, and a detection signal corresponding to the detected magnetic amount. Is output to the waveform shaping circuit 40 via the output electrodes 29a and 29b. The constant voltage power supply circuit 30 of the Hall IC 1 is supplied with power from the battery 2, and the detected signal is output from the waveform shaping circuit 40 of the Hall IC 1 to the electronic control unit 3. The sectional structure of the Hall IC 1 is shown in FIG. The Hall IC 1 is formed on the P-Si substrate 20, and the constant voltage power supply circuit 30 and the waveform shaping circuit 40 are manufactured by a normal Si IC manufacturing technique. That is, the N ⁺ buried layer 24 is formed on the surface of the P-Si substrate 20 by the buried diffusion, and then N ⁻ -Si is epitaxially grown on the surface of the P-Si substrate 20 and is locally formed in the epitaxial layer for element isolation. manner by diffusing P-type impurity, an island-shaped N ^-
The -Si layer 25 and the P-Si layer 22 of the separation layer are formed. After that, depending on the element to be created, the island-shaped N ^-- Si layer 25 may be P-type,
By diffusing N-type impurities, the PNP transistor 31, the NPN transistor 32, the MOS capacitor 33, etc. of the elements constituting the constant voltage power supply circuit 30 or the waveform shaping circuit 40 are formed. Incidentally, 34 is SiO ₂
And 35 is an Al electrode. Next, the configuration of the Hall element unit 10 will be described. The main surface of the P-Si substrate 20 is <0 with respect to the (100) plane.
A single crystal tilted by 4 ° ± 1 ° in the 11> direction is used. Then, on the P-Si layer 22 epitaxially grown on the P-Si substrate 20, a buffer layer 13 made of GaAs is formed.
Is formed with a thickness of 0.5 μm, and an insulating layer 12 made of gallium aluminum arsenide (Al _0.3 Ga _0.7 As) is formed with a thickness of 0.5 μm.
m-thick operating layer made of N-GaAs
11 (in this embodiment, this operation layer 11 serves as a magnetic sensing layer of a Hall element) is formed to a thickness of 1.5 μm, and N ⁻ -GaAs layers 15a and 15b are formed on the electrode portion thereon. Au / Ni / Au− on top
Current electrodes 28a and 28b made of Ge are formed. Each of these layers is formed by metalorganic pyrolysis vapor deposition (MOCV).
According to D), it was formed by sequentially and continuously performing epitaxial growth. Trimethylgallium (TMGa, G
a (CH ₃ ) ₃ ), trimethylaluminum (TMAl.Al (C
H ₃ ) ₃ ) and hydrogen diluted arsine (AsH ₃ ) were used. Again n
SiH ₄ diluted with hydrogen was used as the type dopant. The flow rates of these gases are accurately controlled by a flow rate control device so that a constant crystal growth rate is obtained, and the growth rate is controlled.
It was 4.3 μm / h. The growth temperature was 750 ° C. P-Si
To grow a buffer layer of GaAs on layer 22, 45
A two-step growth method was used in which a GaAs layer having a thickness of about 200Å was grown at 0 ° C and then main growth was performed at 750 ° C. In this way, the Hall element part 10 is composed of a GaAs-based semiconductor epitaxially grown on the P-Si substrate 20, and the other peripheral circuits are composed of Si semiconductors formed on the same P-Si substrate 20. Hall IC was obtained. This Hall IC is GaAs
It showed the same characteristics as those composed only of semiconductors of the system. Further, in order to confirm the effect of the insulating layer 12 made of Al _0.3 Ga _0.7 As according to the characteristic part of the present embodiment, the hole mobility of the operating layer 11 made of N-GaAs in the Hall element portion 10 and Al _0.3 Ga.
The hole mobility of the N-GaAs layer directly epitaxially grown on the P-Si substrate without the interposition of the insulating layer 12 of _0.7 As was measured. As a result, as it can be understood from FIG. 3, the Hall mobility with insulating layer 12 who is interposed an insulating layer 12 made of Al _0.3 Ga _0.7 As of the present embodiment is made of Al _0.3 Ga _0.7 As It turns out that it is about 1.6 times larger than the case without it. As a result, the detection sensitivity as a Hall element is also _0.3 G
It is 1.6 times larger when the insulating layer 12 made of a _0.7 As is interposed than when the insulating layer 12 is not interposed. In addition, N directly grown epitaxially on the P-Si substrate
− As a result of observing the cross section of the GaAs layer with a microscope,
It was found that a large number of metastases occurred in the range of 0.5 to 1.0 μm. From this fact, the buffer layer 13 made of GaAs and the Al layer are made to the extent that this transition does not reach the operating layer 11 made of N-GaAs.
It can be seen that it is desirable to set the total thickness of the insulating layer 12 made of _0.3 Ga _0.7 As to 1 μm or more. In addition, N directly grown epitaxially on the P-Si substrate
-The relationship between the carrier density of the GaAs layer and the distance from the interface with Si was measured. The results are shown in FIG. From this, the carrier density of the N-GaAs layer is 1 near the interface with Si.
× 10 ¹⁹ cm ^-3 , the maximum, 0.75 from the interface to the N-GaAs layer side
It can be seen that at μm it is 4 × 10 ¹⁶ cm ^-3, which is the same as near the surface. Therefore, the carrier density of the N-GaAs layer is about two orders of magnitude higher in the vicinity of the interface with Si than in the vicinity of the surface. As a result, when the N-GaAs layer directly epitaxially grown on the P-Si substrate is used as a Hall element, it is revealed that the high mobility of GaAs cannot be effectively used because the current concentrates near the interface. . Therefore, in this embodiment, the insulating layer 12 made of Al _0.3 Ga _0.7 As is used.
Is a buffer layer 13 made of GaAs and N− as a Hall element.
By interposing it between the GaAs layers 11, the high carrier density region near the interface is insulated from the N-GaAs layer 11 to improve the sensitivity of the Hall element. Although the mixed crystal ratio x of the insulating layer 12 made of Al _x Ga _1-x As is set to 0.3 in the above-mentioned embodiment, the value of the mixed crystal ratio x makes the epitaxial growth of the N-GaAs layer 11 good and maintains the insulating property. What is necessary is just to do, and it is possible to use it in the range of 0 <X <1. Second Embodiment In the first embodiment, the insulating layer 12 made of Al _0.3 Ga _0.7 As is used in the process of epitaxial growth by MOCVD.
Instead of forming P, a P-GaAs layer may be formed to a thickness of about 1 μm using diethylzinc (DEZn) as a P-type dopant, and an operating layer 11 composed of an N-GaAs layer may be formed thereon. . In this case, the operating layer 11 is a buffer layer by PN junction.
The same GaAs layer is insulated from the buffer layer 13
The crystallinity of the operating layer 11 is good because it is grown sequentially from
The same effect as that of the first embodiment was obtained. Third Embodiment In the first embodiment, the insulating layer 12 made of Al _0.3 Ga _0.7 As is used in the process of epitaxially growing by MOCVD.
Instead of forming, a ZnSe layer was epitaxially grown. ZnSe has good lattice matching with GaAs and has a forbidden band width.
Since it is as wide as 2.6 eV, it has good insulation properties for the buffer layer 13,
The same effect as in the first embodiment was obtained. Fourth Embodiment In the first embodiment, the insulating layer 12 made of Al _0.3 Ga _0.7 As is used in the process of epitaxially growing by MOCVD.
Instead of forming, a superlattice of AlAs and GaAs was laminated to form an insulating layer. This Hall IC also produced the same effect as in the first embodiment. Fifth Embodiment This embodiment shows a solar cell IC, the sectional structure of which is shown in FIG. The same functional parts as those in the first embodiment are designated by the same reference numerals. An operating layer made of an N-GaAs layer as in the first embodiment.
11 is formed, and then an operating layer 11 made of an N-GaAs layer is formed.
A P-GaAs layer 14 is formed by using a P-type dopant in a part of the P-GaAs layer 14, and an electrode layer 16b made of N ⁺ -GaAs is joined to the operating layer 11 made of an N-GaAs layer. An electrode layer 16a made of a P ⁺ -GaAs layer is bonded to the. The other peripheral circuits are the same as in the first embodiment. In this case, the operating layer 11 made of the N-GaAs layer and the P-GaAs layer 14 form a solar cell semiconductor element. The solar cell IC manufactured in this way showed good characteristics. In addition to the various embodiments described above, a double heterojunction layer of a GaAs-based semiconductor is similarly formed on the operating layer 11 made of an N-GaAs layer to form a laser diode or the like, and its drive circuit is used as a peripheral circuit on the same Si substrate. It may be formed on top. In the above embodiment, GaAs or the like is epitaxially grown using the epitaxially grown P-Si layer 22 as a Si substrate in order to form an IC by combining with other functional elements. However, GaAs or the like is epitaxially grown on the original single crystal Si substrate. You may.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to a specific embodiment of the present invention, FIG. 2 is a block diagram showing its functional structure, and FIG. 3 is a hole mobility measurement diagram. FIG. 4 is a measurement diagram of carrier density distribution, and FIG. 5 is a sectional view showing a semiconductor device according to another embodiment. 1 ...... Hall IC, 2 ...... battery, 3 ...... electronic control unit, 10 ...... Hall element unit, 11 ...... Operation layer, 12 ...... insulating layer, 13 ...... buffer layer, 15a, 15b ...... N ^- -GaAs layer, 20 ...
... P-Si substrate, 28a, 28b ... Current electrode, 22 ... P-Si
Layer, 24 …… N ⁺ buried layer, 25 …… N ^-- Si layer, 31 …… PNP transistor, 32 …… NPN transistor, 32,33 …… MOS capacitance, 34 …… protective film, 35 …… Al Electrodes, 30 ... Constant voltage power supply circuit, 40 ... Waveform shaping circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01S 3/18 H01L 31/04 E

Claims (6)

(57) [Claims] 1. A buffer layer made of gallium arsenide (GaAs) formed on a silicon (Si) substrate, and an operation layer made of gallium arsenide (GaAs) formed on this buffer layer and functioning as a semiconductor element. It is provided between the buffer layer and the operating layer, electrically insulates the buffer layer, and (a) gallium aluminum arsenide (Al _x Ga _1-x A
s), (b) conductive type gallium arsenide (GaAs) forming a potential barrier against the gallium arsenide (GaAs) in the operating layer, (c) zinc selenide (ZnSe), (d) gallium arsenide (GaAs) An insulating layer formed of any one of (a), (b), (c), and (d) in a superlattice containing (1). 2. The semiconductor according to claim 1, wherein the superlattice containing gallium arsenide (GaAs) is a superlattice made of a compound semiconductor containing gallium arsenide (GaAs) and gallium or arsenic. apparatus. 3. A compound semiconductor containing the gallium or arsenic.
The semiconductor device according to claim 2, wherein the semiconductor device is made of AlAs, AlGaAs, InGaAs, InAs. 4. The semiconductor device according to claim 1, wherein the operating layer made of gallium arsenide (GaAs) constitutes a Hall element. 5. A drive circuit for driving a semiconductor element including the operation layer or a signal processing circuit for processing a signal output from the semiconductor element is formed on the silicon (Si) substrate. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 1, wherein a total thickness of the buffer layer and the insulating layer is equal to or larger than a thickness at which dislocations generated from an interface terminate.