JP2562735B2 - Waveform equalization LSI and video signal receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is a ghost canceler.
(GCR) and waveform equalization LSI used for waveform equalization of MUSE signals, and a video signal receiver using the same.

[0002]

2. Description of the Related Art As a technique for band-compressing a high-definition video signal, a multiple sub-Nyquist sampling encoding method
(MUSE method) (Multiple Sub-Nyquist Sampling Encod
ing) was developed by NHK (Japan Broadcasting Corporation), and is regularly broadcast by satellite broadcasting.

[0003] The MUSE system is a 1-channel satellite bandwidth 27MH _Z, a band compression method for transmitting high-definition video signal. In the MUSE system, a high-definition video signal bandwidth compression ene - into a band compressed signal bandwidth 8.1MH _Z performs sub-Nyquist sampled rig treated with da.

The MUSE system is introduced in the following literature.

(A) NHK technology research 1987 Vol. 39 No. 2
Issue No. 172 No. 18 (76)-53 (111) Ninomiya, Otsuka, Izumi,
Koshi, Iwadate, "Development of MUSE method" (B) Nikkei McGraw-Hill's magazine "Nikkei Electronics, November 2, 1987, No.433," pages 189-212, Ninomiya, "Hi-Vision using satellites" Broadcast transmission system MUS
E] The waveform equalization of the MUSE signal will be described.

A training signal for waveform equalization is added to the MUSE signal on the transmitting side in advance.

This training signal is a VIT signal (Ver
tical Interval Test Signal) (On the VI receiver side, this M
After converting the USE signal from analog to digital, VIT
The characteristics of the transmission line are equalized by taking in the response waveform of the signal and manipulating the characteristics of the equalization filter on the receiving side so that the error from the ideal impulse response is reduced.

A waveform equalizer for MUSE signals is described in "1989
Proceedings of IEICE Spring National Congress, Volume 3
3-290 Lecture No. B-584 ”.

An outline of a conventional MUSE signal receiver for waveform equalization will be briefly described with reference to FIG.

(10) is an input terminal to which the transmitted MUSE signal is input.

(12) is an A / D converter.

(14) is a PLL synchronous clock circuit. This PLL synchronous clock circuit (14) creates a 16.2 MHz resample clock. A 32.4 MHz resample clock for performing highly accurate waveform equalization may be created. Also, this PLL synchronous clock circuit (14)
Outputs a frame pulse (FP) and a line pulse (HP). This frame pulse and line pulse are the circuit (2
8) Used for timing control in (32).

(15) is a transversal filter (hereinafter,
It is called TVF).

(16) is a waveform equalizing LSI.

(16a) is a clock signal input terminal.

(16b) is a digital video signal input terminal.

(16c) is a digital video signal output terminal.

(16d) is a tap coefficient input terminal.

The above-mentioned TVF (15) comprises a delay circuit (18) for delaying a video signal by a clock signal and an arithmetic circuit (20).
Prepare This delay circuit (18) consists of four data latch circuits.
(22-22). The arithmetic circuit (20) includes five multipliers (24-24) and an adder (26).

Reference numeral (28) is a VIT memory for storing video signal data in the VIT signal period of the output signal from the TVF (15). The storage operation timing of the VIT memory (28) is controlled by the frame pulse and the line pulse.

(30) is an equalization arithmetic processing circuit composed of a microcomputer. This equalization processing circuit (30)
Pre-stored ideal VIT signal data and VI
The data read from the T memory (28) is compared and operated to derive each tap coefficient of the multipliers (24-24) of the TVF (15) for equalization. Each of the multipliers (24 to 24) multiplies the tap coefficient by the output from the equalization arithmetic processing circuit (30).

(32) is a MUSE signal processing circuit,
Processing for converting a USE signal into a high-definition signal is performed.

In order to simplify the explanation, the TVF (15) of this conventional example is a 5-tap filter.
For E signals, at least 33 taps are required. In the case of GCR, 100 to 200 taps are required, so several waveform equalizing LSIs are connected in series.

The above operation will be described.

The MUSE signal which is distorted in the transmission line is
Input from the input terminal (10), AD converter (12), TVF (1
Distortion is removed via 5) and the MUSE signal processing circuit
Output to (32).

Further, the VI of the output of the equalizing LSI (16)
The T signal portion is stored in the VIT memory (26). In addition, VI
The T memory (26) stores most of the horizontal scanning period in which the VIT signal is inserted for waveform equalization, and the data of the stored VIT signal is input to the equalization arithmetic processing circuit (30). Then, the error is obtained, and each tap coefficient is calculated by the equalization algorithm. Then, the tap coefficient value thus derived is output to each of the multipliers (22 to 22).

In this way, the equalization processing of the MUSE signal is performed.

[0028]

By the way, TVF (15)
The operation timing of the circuit (28, 32) in the subsequent stage is the frame pulse (FP) output from the PLL synchronous clock circuit (14).
And the line pulse (HP).

By the way, the TVF (15) delays the video signal, which is a matter of course.

Therefore, when designing the equipment, first,
If the TVF (15) does not determine how much the video signal is delayed, as shown in FIG. 2, the adjustment variable delay circuit (3) for delaying the frame pulse and the line pulse in accordance with the video signal.
4, 36) are required.

For example, in order to expand the range of waveform equalization,
If two equalization LSIs (16) are connected and the number of taps is doubled, the delay time is doubled. Also, 16.2MHz is T
When the delay circuit (18) is controlled by inputting it to the terminal (16a) as a clock signal of VF (15), TVF is set to 32.4MHz.
Compared with the case of using the clock signal of (15), the delay time is 2
Double. Furthermore, designing a waveform equalizer capable of switching the clock frequency between 16.2 MHz and 32.4 MHz becomes more complicated.

If the designer of the video signal receiver does not preset the frequency of the clock signal used in the waveform equalization process and the number of equalization LSIs to be used, the adjustment variable delay circuit shown in FIG. At (34,46), the amount of delay of the sync signal must be adjusted.

As described above, the designer of the video signal receiver adjusts according to the change in the delay time of the video signal in the waveform equalization processing.
A circuit that adjusts the delay of synchronizing signals such as frame pulses (34,
46) also has to be designed.

The designer wants to freely select the clock frequency, the number of LSIs used, and the like in the waveform equalization processing. However, the designer does not want to consider the delay adjustment of the synchronization signal.

In other words, in the waveform equalization processing, it suffices to automatically delay the synchronizing signal such as the frame pulse according to the clock frequency used, the number of LSIs, and the like.

According to the present invention, even if the frequency of the clock signal for waveform equalization processing and the number of equalization LSIs are changed,
The present invention provides an equalizing LSI in which the designer does not have to consider the delay adjustment of the synchronization signal.

[0037]

Means for Solving the Problems Equalization LSI of the present invention
Incorporates a delay circuit (400, 420) for synchronizing signal which delays the synchronizing signal (frame pulse, line pulse). And
The same clock signal as the clock signal for delaying the video signal for waveform equalization is supplied to the synchronization signal delay circuit (400, 420).

Further, the video signal receiver of the present invention uses the equalization L which has the same timing as the equalized video signal.
It is characterized in that it is provided with a post-stage circuit (28, 32) whose timing is controlled by using a delay synchronizing signal from SI (38, 40).

[0039]

In the present invention, since the synchronizing signal (frame pulse, line pulse) is delayed by the same clock signal as the video signal, the delay phases of the video signal and the synchronizing signal coincide with each other.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. Note that, in FIG. 3, the same parts as those in FIG.

In FIG. 3, reference numeral (38) is a waveform equalizing LSI.

Reference numeral (38a) is a clock signal input terminal.

(38b) is a digital video signal input terminal.

(38c) is a digital video signal output terminal.

(38d) is a tap coefficient input terminal.

(38e) is a frame pulse input terminal.

Reference numeral (38f) is a line pulse input terminal.

(38g) is a frame pulse output terminal.

(38h) is a line pulse output terminal.

(400) is a frame pulse delay circuit, which is composed of two latch circuits (not shown). The frame pulse delay circuit (400) is supplied with the clock signal supplied to the TVF (15) from the terminal (38a).

Reference numeral (420) is a line pulse delay circuit, which comprises two latch circuits (not shown). This line pulse delay circuit (420) also has a TVF (15) from the terminal (38a).
The clock signal is supplied to the.

The number of taps of the TVF (15) in FIG. 3 is 5 as in the TVF (15) of FIGS. 1 and 2, and the number of latch circuits is 4. That is, the delay time of the video signal of the TVF (15) is the number of delay latch circuits / 2 × 1 cycle of the clock signal = 4 pieces / 2 × 1 cycle of the clock signal.

The delay time of the synchronizing signal in the synchronizing signal delay circuit (400, 420) is the number of delay latch circuits × 1 cycle of the clock signal = 2 pieces × 1 cycle of the clock signal.

That is, if the number of latch circuits of the delay circuits (400) (420) is selected to be half the number of latch circuits of the TVF (15), the terminal (3
The phase timing relationship between the video signal input to 8b) and the synchronization signal input to terminals (38e) and (38f) is the same as the video signal output from terminal (38c) and the output from terminals (38g) (38h). And the phase timing relationship with the sync signal.

A second embodiment of the present invention will be described with reference to FIG. Note that, in FIG. 4, the same parts as those in FIG.

In the example of FIG. 4, the VIT memory (28) is equalized to L
This is an example integrated with SI (40).

Reference numeral (40) is an LSI for waveform equalization. (40a)
Is a clock signal input terminal. (40b) is a digital video signal input terminal. (40c) is a digital video signal output terminal. (40d) is a tap coefficient input terminal. (40e) is a frame pulse input terminal. (40f)
Is a line pulse input terminal. (40g) is a frame pulse output terminal. (40h) is a line pulse output terminal.

Reference numeral (40i) is an output terminal for outputting the data of the VIT signal stored in the VIT memory (28).

A third embodiment of the present invention will be described with reference to FIG. In FIG. 5, the same parts as those in FIGS.

(30 ') is an equalization arithmetic processing circuit. This equalization arithmetic processing circuit (30 ') and the equalization arithmetic processing circuit (3'
The difference from 0) is that the number of waveform equalization LSIs (40) increases, and the number of tap coefficients to be calculated and calculated is doubled.

In the above embodiment, the delay circuits (400) (420)
The number of the latch circuits is selected to be half the number of the latch circuits of the TVF (15), because the center tap output normally corresponds to the delay of the video signal in the waveform equalization processing. Therefore, for the video signal receiver whose video signal delay is not always the center tap output, a plurality of delay sync signal output terminals for outputting a plurality of delay sync signals from different taps of the sync signal delay circuit are provided, You may make it select at the time of use. Alternatively, the arithmetic circuit (20) is designed to output the delay selection signal together with the tap coefficient, and one of the plurality of delay synchronizing signals from the different taps is selected by the delay selection signal to delay the delay. It may be output from the sync signal output terminal.

[0062]

According to the present invention, the synchronizing signal (in the case of MUSE signal, for example, frame pulse, line pulse) is delayed by the same clock signal as the video signal.
Since the phases of the video signal and the sync signal are constant, it is not necessary to newly provide a sync signal delay adjustment circuit that matches the delay of the video signal generated in the waveform equalization processing.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional video signal receiver with a waveform equalizing function.

FIG. 2 is a diagram showing a video signal receiver.

FIG. 3 is a diagram showing a first embodiment of the present invention.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a third embodiment of the present invention.

[Explanation of symbols]

(12) AD converter (14) PLL synchronous clock circuit (synchronous circuit) (15) TVF (transversal filter) (28) VIT memory (waveform memory circuit, digital video signal processing circuit) (32) MUSE signal processing circuit (Digital video signal processing circuit) (38,40) Waveform equalization LSI (38a, 40a) Clock signal input terminal (Clock input terminal) (38b, 40b) Digital video signal input terminal (38c, 40c) Digital video signal output Terminal (38e, 40e) Frame pulse input terminal (sync signal input terminal) (38f, 40f) Line pulse input terminal (sync signal input terminal) (38g, 40g) Frame pulse output terminal (sync signal output terminal) (38h , 40h) Line pulse output terminal (sync signal output terminal) (400) Frame pulse delay circuit (sync signal delay circuit) (420) Frame pulse delay circuit (sync signal delay circuit) (FP) Frame Pulse (sync signal) (FP) Line pulse (sync signal)

Claims (4)

(57) [Claims] 1. A digital video signal input terminal (38b, 4)
0b) and the transversal filter (1) to which the video signals from the digital video signal input terminals (38b, 40b) are input.
5), digital video signal output terminals (38c, 40c) for outputting the transversal filter output to the outside, and clock input terminals (38a, 40c) to which the delay clock signal of the transversal filter (15) is input.
a) and a sync signal (FP, H) separated from the digital video signal.
P) is input , and for waveform equalization, including a synchronization signal delay circuit (400, 420) which is controlled by the clock signal and delays the synchronization signals (FP, HP) .
The delay circuit for synchronizing signals (400, 4
20) Operate according to the delayed sync signal output
LSI waveform equalizing you characterized. 2. A digital video signal input terminal (38b, 4)
0b) and the transversal filter (1) to which the video signals from the digital video signal input terminals (38b, 40b) are input.
5), digital video signal output terminals (38c, 40c) for outputting the transversal filter output to the outside, and clock input terminals (38a, 40c) to which the delay clock signal of the transversal filter (15) is input.
a) and a sync signal (FP, H) separated from the digital video signal.
P) is input, and the synchronizing signal delay circuits (400, 420) are controlled by the clock signal and delay the synchronizing signals (FP, HP), and the output of the synchronizing signal delay circuit (400, 420). To the outside of the synchronization signal output terminals (38g, 40g) (3
8h, 40h), and a waveform equalization LSI comprising: 3. Digital video signal input terminals (38b, 40b)
And a transversal filter (15) to which a video signal from this digital video signal input terminal (38b, 40b) is input,
A digital video signal output terminal (38c, 40c) that outputs this transversal filter output to the outside, and a clock input terminal (38a, 40a) to which the delay clock signal of the transversal filter (15) is input, The sync signal (FP, HP) separated from the digital video signal is input, and the sync signal (FP, HP) is controlled by the clock signal.
A delay circuit for a synchronization signal (400, 420) for delaying the delay signal from the output of the delay circuit for a synchronization signal (400, 420),
A waveform equalizing LSI comprising: a waveform storage circuit (28) which receives a timing control signal and stores the transversal filter output during a period determined by the delay synchronizing signal. 4. An AD converter (12) for converting an analog video signal into a digital video signal, a synchronizing circuit (14) for receiving the digital video signal and separating and outputting a synchronizing signal, and the digital video signal for inputting. Waveform equalization LSI (38, 40) that performs delayed operation based on the supplied clock signal
And a synchronizing signal delay circuit (400, 420) built in the waveform equalizing LSI (38, 40) for delaying the synchronizing signal based on the clock signal, and the waveform equalizing LSI (38, 4)
A video signal receiver provided with a digital video signal processing circuit (28, 32) to which the delayed sync signal from (0) is input and whose operation timing is determined by the delayed sync signal.