JP2560902B2 - Phase synchronization receiver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked receiver, and more particularly to a phase-locked receiver for a satellite communication system that can easily perform initial acquisition of a signal and re-synchronization after a signal is lost. Regarding the receiver.

[Conventional technology]

Conventionally, a receiver used in a satellite communication system receives a weak electric wave from a satellite, and therefore has a configuration using a phase-sensitive circuit with a narrow band and high sensitivity. At the time of synchronization, the local oscillation frequency is swept to facilitate phase synchronization of the received signal.

FIG. 2 is a block diagram of a conventional phase locked receiver.
The received signal is frequency-converted into an intermediate frequency band by the output of the voltage-controlled oscillator 4 in the mixer 1 and input to the gain-controlled amplifier 2, and the phase detector 3 and the phase detector 3 receiving the reference signal from the common reference-signal oscillator 6 It is transmitted to the synchronous detector 5, respectively.

The output of the phase detector 3 is applied to the voltage controlled oscillator 4 via the signal switch 11 to form a phase locked loop. The output of the synchronous detector 5 is added to the gain control amplifier 2 to form an AGC loop. Further, the signal of the sweep oscillator 13 is sent to the signal switch 11 which controls the phase locked loop to perform the sweep. The synchronism detector 12 determines whether the phase-locked loop is synchronized or asynchronized from the output of the synchronism detector 5, and controls the signal switcher 11 based on the determination result.

[Problems to be Solved by the Invention]

In the above-described conventional phase-locked receiver, when the phase-locked loop is swept over the entire received band, the phase is synchronized with the unnecessary signal, so that a minute range is swept around a certain set value.

Therefore, if the received signal deviates with the passage of time, there is a problem that when the signal is lost, the sweep oscillator cannot cover the deviation and cannot resynchronize. Also,
Even if the received signal does not shift, the same problem occurs when the output frequency of the voltage controlled oscillator deviates from the output from the sweep oscillator.

[Means for solving the problem]

The phase-locked receiver of the present invention comprises a mixer for frequency-converting a received signal into an intermediate frequency band, a gain control amplifier for amplifying an output signal of the mixer, and a phase of an output signal of the gain control amplifier. A phase-locked detector for detecting, a voltage-controlled oscillator for inputting a signal from the phase-locked detector to form a phase-locked loop and supplying a local oscillator signal to the mixer, and an output amplitude of the gain-controlled amplifier. In the phase-locked receiver including a synchronous detector that forms an AGC loop in addition to the detected gain control amplifier to control the output amplitude, and a signal switch for controlling the phase-locked loop, the voltage-controlled oscillator , A memory capable of storing the count value of the counter, a control voltage is generated when the phase locked loop is not in phase synchronization, and the signal switcher Through the D / A converter supplied to the voltage controlled oscillator through the received signal, the output frequency of the voltage controlled oscillator based on the information stored in the memory when the received signal is missing is set to the frequency immediately before the missing of the received signal. A processor for generating the control voltage in the D / A converter, sweeping the control voltage, and re-phase synchronizing is provided.

Further, in the phase locked receiver of the present invention, a reference frequency is stored in the memory in advance, and the output frequency of the voltage controlled oscillator is the reference frequency based on the reference frequency stored in the memory at the time of initial acquisition by the processor. The control voltage may be generated and swept by the D / A converter so as to have a frequency.

Further, the phase-locked receiver of the present invention includes a frequency divider that inputs a signal from the voltage controlled oscillator, and the counter inputs the signal from the frequency divider to detect the output frequency of the voltage controlled oscillator. May be configured to do so.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of an embodiment of the present invention.

The received signal is frequency-converted into an intermediate frequency band by the output of the voltage controlled oscillator 4 in the mixer 1, and the gain controlled amplifier 2
Is input to The output of the phase detector 3 and the synchronous detector 5 receives the reference signal from the common reference signal generator 6.
Are sent to each. The output of the phase detector 3 is normally applied to the voltage controlled oscillator 4 via the signal switch 11 to form a phase locked loop (PLL). On the other hand, the output of the synchronous detector 5 is added to the gain control amplifier 2 to form an AGC loop.

The microprocessor 9 reads the count value of the counter 7 according to the control program written in the memory 8. In general, a signal in the tens of MHz band is used as the received signal, and the output frequency of the voltage controlled oscillator 4 also has a value of the same order, so the frequency may not be directly counted by the counter 7. Therefore, in this embodiment, the frequency of the voltage controlled oscillator 4 is counted via the frequency divider 12 and stored in the memory 8.

When the phase locked loop is not in the locked state, the microprocessor 9 sets the signal switcher 11 on the D / A converter 10 side and gives the output of the D / A converter 10 to the voltage controlled oscillator 4 to sweep it. After that, when the locked state is approached, the signal switch 11
To switch to the phase locked loop by the output of the phase detector 3.

Further, when the received signal is cut off after the phase locked loop is once locked, the microprocessor 9 sets the D / A so that it matches the count number of the counter 7 obtained before the received signal is cut off. The voltage controlled oscillator 4 is controlled via the output of the converter 10 and is swept around its frequency for resynchronization.

Therefore, even if the frequency of the received signal is deviated, or even if the oscillation frequency with respect to the control voltage of the voltage controlled oscillator 4 is deviated, the oscillation of the voltage controlled oscillator 4 held in the memory 8 immediately before the reception signal is cut off. Resynchronization can be easily obtained by sweeping a minute range based on the frequency.

Further, at the time of initial capture of the received signal, the control voltage to the voltage controlled oscillator 4 is set to the D / A converter so that the center frequency swept by the voltage controlled oscillator 4 becomes a certain reference frequency stored in the memory 8. Phase lock can be obtained by controlling through 10 and sweeping a little around that frequency.

〔The invention's effect〕

As described above, the present invention generates the control voltage of the phase locked loop based on the output frequency of the voltage controlled oscillator immediately before the reception signal stored in the memory is lost when the reception signal is lost, and Since it is configured to swivel and quickly resynchronize, there is an effect that resynchronization can be easily obtained by sweeping in a minute range even if the frequency of the received signal shifts.

In addition, at the time of initial acquisition of the signal, the control voltage of the voltage controlled oscillator is controlled based on the reference frequency stored in the memory, so that there is no difference between the control voltage of the voltage controlled oscillator and the deviation due to secular change of the oscillation frequency. The effect is that frequency sweeping is performed and synchronization can be easily obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional phase synchronization receiver. 1 ... Mixer, 2 ... Gain control amplifier, 3 ... Phase detector, 4 ... Voltage-controlled oscillator, 5 ... Synchronous detector, 6 ...
Reference signal generator, 7 ... Counter, 8 ... Memory, 9 ...
… Microprocessor, 10 …… D / A converter, 11 …… Signal switch, 12 …… Synchronous detector, 13 …… Sweep oscillator, 14 ……
Frequency divider.

Claims (3)

(57) [Claims] 1. A mixer for frequency-converting a received signal into an intermediate frequency band, a gain control amplifier for amplifying an output signal of the mixer, and a phase for detecting a phase of an output signal of the gain control amplifier. A synchronous detector, a voltage-controlled oscillator which inputs a signal from the phase-locked detector to form a phase-locked loop and supplies a local oscillation signal to the mixer, and an output amplitude of the gain-controlled amplifier to detect the gain. In a phase-locked receiver including a synchronous detector that forms an AGC loop in addition to a control amplifier to control the output amplitude, and a signal switch for controlling the phase-locked loop, the output frequency of the voltage-controlled oscillator is A counter for detecting, a memory capable of storing the count value of the counter, a control voltage generated when the phase-locked loop is not phase-locked, and the voltage via the signal switch. A D / A converter to be supplied to the control oscillator, and the output frequency of the voltage-controlled oscillator based on the information stored in the memory when the received signal is lost so that the output frequency is the frequency immediately before the received signal is dropped. A phase-locked receiver comprising: a processor for generating a control voltage in the D / A converter and sweeping the signal to re-phase-lock. 2. A reference frequency is previously stored in the memory, and the control is performed so that the output frequency of the voltage controlled oscillator becomes the reference frequency based on the reference frequency stored in the memory at the time of initial acquisition by the processor. 2. The phase locked receiver according to claim 1, wherein a voltage is generated and swept by the D / A converter. 3. A frequency divider for inputting a signal from the voltage controlled oscillator, wherein the counter inputs the signal from the frequency divider to detect the output frequency of the voltage controlled oscillator. The phase-locked receiver according to claim 1, wherein the receiver is a phase-locked receiver.