JP2560518B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2560518B2
JP2560518B2 JP2157137A JP15713790A JP2560518B2 JP 2560518 B2 JP2560518 B2 JP 2560518B2 JP 2157137 A JP2157137 A JP 2157137A JP 15713790 A JP15713790 A JP 15713790A JP 2560518 B2 JP2560518 B2 JP 2560518B2
Authority
JP
Japan
Prior art keywords
filler
solder
brazing
soft
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2157137A
Other languages
Japanese (ja)
Other versions
JPH0448770A (en
Inventor
一之 蒔田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2157137A priority Critical patent/JP2560518B2/en
Publication of JPH0448770A publication Critical patent/JPH0448770A/en
Application granted granted Critical
Publication of JP2560518B2 publication Critical patent/JP2560518B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体片とそれに接続される導体端子の間
あるいは高圧整流素子におけるように積層される半導体
片相互間を軟ろうを用いて結合する半導体装置の製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention uses a soft solder to bond between a semiconductor piece and a conductor terminal connected thereto or between semiconductor pieces stacked as in a high-voltage rectifying device. To a method for manufacturing a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体装置の製造の際に、半導体片と導体端子とを結
合するためあるいは高圧整流整流素子の場合のように複
数の半導体片を積層するために軟ろうを用いることが多
い。これは、作業が容易なことおよび接合を有する半導
体片を高温に加熱する必要がないため特性への影響がな
いことによる。従来、半導体装置に使用される軟ろう
は、その組成により溶融温度,熱膨張率などの各種特性
を制御していた。また、ろう付け後のろう層の厚さを所
定の厚さにして結合の信頼性を高めるため、ろう材の中
にろう付温度で溶融しないフィラーを加えたものが考案
された。このフィラー入り軟ろうは、ろう付けに用いら
れる際の板状のろう材の厚さ、あるいはろう付け後の所
期のろう層厚さとほぼ同じ寸法の粒径をもつフィラーが
ろう材内に分布している構造をもつ。このようなフィラ
ー入り軟ろうは、はんだのような軟ろう材料を溶融する
ときにフィラーをその中に入れ、それを冷却して得た鋳
塊を圧延して製造する。あるいは、帯状のろう材を圧延
して製造するとき、ろう材の画面または片面にフィラー
を蒔き、そのまま圧延してフィラーをはんだ内に押し込
む。
In manufacturing a semiconductor device, a soft solder is often used for connecting a semiconductor piece and a conductor terminal or for stacking a plurality of semiconductor pieces as in the case of a high-voltage rectifier. This is because the work is easy and there is no need to heat the semiconductor piece having the junction to a high temperature, so that the characteristics are not affected. Conventionally, various properties such as melting temperature and coefficient of thermal expansion of soft solder used in semiconductor devices have been controlled by the composition thereof. Further, in order to increase the reliability of bonding by setting the thickness of the brazing layer after brazing to a predetermined thickness, a brazing material containing a filler that does not melt at the brazing temperature has been devised. This filler-containing soft brazing filler metal has a particle size that is approximately the same as the thickness of the plate-shaped brazing filler metal used for brazing or the desired brazing layer thickness after brazing. It has a structure. Such a soft solder containing a filler is manufactured by inserting a filler into a soft brazing material such as solder when the soft brazing material is melted, and cooling the resulting ingot. Alternatively, when a strip-shaped brazing material is rolled and manufactured, a filler is sown on the screen or one side of the brazing material, and the filler is rolled into the solder and pressed into the solder.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

従来のフィラー入り軟ろう材には次のような問題があ
った。
The conventional filler-containing soft brazing material has the following problems.

(1)フィラーを溶融ろう材に添加する方法では、フィ
ラーの分布状態を制御しにくいため、ろう材中にフィラ
ーの塊が生じやすい。このフィラーの塊がろう材表面に
顔を出すと、ろう付されない個所が生ずる。
(1) In the method of adding the filler to the molten brazing filler metal, it is difficult to control the distribution state of the filler, and thus the filler lumps are likely to occur in the brazing filler metal. When this lump of filler is exposed on the surface of the brazing material, there are some areas that are not brazed.

(2)フィラーを溶融ろう材に添加する場合、フィラー
とろう材の比重が大きく異なると、フィラーは溶融ろう
材の上部あるいは下部に集中してしまい、鋳塊中のフィ
ラーの分布が不均一になるため、圧延後も均一な分布の
フィラー入り軟ろう材を得ることができない。
(2) When the filler is added to the molten brazing filler metal, if the specific gravity of the filler and the brazing filler metal greatly differ, the filler concentrates on the upper or lower portion of the molten brazing filler metal, resulting in uneven distribution of the filler in the ingot. Therefore, it is impossible to obtain a filler-containing soft brazing filler metal having a uniform distribution even after rolling.

(3)帯状ろう材の圧延の際に表面にフィラーを蒔いて
押し込む方法では、フィラーの量が多いと表面部をフィ
ラーが占める割合が多くなり、ろう付性が低下する。
(3) In the method of squeezing the filler on the surface during the rolling of the band-shaped brazing material and pushing it in, when the amount of the filler is large, the ratio of the filler occupying the surface portion increases and the brazing property decreases.

本発明の目的は、上述の問題を解決し、ろう付け性が
良好なフィラー入り軟ろうを用い、所望の特性を有する
均一な結合部を形成することのできる半導体装置の製造
方法を提供することにある。
An object of the present invention is to solve the above problems and to provide a method for manufacturing a semiconductor device capable of forming a uniform joint having desired characteristics by using a soft solder containing a filler having a good brazing property. It is in.

〔課題を解決するための手段〕[Means for solving the problem]

上記の目的を達成するために、本発明は、半導体片と
導体端子との間あるいは半導体片相互間を軟ろうを用い
てのろう付けにより結合する半導体装置の製造方法にお
いて、表面層が軟ろうのみよりなり、内部に層状にフィ
ラーを多く含む層を有する積層体を圧延してなるフィラ
ー入り軟ろう材を用いてろう付けするものとする。
In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor device in which a semiconductor piece and a conductor terminal or between semiconductor pieces are joined together by brazing using a soft solder. It is brazed using a filler-containing soft brazing material obtained by rolling a laminated body having a layer containing a large amount of filler in a layered state.

〔作用〕[Action]

表面が軟ろうのみよりなり、内部に層状にフィラーを
多く含む層を有する積層体を圧延してなるフィラー入り
軟ろう材は、表面にフィラーがほとんど存在しないた
め、ろう付け時に被結合部材表面に接するフィラーがほ
とんどなく、部材とろうとの結合を阻害しない。そし
て、溶融ろう材とフィラーを混合するのではないので比
重の問題はなく、ろう材には平面的に均一にフィラーが
存在するので均一な結合が生ずる。また、フィラーに富
む層が軟ろう層中に層状に存在するので、導体端子と半
導体片との熱膨張係数の差により半導体片に加わる結合
面と平行な応力が緩和され、半導体装置の熱疲労に対す
る耐性,サージ電流に対する限界特性などが向上する。
The surface is made of only soft solder, and the filler-containing soft brazing material obtained by rolling the laminate having the layer containing a large amount of filler in the layered state is almost free of filler on the surface. There is almost no filler in contact, and it does not hinder the bonding between the member and the wax. Further, since the molten brazing material and the filler are not mixed, there is no problem of specific gravity, and since the filler is present uniformly in the brazing material in a plane, uniform bonding occurs. In addition, since the filler-rich layer exists in layers in the soft brazing layer, the stress parallel to the bonding surface applied to the semiconductor piece is relaxed due to the difference in the thermal expansion coefficient between the conductor terminal and the semiconductor piece, and the thermal fatigue of the semiconductor device. Resistance and surge current limit characteristics are improved.

〔実施例〕〔Example〕

以下、図を引用して本発明の実施例について延べる。
第1図は本発明の一実施例に用いたフィラー入りはんだ
板1を示し、Pb/Sn=90/10のはんだ層2の中に平均粒径
20μmのシリコン粒がフィラー3として混在している。
はんだ板1の厚さは80μmである。このフィラー入りは
んだ板1は第3図(a),(b)に示す方法で製造し
た。すなわち、同図(a)に示すように厚さ50μmの帯
はんだ21の上にフィラー3を蒔き、それを3枚重ね、さ
らにフィラーを蒔かない帯はんだ21を1枚重ねたのち、
同図(b)に示すようにこの積層体20を圧延ロール31,3
2を用いて80μmの厚さまで圧延した。これにより表面
にフィラー3が露出しないフィラー入りはんだ板が得ら
れた。このはんだ板1を用いて第2図に示すような高圧
整数素子を製造した。図において、半導体片4はSi基板
の両面よりドナーおよびアクセプタを拡散し、Ni電極5
を設けたのち、方形に切断したものである。この半導体
片4をフィラー入りはんだ板1を重ねて積重ね、さらに
両端に導体端子7の頭部の電極6を接触させて加熱して
はんだ付けを行った。このあと、側面をJCR8で被覆した
のち、樹脂9により封止した。この整流素子と同一構造
でフィラーを含まない90/10はんだ板を用いてろう付け
した整流素子とのサージ電流に対する限界特性を測定し
たところ、第2の整流素子の方が2倍の耐性があった。
これははんだ付け部の特性によるものと考えられる。
Examples of the present invention will be described below with reference to the drawings.
FIG. 1 shows a solder plate 1 containing a filler used in one embodiment of the present invention, in which an average particle size is contained in a solder layer 2 of Pb / Sn = 90/10.
20 μm silicon particles are mixed as the filler 3.
The thickness of the solder plate 1 is 80 μm. This filler-containing solder plate 1 was manufactured by the method shown in FIGS. 3 (a) and 3 (b). That is, as shown in FIG. 3A, the filler 3 is sown on the band solder 21 having a thickness of 50 μm, three pieces of the filler 3 are stacked, and further one band solder 21 without the filler is stacked,
This laminated body 20 is rolled into rolls 31, 3 as shown in FIG.
2 was rolled to a thickness of 80 μm. As a result, a filler-containing solder plate in which the filler 3 was not exposed on the surface was obtained. Using this solder plate 1, a high voltage integer element as shown in FIG. 2 was manufactured. In the figure, the semiconductor piece 4 diffuses donors and acceptors from both sides of the Si substrate, and the Ni electrode 5
It was cut into a square after the provision of. The semiconductor pieces 4 were stacked by stacking the solder plates 1 containing filler, and the electrodes 6 on the heads of the conductor terminals 7 were brought into contact with both ends to be heated and soldered. Then, the side surface was covered with JCR8 and then sealed with resin 9. The rectifying element was brazed with a 90/10 solder plate having the same structure as this rectifying element and containing no filler, and the limiting characteristics against surge current were measured. The second rectifying element had twice the resistance. It was
This is considered to be due to the characteristics of the soldered part.

第4図は本発明の別の実施例のフィラー入りはんだ板
の製造方法を示し、上にフィラー3を蒔いた長い帯はん
だ21を巻回し、これを図の上下方向に押しつぶして第3
図の積層体20と同様の積層体を得る。これを圧延するこ
とにより内部にフィラーの層構造を有するフィラー入り
はんだ板1を作製することができる。
FIG. 4 shows a method for manufacturing a solder plate containing a filler according to another embodiment of the present invention, in which a long strip of solder 21 having a filler 3 is wound on it, and this is crushed in the vertical direction of the drawing to form a third plate.
A laminate similar to the laminate 20 in the figure is obtained. By rolling this, the filler-containing solder plate 1 having a filler layer structure inside can be produced.

第1図に示したフィラー入りはんだ板1は目的のはん
だ厚さの1/4の粒径のフィラー3が含むが、第5図に示
したはんだ板11ははんだ層2の中に目的のはんだ厚さの
1/10の粒径のフィラー3を含む。
Although the filler-containing solder plate 1 shown in FIG. 1 contains the filler 3 having a particle diameter of 1/4 of the target solder thickness, the solder plate 11 shown in FIG. 5 contains the target solder in the solder layer 2. Thick
Includes 1/3 particle size filler 3.

上記の実施例で、フィラー3としてSi粒を用いたのは
粒径の揃った粒が得やすいという理由に基づく。しか
し、他のはんだより融点の高い材料の粒子、例えばAg,N
iあるいはAgの被覆したCuの粒を用いることもできる。
溶融はんだに対するフィラーの混合によらないので、フ
ィラーの材料を任意に選ぶことができる。また、Pb/Sn
はんだの代りに他の軟ろうを用いることができる。
In the above examples, the reason why Si particles are used as the filler 3 is that particles having a uniform particle size are easily obtained. However, particles of a material with a higher melting point than other solders, such as Ag, N
Cu grains coated with i or Ag can also be used.
Since the filler is not mixed with the molten solder, the filler material can be arbitrarily selected. Also, Pb / Sn
Other soft solders can be used instead of solder.

〔発明の効果〕〔The invention's effect〕

本発明によれば、表面層がフィラーを含まない軟ろう
よりなり、内部に層状にフィラーを含む層を有する積層
体を圧延して作製したフィラー入り軟ろう板を用いて、
半導体片相互あるいは半導体片と導体端子との結合を行
うことにより、ろう付け性が向上し、ろう層が所定の厚
さになるので信頼性の高い半導体装置を得ることができ
た。また、フィラー層が結合面に平行な層構造となるの
で、ろう層に生ずる結合面に平行な応力が緩和された。
さらに、フィラーの材料も任意に選定できるので、サー
ジ電流に対する耐量をはじめ、ろう材の組成によって制
御できない特性の向上も可能になるなど、本発明により
得られる効果は極めて大きい。
According to the present invention, the surface layer is made of a soft wax containing no filler, using a filler-containing soft solder plate prepared by rolling a laminate having a layer containing a filler layered inside,
By connecting the semiconductor pieces to each other or connecting the semiconductor pieces to the conductor terminals, the brazing property is improved and the brazing layer has a predetermined thickness, so that a highly reliable semiconductor device can be obtained. Further, since the filler layer has a layered structure parallel to the bonding surface, the stress generated in the brazing layer parallel to the bonding surface was relaxed.
Further, since the material of the filler can be arbitrarily selected, the effects obtained by the present invention are extremely large, such as the improvement of the resistance to surge current and the characteristics that cannot be controlled by the composition of the brazing material.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例に用いるフィラー入りはんだ
板の断面図、第2図は本発明の一実施例によって製造さ
れる高圧整流素子の断面図、第3図は第1図のはんだ板
の製造工程の一例を示し、(a)は積層体の断面図、
(b)はその積層体の圧延工程を示す断面図、第4図は
フィラー入りはんだ板製造工程の他の例を説明する断面
図、第5図は本発明の実施例に用いる他のフィラー入り
はんだ板の断面図である。 1,11:フィラー入りはんだ板、2:はんだ層、3:フィラ
ー、4:半導体片、6:電極、7:導体端子、20:積層体。
FIG. 1 is a cross-sectional view of a solder plate containing a filler used in an embodiment of the present invention, FIG. 2 is a cross-sectional view of a high-voltage rectifying element manufactured according to an embodiment of the present invention, and FIG. 3 is the solder of FIG. An example of the manufacturing process of a board is shown, (a) is sectional drawing of a laminated body,
(B) is a cross-sectional view showing a rolling process of the laminate, FIG. 4 is a cross-sectional view illustrating another example of a manufacturing process of a filler-containing solder plate, and FIG. 5 is another filler-containing solder used in an embodiment of the present invention. It is sectional drawing of a solder plate. 1, 11: solder plate containing filler, 2: solder layer, 3: filler, 4: semiconductor piece, 6: electrode, 7: conductor terminal, 20: laminated body.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体片と導体端子との間あるいは半導体
片相互間の軟ろうを用いてのろう付けによる結合する半
導体装置の製造方法において、表面層が軟ろうのみより
なり、内部に層状にフィラーを多く含む層を有する積層
体を圧延してなるフィラー入り軟ろう材を用いてろう付
けすることを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device in which a semiconductor piece and a conductor terminal or between semiconductor pieces are joined by brazing using soft solder, wherein a surface layer is made of only soft solder, and a layer is formed inside. A method for manufacturing a semiconductor device, which comprises brazing using a filler-containing soft brazing material obtained by rolling a laminate having a layer containing a large amount of filler.
JP2157137A 1990-06-15 1990-06-15 Method for manufacturing semiconductor device Expired - Lifetime JP2560518B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2157137A JP2560518B2 (en) 1990-06-15 1990-06-15 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2157137A JP2560518B2 (en) 1990-06-15 1990-06-15 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0448770A JPH0448770A (en) 1992-02-18
JP2560518B2 true JP2560518B2 (en) 1996-12-04

Family

ID=15643010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2157137A Expired - Lifetime JP2560518B2 (en) 1990-06-15 1990-06-15 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2560518B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232188A (en) * 1993-01-29 1994-08-19 Nec Corp Manufacture of solder material
TWI230104B (en) 2000-06-12 2005-04-01 Hitachi Ltd Electronic device
JP3757881B2 (en) 2002-03-08 2006-03-22 株式会社日立製作所 Solder

Also Published As

Publication number Publication date
JPH0448770A (en) 1992-02-18

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