JP2557847B2 - Operation analysis method and operation analysis apparatus for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to an operation analysis technique for a semiconductor integrated circuit,
In particular, the present invention relates to an operation analysis method and an operation analysis apparatus for a semiconductor integrated circuit in which a desired wiring portion is cut by using a focused ion beam for operation analysis.

(Prior Art) Conventionally, in a semiconductor integrated circuit in which semiconductor elements are integrated on a substrate, for example, a semiconductor memory, a sense amplifier is used to shorten access time. Here, between the magnitude of the driving force of the sense amplifier (the amount of current that can be handled) and the access time A and the power consumption B,
There is a relationship as shown in the figure. That is, if the sense amplifier is made larger, the access time A becomes shorter but the power consumption B becomes larger. Conversely, if the sense amplifier is made smaller, the power consumption B becomes smaller but the access time A becomes longer. In the semiconductor memory, generally, the memory having the smallest value C of (access time) + (power consumption) has the best performance. Therefore, in order to obtain such a memory, it is necessary to use a sense amplifier having an optimum size that minimizes the value C.

In order to optimize the size of the sense amplifier, it is necessary to investigate the dependence of access time and power consumption on the size of the sense amplifier. Therefore, conventionally, the required number of types of memory chips having sense amplifiers of different sizes were manufactured, and the operation analysis was performed for each memory chip. However, manufacturing a plurality of types of memory chips having sense amplifiers of different sizes complicates the manufacturing process, and the manufacturing time of the plurality of types of chips as a whole becomes enormous. Therefore, it takes a long time to optimize the size of the sense amplifier, and a long development period is required to realize the semiconductor memory.

Also, instead of manufacturing a memory chip with sense amplifiers of different sizes, it is possible to change the size of the sense amplifier by separating the constituent elements of the sense amplifier. In this case, the constituent elements are separated. However, it is necessary to cut the wiring. Conventionally, a method of using a laser beam has been used as a means for cutting the wiring, but the beam diameter of the laser beam is larger than that of the wiring pattern (3 to 5 μm).
Therefore, it is difficult to selectively cut only the fine wiring portion.

(Problems to be Solved by the Invention) As described above, when it is necessary to separate an unnecessary circuit which obstructs operation analysis of a semiconductor integrated circuit,
It was necessary to separately manufacture a chip having a circuit configuration equivalent to that of an unnecessary circuit separated, which required manufacturing time. Therefore, there is a problem that it takes a long time to develop the semiconductor integrated circuit.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to unnecessarily perform operation analysis by selectively cutting a desired wiring portion for operation analysis of a semiconductor integrated circuit. It is possible to separate various circuits and obtain a chip with a circuit configuration required for operation analysis in a much shorter time than when a chip with another circuit configuration is manufactured, which shortens the development period of semiconductor integrated circuits. An object is to provide a method for analyzing the operation of a semiconductor integrated circuit to be obtained.

Another object of the present invention is to provide a semiconductor integrated circuit operation analysis apparatus for implementing the above method.

[Structure of the Invention] (Means for Solving Problems) The essence of the present invention is to separate a circuit unnecessary for operation analysis by cutting the wiring portion thereof, and use a focused ion beam for this cutting. Especially.

A method of using a laser beam can be considered as a cutting means for the wiring portion.
It is not possible to selectively cut only the wiring part of a fine pattern such as SI. Therefore, in the present invention, fine wiring is cut using a focused ion beam. Here, the focused ion beam can be easily focused to a beam diameter of 0.1 to several μm, and the fine wiring portion can be selectively cut. Further, even if the wiring is covered with the passivation film, only the intended wiring can be cut.

The present invention focuses on such points, and in the operation analysis method of a semiconductor integrated circuit in which a plurality of semiconductor elements are integrated on a substrate, a desired integrated circuit to be cut for the operation analysis of the semiconductor integrated circuit is desired. This is a method in which after the wiring part of is cut with a focused ion beam, the operation analysis of the semiconductor integrated circuit is performed using a VLSI tester, an electron beam tester, or the like.

Further, the present invention provides a semiconductor integrated circuit operation analysis apparatus for performing the above method, including a vacuum container for accommodating the semiconductor integrated circuit, and an operation analysis unit such as an electron beam tester for analyzing the operation state of the semiconductor integrated circuit. The semiconductor integrated circuit is provided with a focused ion beam irradiation unit for irradiating the semiconductor integrated circuit with a focused ion beam and cutting a desired wiring portion of the integrated circuit.

(Operation) According to the above method, an unnecessary circuit can be separated by using a focused ion beam in the operation analysis of the semiconductor integrated circuit. Therefore, a chip having a circuit configuration equivalent to that of the unnecessary circuit can be separated. The circuit configuration required for motion analysis can be realized in a much shorter time than the fabrication. Therefore, the operation analysis of the semiconductor integrated circuit can be performed easily in a short time. Further, since the wiring portion can be cut and the operation analysis can be performed while the semiconductor integrated circuit is placed in the same container, the time required for the operation analysis can be significantly shortened.

(Examples) The details of the present invention will be described below with reference to illustrated examples.

FIG. 1 is a schematic configuration diagram showing a focused ion beam irradiation apparatus used in the method of one embodiment of the present invention. In the figure, 11 is a sample such as a semiconductor integrated circuit, and this sample 11 is a sample stage.
12 is placed on. The sample stage 12 is housed in a vacuum container (not shown). The sample stage 12 is moved in the X direction (left and right direction on the paper surface) and the Y direction (front and back direction on the paper surface) by a stage drive circuit 13 that operates according to a command from the computer 20.

Above the sample stage 12, the ion beam optical barrel 30
The lens barrel 30 is provided with an ion beam control system 40.
It is controlled by. The ion beam optical barrel 30 is composed of an ion source 31, an aperture 32, an electrostatic lens 33, a blanking electrode 34, an aperture 35, a deflector 36, and the like. Then, the ion beam emitted from the ion source 31 is focused by the lens 33 and irradiated on the sample 11, and the deflector 36 scans the sample 11. Further, the ion beam control system 40 is composed of a lens control circuit 43, a blanking control circuit 44, a deflection control circuit 46 and the like. These control circuits 43,44,46
Is to apply a predetermined voltage to the lens 33, the blanking electrode 34, and the deflector 36 according to a command from the computer 20.

Next, an operation analysis method of a semiconductor integrated circuit using the above device will be described. In this embodiment, a semiconductor memory is used as the semiconductor integrated circuit.

As shown in FIG. 2, the semiconductor memory 51 is composed of a plurality of memory elements 52 and a sense amplifier 53. Here, the sense amplifier 53 is an 80% constituent element as shown in FIG.
54% and 20% component 55, and 20% component 55 is 80%
It is connected in parallel with the component 54. In addition, 5 in FIG.
6,57 is the connection of 20% component 55 to 80% component 54, 5
Reference numerals 8 and 59 represent bit lines.

First, a predetermined power supply was connected to the semiconductor memory 51, and the access time of the sense amplifier 53 (100% constituent element) was measured with a VLSI memory tester. Then, using the apparatus shown in FIG. 1, the sense amplifier 53 is irradiated with the focused ion beam.
20% of the elements that make up
Separated from. That is, the wiring portions 56 and 57 of the 20% constituent element 55 shown in FIG. 3 were cut by irradiation with a focused ion beam. In this state, the access time of the sense amplifier 53 (80% constituent element) was measured with a VLSI memory tester.

Here, a cross section of the cut wiring is shown in FIG. In FIG. 4, 61 is a silicon substrate, 62 is an oxide film, 63 is polysilicon wiring, 64 is aluminum wiring, and 65 is a passivation film.
Polysilicon wiring 63 and aluminum wiring 64 are each 3.6
It is covered with a passivation film 65 of μm and 2.6 μm.

As shown in FIG. 4, the wirings 63, 64 and the like which are thickly covered with the passivation film 65 cannot be cut by the laser beam. On the other hand, with the focused ion beam, the wiring is cut by sputter etching, so that it can be cut regardless of the material and even if it is thickly coated. Also,
With a focused ion beam, a beam diameter of 0.1 to several μm can be easily obtained, and fine processing is possible, so that only a target wiring can be cut even in a fine circuit. In this example, a Ga focused ion beam with an accelerating voltage of 30 kv was used, and the wiring cutting time was about 60 seconds under the conditions of a beam current of 2 nA and a beam diameter of 1 μm. At the time of cutting the wiring, a device controlled by a computer as shown in FIG. 1 was used to irradiate a focused ion beam only on the desired wiring to cut the wiring portion.

FIG. 5 shows the results of measuring the access time of the semiconductor memory (memory chips equipped with sense amplifiers of 100% and 80% size) before and after disconnecting the wiring with a VLSI memory tester. FIG. 5 (a) shows a memory having a 100% -sized sense amplifier, and FIG. 5 (b) shows the result of a memory having an 80% -sized sense amplifier. from this result,
In this memory, it was found that when the size of the sense amplifier is set to 80%, the access time becomes about 4nsec.

In practice, the sense amplifier is formed of a main constituent element and a plurality of auxiliary constituent elements, and the auxiliary constituent elements are sequentially separated to obtain the optimum size of the sense amplifier.
For example, as shown in Fig. 6, main constituent elements (70% constituent elements)
Auxiliary constituent elements (10% constituent elements) 71, ..., 73 that can be separated from this together with 70 are formed, and the auxiliary constituent elements 71, ..., 73 are separated in this order using a focused ion beam, and 100%, 90% , 80
%, 70%, access time and power consumption are measured, and the condition that the value of (access time) + (power consumption) is minimum is found. This makes it possible to analyze the size of the sense amplifier close to the optimum condition.

Thus, according to the method of this embodiment, by cutting the predetermined wiring portion with the focused ion beam, it is possible to obtain sense amplifiers having different driving forces (the amount of current that can be handled) from one chip. Then, in each case, the optimum size of the sense amplifier can be determined by measuring the relationship between the access time and the power consumption. That is, it is not necessary to provide a plurality of types of chips having sense amplifiers having different sizes as in the conventional case, and the circuit configuration required for the operation analysis can be easily realized in a short time. Therefore, the development period required to realize a semiconductor memory having an optimal size sense amplifier is
It can be greatly shortened.

 Next, another embodiment of the present invention will be described.

FIG. 7 is a schematic configuration diagram schematically showing an operation analysis device of a semiconductor integrated circuit according to another embodiment of the present invention. This embodiment is an example in which an electron beam tester (EB tester) and a focused ion beam irradiation device are combined. In the figure, 10 is a vacuum container, in which a sample 11 such as a semiconductor integrated circuit is provided.
A sample stage 12 on which is mounted is housed. The sample stage 12 is moved in the X direction (left and right direction on the paper surface) and the Y direction (front and back direction on the paper surface) by a stage drive circuit 13 that operates according to a command from the computer 20.

An electron beam optical lens barrel 80 is provided above the vacuum container 10. The lens barrel 80 irradiates a desired position on the sample 11 with an electron beam, and is controlled by an electron beam control system 90 . Then, the sample 11 is irradiated with the electron beam.
The secondary electrons emitted from the surface of the are detected by the electron detector 14, and this detection information is supplied to the signal processing circuit 15. An ion beam optical lens barrel 30 is provided on the side of the electron beam optical lens barrel 80 . The lens barrel 30 is for irradiating the wiring portion of the sample 11 to be cut with the focused ion beam from an oblique direction, and is the same as that shown in FIG.

 Fig. 8 shows electron beam optical lens barrel80And its control system90Ingredient
It is a schematic diagram which shows a physical constitution. Electron beam optical barrel80
Is an electron gun 81, blanking electrode 82, condenser lens 8
3, which includes a deflector 84, an objective lens 85, and the like. So
Then, the electron beam emitted from the electron gun 81 is reflected by the lenses 83, 8
It is reduced by 5 and irradiated on the sample 11 and deflected.
The sample is scanned on the sample 11 by the device 84. This
In the sample 11 by the electron beam irradiation of the
Secondary electrons are emitted according to the potential. And this secondary
The electrons are detected by the electron detector 14.
Also, electron beam control system90Is the electron gun control circuit 91, bra
Focusing control circuit 92, condenser lens control circuit 93, deflection
It consists of a control circuit 94 and an objective lens control circuit 95.
You. Then, these control circuits 91 to 95 are connected to the computer.
In response to a command from the
S 83, 85 and the deflector 84.

In the present apparatus thus configured, the potential of each part of the semiconductor integrated circuit in the operating state can be measured by the function of the EB tester. That is, the electron beam optical lens barrel 80 scans the sample 11 with an electron beam to detect secondary electrons at this time. The secondary electron intensity changes according to the potential of the beam irradiation part. Therefore, the potential of the beam irradiation unit can be indirectly measured by detecting the secondary electrons.

On the other hand, the focused ion beam irradiation function can cut a desired wiring portion. That is, by scanning the sample 11 with the ion beam by the ion beam optical lens barrel 30 , a desired wiring portion can be cut, and thus a circuit unnecessary for the operation analysis can be cut off.

Therefore, according to the present embodiment, after the desired wiring portion is cut by the ion beam irradiation function, the operation analysis of only the necessary circuit portion can be performed by the EB tester function. In this case, similarly to the previous embodiment, since it is not necessary to separately manufacture a chip having a configuration excluding the circuit to be separated, the operation analysis can be easily performed. In addition, the sample
Since the wiring part can be cut and the operation analysis can be performed while the 11 is housed in the same vacuum container 10, there is an advantage that the time required for the operation analysis can be further shortened.

Note that the present invention is not limited to the above-described embodiments. For example, the sample to be subjected to the operation analysis is not limited to the semiconductor memory and can be applied to various semiconductor integrated circuits. Further, in the apparatus shown in FIG. 7, the operation analysis unit is not limited to the EB tester, and may be any unit capable of detecting the potential of each part of the sample while the sample is placed in a vacuum. If a motion analyzer that performs the same measurement as an EB tester by ion beam irradiation is used, it is possible to use only one lens barrel (motion analysis unit and ion beam irradiation unit) connected to the vacuum container. In addition, various modifications can be made without departing from the scope of the present invention.

[Effect of the Invention] As described in detail above, according to the present invention, an unnecessary circuit which hinders the operation analysis of the semiconductor integrated circuit is separated by the focused ion beam irradiation to the fine wiring portion. It is possible to realize the circuit configuration required for the operation analysis in a much shorter time than the case of manufacturing the chip having the circuit configuration of. Therefore, the operation analysis of the semiconductor integrated circuit can be performed easily and in a short time, and the development period of the semiconductor integrated circuit can be shortened.

[Brief description of drawings]

1 to 6 are each for explaining an embodiment method of the present invention. FIG. 1 is a schematic configuration diagram showing a focused ion beam irradiation apparatus used in the embodiment method, and FIG. 2 is a sample. FIG. 3 is a schematic diagram showing the structure of a semiconductor memory as an example, FIG. 3 is a circuit configuration diagram showing the configuration of a sense amplifier section, FIG. 4 is a sectional view showing the schematic structure of a wiring section, and FIG. 5 is an access time and the number of bits. FIG. 6 is a schematic diagram showing another example of the configuration of a semiconductor memory, FIG. 7 is a schematic configuration diagram showing an operation analysis device of a semiconductor integrated circuit according to another example, and FIG.
FIG. 9 is a main part configuration diagram showing a specific configuration of an electron beam optical lens barrel and its control system used in the above-described operation analysis device, and FIG. 9 is a diagram for explaining a conventional problem, and it relates to the size of a sense amplifier. It is a characteristic view which shows the relationship between access time and power consumption. 11 …… Sample (semiconductor integrated circuit), 12 …… Sample stage,
14 ... Electron detector, 20 ... Computer, 30 ... Ion beam optical lens barrel, 40 ... Ion beam control system, 51 ... Semiconductor memory, 52 ... Memory element, 53 ... Sense amplifier,
54 …… 80% component, 55 …… 20% component, 56,57 ……
Connection wiring part, 70 ... Main constituent element (70% constituent element), 71,
~, 73 …… Auxiliary component (10% component), 80・・・ Electron beam optical lens barrel, 90・・・ Electron beam control system.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H01L 27/10 481 G11C 11/34 353Z (56) Reference JP-A-59-168652 (JP, A, 652) ) JP-A-51-108580 (JP, A) JP-A-60-169150 (JP, A) JP-A-59-172248 (JP, A)

Claims (5)

(57) [Claims] 1. A method for analyzing the operation of a semiconductor integrated circuit in which a plurality of semiconductor elements are integrated on a substrate, wherein the semiconductor integrated circuit has a sense amplifier and a plurality of memories in which the magnitude of driving force can be varied by cutting wiring. After forming a semiconductor memory composed of elements, a desired wiring portion of a sense amplifier to be cut for operation analysis of the semiconductor integrated circuit is cut by a focused ion beam, and then operation analysis of the integrated circuit is performed. A characteristic analysis method of a semiconductor integrated circuit. 2. The operation analysis method for a semiconductor integrated circuit according to claim 1, wherein a VLSI memory tester or an electron beam tester is used as the means for performing the operation analysis. 3. A vacuum container for accommodating a substrate on which a semiconductor memory including a sense amplifier and a plurality of memory elements, which can change the magnitude of driving force by cutting wiring, is formed as a semiconductor integrated circuit on the substrate, and the semiconductor. The integrated circuit comprises an operation analysis section for analyzing the operation state of the integrated circuit, and a focused ion beam irradiation section for irradiating the sense amplifier section of the semiconductor integrated circuit with a focused ion beam to cut a desired wiring section of the sense amplifier. A semiconductor integrated circuit operation analysis apparatus characterized by the above. 4. The operation analysis unit is an electron beam tester for irradiating the semiconductor integrated circuit with an electron beam and detecting secondary electrons from the integrated circuit to detect the potential of the beam irradiation unit. 4. A semiconductor integrated circuit operation analysis apparatus according to claim 3. 5. The semiconductor integrated device according to claim 3, wherein the focused ion beam irradiating unit irradiates the semiconductor integrated circuit with an ion beam from an oblique direction. Circuit motion analysis device.