JP2556404B2 - Frequency-voltage conversion circuit - Google Patents
Frequency-voltage conversion circuitInfo
- Publication number
- JP2556404B2 JP2556404B2 JP3284239A JP28423991A JP2556404B2 JP 2556404 B2 JP2556404 B2 JP 2556404B2 JP 3284239 A JP3284239 A JP 3284239A JP 28423991 A JP28423991 A JP 28423991A JP 2556404 B2 JP2556404 B2 JP 2556404B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- circuit
- conversion circuit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Controls And Circuits For Display Device (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、オートスキャン方式の
表示装置に使用する周波数−電圧変換回路に関するもの
である。
【０００２】
【従来の技術】小型陰極線管、液晶、又はプラズマ等を
使用するオートスキャン方式の表示装置においては、水
平発振周波数、水平位相、偏向高圧等の制御用電圧とし
て水平同期信号を直流電圧に変換する周波数−電圧変換
回路（以下Ｆ−Ｖ変換回路と略称す。）が必要であり、
通常は水平同期信号をマルチヴァイブレーター回路を用
いたパルスカウント方式のＦ−Ｖ変換回路を使って直流
電圧に変換している。
【００３】
【発明が解決しようとする問題点】しかしながら、供給
される信号の違いによって前記Ｆ−Ｖ変換回路で作られ
る変換直流電圧に誤差が生ずる。例えば、水平同期信号
として図２−イのセパレート信号（垂直同期信号なし）
と図２−ロの複合同期信号（垂直同期信号あり）がＦ−
Ｖ変換回路に入力された場合を比較すると、図２−ロの
信号は垂直同期信号パルス幅の期間内に水平同期信号が
無い為、計数パルス数が少なくなり、前記Ｆ−Ｖ変換回
路に発生する制御用の変換直流電圧は、図２−イのセパ
レート信号を計数することによって発生する制御用の変
換直流電圧より低くなってしまう。つまり、同一の水平
同期周波数でもセパレート信号と複合同期信号とでは変
換電圧に差が出てしまう。又この差は垂直同期パルス幅
が長い程大きくなり、画面の位相ずれや水平発振周波数
のずれ等の問題が生じていた。
【０００４】
【課題を解決するための手段】本発明は、前記の不具合
を解消するためにＦ−Ｖ変換回路の前段に設けた周波数
分離回路と信号選択回路とによって複合同期信号中の垂
直同期信号の期間を検出し、該期間内に水平ドライブパ
ルス信号を取り込んだ信号をＦ−Ｖ変換回路に入力する
ことを特徴としている。
【０００５】
【実施例】図１は本発明になる実施例図であり、図２は
供給される入力信号波形、図３及び図４は図１における
各主要点の波形図であり、以下図に従って説明する。 【０００６】 図１のＡ点に入力された図２−イの信号
（水平同期信号）は垂直同期信号のみ取り出す周波数分
離回路２（抵抗Ｒ、コンデンサーＣ及びトランジスター
Ｑより構成されている）によって水平同期周波数成分が
除去され、Ｃ点はローレベルとなってＮＡＮＤゲートで
構成されている信号選択回路３のＮＡＮＤゲートＩＩに
供給される。その為、Ｂ点から信号選択回路３のＮＡＮ
ＤゲートＩＩＩに供給されている水平ドライブ信号（水
平発振回路から常に供給されている）はカットされてＡ
点から直接信号選択回路３のＮＡＮＤゲートＩに供給さ
れている信号がＤ点に出力され、Ｆ−Ｖ変換回路１に供
給されて変換電圧が発生する。 【０００７】 次に、図２−ロの複合同期信号がＡ点に供
給されると周波数分離回路２で水平同期周波数成分が除
去され、Ｃ点に垂直同期パルス幅の期間のみハイレベル
となっている信号が得られて信号選択回路３に送られ
る。この状態でＡ点から直接信号選択回路３に供給され
ている該複合同期信号の垂直同期信号期間内に、該垂直
同期信号幅の長短に拘らずＢ点に供給されている水平ド
ライブ信号が取り込まれた図４のような信号がＤ点に出
力し、Ｆ−Ｖ変換回路１に送られて変換電圧が発生す
る。 【０００８】
【発明の効果】以上、説明した如く、本発明になるＦ−
Ｖ変換回路には周波数分離回路２と信号選択回路３によ
って信号形態の相違を補正した信号をＦ−Ｖ変換回路１
に入力する為に変換電圧に誤差が生じない、回路が簡略
化される等の効果を得ることが可能である。 Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency-voltage conversion circuit used in an auto-scan display device. 2. Description of the Related Art In a display device of an auto scan system using a small cathode ray tube, liquid crystal, plasma or the like, water is used.
As the control voltage for the flat oscillation frequency, horizontal phase, deflection high voltage, etc.
Frequency-voltage conversion to convert the horizontal sync signal to DC voltage
A circuit (hereinafter abbreviated as FV conversion circuit) is required,
Normally, the horizontal synchronizing signal is converted into a DC voltage by using a pulse count type FV conversion circuit using a multivibrator circuit. [Problems to be Solved by the Invention] However, supply
Is generated by the F-V conversion circuit according to the difference in the signals
An error occurs in the converted DC voltage. For example, horizontal sync signal
As shown in Figure 2-a. Separate signal (without vertical sync signal)
And the composite sync signal (with vertical sync signal) in Figure 2-B is F-
Comparing the case of input to the V conversion circuit,
The signal is the horizontal sync signal within the period of the vertical sync signal pulse width.
Since it does not exist, the number of counting pulses decreases and the F-V conversion times
The converted DC voltage for control generated in the path is
A control variable generated by counting the rate signal.
It becomes lower than the DC voltage. That is, the same horizontal
Even at the sync frequency, there is no difference between the separate signal and the composite sync signal.
There is a difference in the replacement voltage. This difference is the vertical sync pulse width
Is longer, the screen becomes larger, and the screen phase shift and horizontal oscillation frequency
There was a problem such as the deviation of. The present invention has the above-mentioned drawbacks.
Frequency provided in the previous stage of the F-V conversion circuit to eliminate the
The separation circuit and the signal selection circuit allow
The period of the direct sync signal is detected, and the horizontal drive pattern is detected within that period.
It is characterized in that a signal obtained by capturing the loose signal is input to the FV conversion circuit . FIG. 1 is a diagram showing an embodiment according to the present invention , and FIG.
Input signal waveform supplied, FIG. 3 and FIG. 4 are in FIG.
It is a waveform diagram of each main point, which will be described below with reference to the drawings. The signal of FIG. 2-a input to point A of FIG .
(Horizontal sync signal) is the frequency for extracting only the vertical sync signal
Separated circuit 2 (resistor R, capacitor C and transistor)
The horizontal sync frequency component is
Removed, point C goes low and NAND gate
In the NAND gate II of the configured signal selection circuit 3,
Supplied. Therefore, the NAN of the signal selection circuit 3 from the point B
Horizontal drive signal (water
(Always supplied from the flat oscillator circuit) is cut A
Directly to the NAND gate I of the signal selection circuit 3
The signal being output is output to point D and supplied to the FV conversion circuit 1.
Is supplied and a converted voltage is generated. [0007] Next, the composite synchronizing signal of FIG. 2 (b) is subjected to the point A
When supplied, the frequency separation circuit 2 removes the horizontal sync frequency component.
High level only for the period of vertical sync pulse width at point C
Signal is obtained and sent to the signal selection circuit 3.
It In this state, the signal is directly supplied from the point A to the signal selection circuit 3.
Within the vertical sync signal period of the composite sync signal
The horizontal drive signal supplied to point B regardless of the length of the sync signal width.
The signal as shown in Fig. 4 with the live signal captured appears at point D.
Applied to the F-V conversion circuit 1 to generate a converted voltage.
It As described above, according to the present invention, the F-
The V conversion circuit includes a frequency separation circuit 2 and a signal selection circuit 3.
Then, the signal corrected for the difference in signal form is F-V conversion circuit 1
Since the input voltage is input to the converter, there is no error in the converted voltage, and the circuit is simple.
It is possible to obtain effects such as being converted.
【図面の簡単な説明】
【図１】本発明になるＦ−Ｖ変換回路の実施例図であ
る。
【図２】入力信号の波形図である。
【図３】入力信号がセパレート信号の場合の各主要点の
波形図である。
【図４】入力信号が複合同期信号の場合の各主要点の波
形図である。
【符号の説明】
１：Ｆ−Ｖ変換回路
２：周波数分離回路
３：信号選択回路
４：水平ドライブ回路
５：水平偏向回路
Ｒ：抵抗
Ｃ：コンデンサー
Ｑ：トランジスターBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an embodiment diagram of an FV conversion circuit according to the present invention. FIG. 2 is a waveform diagram of an input signal. FIG. 3 is a waveform diagram of each main point when the input signal is a separate signal. FIG. 4 is a waveform diagram of each main point when the input signal is a composite synchronizing signal. [Explanation of Codes] 1: F-V conversion circuit 2: Frequency separation circuit 3: Signal selection circuit 4: Horizontal drive circuit 5: Horizontal deflection circuit R: Resistor C: Capacitor Q: Transistor
Claims (1)
圧変換回路において、設けられた周波数分離回路と信号
選択回路とによって信号形態の相違を補正した信号を供
給することを特徴とした周波数−電圧変換回路。(57) [Claims] A frequency separation circuit and a signal provided in a frequency- voltage conversion circuit used for an auto-scan display device.
Provide a signal whose difference in signal form is corrected by the selection circuit.
Frequency is characterized by feeding - voltage converting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3284239A JP2556404B2 (en) | 1991-08-06 | 1991-08-06 | Frequency-voltage conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3284239A JP2556404B2 (en) | 1991-08-06 | 1991-08-06 | Frequency-voltage conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0540450A JPH0540450A (en) | 1993-02-19 |
| JP2556404B2 true JP2556404B2 (en) | 1996-11-20 |
Family
ID=17675971
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3284239A Expired - Lifetime JP2556404B2 (en) | 1991-08-06 | 1991-08-06 | Frequency-voltage conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2556404B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02265318A (en) * | 1989-04-05 | 1990-10-30 | Hitachi Ltd | Frequency-voltage conversion circuit |
-
1991
- 1991-08-06 JP JP3284239A patent/JP2556404B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0540450A (en) | 1993-02-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960611 |