JP2555967B2 - Floating point adder / subtractor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point adder / subtractor, and more particularly to addition and subtraction of binary numbers in floating-point representation represented by two's complement representation, each of which has a significand and a exponent. Floating point adder / subtractor

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional floating point adder / subtractor. A conventional floating-point adder / subtractor receives a register file 1 that stores two pieces of floating-point data to be added and subtracted, and mantissa data S2 and S3 of these two pieces of floating-point data to add and subtract, The arithmetic unit 2 that outputs the operation result data S5 and the overflow bit S1, the register 4 that stores the overflow bit S1, and the mantissa operation result data S4 before normalization are received as inputs, and various shift operations are performed according to instructions of the firmware. , And a barrel shifter 5 for outputting shift result data S6.

Here, the floating point data has a structure as shown in FIG. 3, for example. In the figure, the floating point data comprises an exponent part p and a mantissa part m. In the exponent part p, the most significant bit p1 is a sign bit, and similarly, the most significant bit m1 of the mantissa part m is a sign bit. In addition, the exponent part p and the mantissa part m are binary numbers expressed in two's complement notation.

Returning to FIG. 2 again, in this conventional floating-point adder / subtractor, first, mantissa data S2 and S3 of two floating-point data to be added / subtracted are read from the register file 1 respectively, and the arithmetic unit is operated. Addition or subtraction is performed at 2. As a result of this addition or subtraction, the computing unit 2 generates an overflow bit S
1 is stored in the register 4, and the operation result data (mantissa data before normalization) S5 is stored in the register file 1.

Next, the firmware refers to the register 4, and if the overflow bit S1 is set, the operation result data S4 (same as S5) which is the mantissa data before normalization stored in the register file 1. Data) is input to the barrel shifter 5 and logically shifted to the right by 1 bit (the normal barrel shifter 5 has arithmetic shift, logical shift and circular shift functions), and the mantissa data S6 of the shift result is stored again in the register file 1. .

Finally, the adder / subtractor takes out the shifted mantissa data S6 from the register file 1 and outputs the most significant bit (the most significant bit of the normalized data is the second most significant bit) created by the firmware. (Logical inversion) and the logical sum operation in the arithmetic unit 2
Obtain the normalized mantissa data. That is, in the conventional floating-point adder / subtractor, the normalization process at the time of overflow of the mantissa part was performed by the firmware.

[0007]

As described above, in the conventional floating point adder / subtractor, the normalization process when the mantissa overflow occurs in the arithmetic unit 2 is performed by the register 4
The firmware determines whether or not it is an overflow by referring to, and if it is an overflow, it branches to the control firmware for data normalization, and the firmware at the branch destination normalizes the mantissa at the time of overflow, and shifts to the right by 1 bit. To the barrel shifter 5,
Further, the firmware generates the most significant bit and synthesizes it with the most significant bit of the data after shifting by 1 bit to the right, thereby performing the mantissa normalizing process.

However, since a large amount of operation data requires normalization processing when such an overflow occurs (addition with the same exponent part and same sign of mantissa part and subtraction with different sign), overflow occurs. The conventional floating-point adder / subtractor, which requires a large number of firmware steps for time normalization, has a problem that the operation speed becomes slow.

The present invention has been made in view of the above points,
An object of the present invention is to provide a floating-point adder / subtractor that can perform high-speed operation by performing normalization processing when an overflow occurs in hardware.

[0010]

In order to achieve the above object, the present invention provides a register file and mantissa data of first and second floating point data respectively inputted from the register file, and addition or subtraction thereof. The operation result data obtained by performing the above is output and stored in the register file, and when the overflow occurs, the operation unit that outputs the overflow bit, the register that stores the output overflow bit of the operation unit, and the overflow bit are stored. While the input operation result data is shifted to the right by 1 bit according to the output of the register when it is present, the logically inverted data of the most significant bit of the operation result data is combined with the empty most significant bit, and the combined data is normalized mantissa. Barrel shifter that outputs as part data and stores it in the register file And, far as the barrel shifter
General-purpose ballast that performs various shift operations according to the instructions of the hardware
It is configured to share the lucifer .

[0011]

According to the present invention, when an overflow bit is set in the register by the addition or subtraction of the mantissa data of the first and second floating point data by the arithmetic unit and the overflow bit is set in the register, the arithmetic result data is transferred by the barrel shifter. Since it shifts to the right by one bit and combines the most significant bit of the vacant space with the logically inverted data of the most significant bit of the operation result data, the mantissa part normalization processing when an overflow occurs in hardware must be performed. Therefore, there is no need to branch the firmware to perform the mantissa normalization process, and the same firmware as when the overflow does not occur can be processed.

[0012]

Next, an embodiment of the present invention will be described.
FIG. 1 shows a block diagram of an embodiment of the present invention. In FIG.
The same reference numerals are given to the same components as. As shown in FIG. 1, the floating point adder / subtractor of this embodiment comprises a register file 1, an arithmetic unit 2, a barrel shifter 3 and a register 4. The register file 1 stores two pieces of floating point data for addition or subtraction, operation result data and intermediate data at the time of operation.

Further, in this embodiment, the barrel shifter 3 receives the mantissa operation result data S4 before normalization as an input,
Various shift operations (arithmetic shift, logical shift, circular shift, etc.) are performed according to the instructions of the firmware, but the output of the register 4 is also received as an input, and when the overflow bit is set in the register 4, the input before normalization is input. Unconditionally to the right of the mantissa calculation result data S4 of 1
Bit shift is performed, and the logically inverted data of the most significant bit of the operation result data is combined with the most significant bit that has been made available.

Next, the operation of this embodiment will be described.
For example, the mantissa data S2 and S3 of, for example, 40 bits or 24 bits of the two pieces of floating point data read from the register file 1 are 2's complement numbers whose most significant bit is a sign bit as described with reference to FIG. It is a binary number represented by a display. These mantissa data S2
And S3 are input to the computing unit 2 where they are added or subtracted.

As a result, the obtained operation result data S5
Is stored in the register file 1 by the arithmetic unit 2. Further, when an overflow occurs during the addition / subtraction by the arithmetic unit 2, the overflow bit S1 is stored (set) in the register 4. Here, when an overflow occurs, the most significant bit of the operation result data (mantissa part data) S5 (S4) becomes a logical value that is the logical inversion of the original sign bit.

Therefore, the firmware reads out the operation result data S4 (same as S5) from the register file 1 and inputs it to the barrel shifter 3 to shift it for normalization processing. That is, the normalization process is performed on the mantissa part data S.
This is a process of shifting so that the most significant value of the mantissa having a logical value different from that of the most significant bit comes to the bit (the second bit) next to the most significant bit of 4 (that is, the sign bit),
In this embodiment, when the barrel shifter 3 receives the overflow bit S1 output from the register 4, it unconditionally shifts the input mantissa part data S4 (calculation result data S5 before normalization processing) to the right by one bit, and by the shift. The logically inverted data of the most significant bit of the input mantissa data is combined with the vacant most significant bit, and the combined data is output as the normalized mantissa data S6.

The mantissa part data S6 has a sign bit having the same logical value as the original sign bit in the most significant bit, and the second and subsequent bits are the normalized operation result data. Stored in. This completes the calculation. As described above, according to the present embodiment, since the barrel shifter 3 performs the normalization process when the overflow occurs, the step and the process of branching to the firmware for the normalization process that is conventionally required when the overflow occurs No more steps are needed, regardless of whether the mantissa overflow occurs,
Normalization can be performed with the same firmware.

It should be noted that, in the overflow process of the mantissa part, the exponent part naturally needs a process of adding or subtracting 1, but the description is omitted because it is not directly related to the gist of the present invention .

[0019]

As described above, according to the present invention,
By performing the mantissa normalization process when an overflow occurs with hardware called barrel shifter, the firmware does not need to branch and perform the mantissa normalization process.
Since the processing can be performed by the same firmware as when the overflow does not occur, the number of firmware steps can be greatly reduced as compared with the conventional method, and therefore floating point addition / subtraction can be performed faster than the conventional method.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

FIG. 3 is an explanatory diagram of an example of a floating point display format.

[Explanation of symbols]

 1 register file 2 arithmetic unit 3 barrel shifter 4 overflow bit storage register

Claims (2)

(57) [Claims] 1. A register file that stores at least first and second floating-point data, and mantissa data of the first and second floating-point data are input from the register file, respectively, and their addition is performed. Or an arithmetic unit that outputs the arithmetic result data obtained by performing the subtraction and stores it in the register file, and outputs an overflow bit when an overflow occurs; a register that stores the output overflow bit of the arithmetic unit; Output and the operation result data is input from the register file, and the output of the register when the overflow bit is stored shifts the input operation result data to the right by 1 bit, and at the same time, creates a vacant most significant bit. , The logic inversion data of the most significant bit of the operation result data is synthesized, and And it outputs the formed data as normalized mantissa data have a barrel shifter to be stored in the register file, file as the barrel shifter
A general-purpose firmware that performs various shift operations according to firmware instructions.
Floating point adder / subtracter characterized by sharing the rel shifter. 2. The first and second floating-point data each have a mantissa part and an exponent part each having a sign bit, and 2
2. The floating point adder / subtractor according to claim 1, wherein the floating point adder / subtractor is a binary number represented by a complement notation of.