JP2554605B2 - Wideband signal combiner - Google Patents

Abstract

In a switching device for broadband signals with a crosspoint matrix in FET technology provided with input driver circuits (E) and output amplifier circuits (A), switching elements (Kij) having a relatively great forward resistance are provided; the output amplifier circuits (A) in each case exhibit a chain circuit of a CMOS inverter (J) and of a D-type flip flop (DK) and a switch (S) having a relatively low forward resistance via which in each case in a preliminary phase of a bit through-connection period, the line leading from the switching element (Kij) to the inverter input is at least approximately recharged to the potential corresponding to the switching threshold of the inverter (J) and, starting from this, is recharged to the potential corresponding to the bit switched through in each case in the subsequent main phase. <IMAGE>

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention has a connection point matrix formed by FET technology, and may have one input driver circuit at each of its input terminals, and its output terminal. It relates to a broadband coupling device, each provided with one output amplifier circuit.

[Conventional technology]

Recent developments in communication technology have led to the development of optical waveguides that can be used as a transmission medium in the range of subscriber lines, especially for narrow-band communication services such as 64 kbit / s digital telephones and broadband communication services such as 140 Mbit / s video telephones. It has led to transmission and switching systems that make up an integrated service network for the provided narrowband and broadband communication services. The exchange is then preferably provided side by side with a narrow-band signal coupler and a wide-band signal coupler with a common control unit (see German Patent DE 2421002).

In connection with a wideband signal-time division multiplexing-combining device in which the connecting points are each used for multiple connections by means of time division multiplexing, each two conductors is formed as a bistable D multivibrator. It is known to connect by gate elements which are switched on and off by individual memory cells. The individual memory cells of these junctions, which are supplied with the corresponding clock signal at the clock input, are then driven in only one coordinate direction, in particular at their D input (Pfannschmidt). Written by Arbeitsgeschwindigkeitsgre
nzen von Koppelnetzwerken fr Breitband−Digital
signale) ”, dissertation, Braunschweig, 1978
Year, Figure 6.7 and Figure 6.4). Taking into account the time-division multiplexing factor of about 4 to 8 reachable at a bit rate of 140 Mbit / s and the circuit technology required in doing so, currently for wideband signal exchange via individual connection points. Preference is given to purely spatial coupling devices in which the connections to be passed through are exclusively spatially separated from one another.

A pure wideband signal-spatial combiner is constructed as a connection point matrix according to C-MOS technology, which is provided with an input amplifier and an output amplifier, at which connection elements the respective decoder points are decoder controlled. Controlled by the holding memory cells of the above, wherein the coupling elements are each configured as a C-MOS transfer gate (C-MOS transmission gate) (ISS'84 Conference Paper 23Cl, FIG. 9), a pure space. The individual holding memory cells of the connecting points of the combiner are driven in two coordinates from the row decoder and the column decoder via the individual drive lines for the respective rows or columns (Pfanschmidt, supra, FIG. 6.4). The output amplifiers provided in the coupling matrix are (at least) 1 of the associated matrix lines.
It may also be activated in connection with the activation of one connection point (French Patent A-2,365,263, FIG. 5).

Furthermore, it is not possible to provide digital coupling points in the form of a three-state inverter in a wideband signal-spatial coupling point matrix (Electronics, December 1983 15).
, Page 88/89) in general form. Although its specific implementation is not described in the above document, it requires a large number of transistors in any case.

A wideband signal-space coupling device with a coupling point matrix according to FET technology, in order to keep transistor costs particularly low in the realization of the individual coupling points,
Each of the coupling elements, from the memory cell to its gate electrode, exceeds the upper (limit) value of the signal to be cross-connected by a voltage greater than the transistor-pinch-off voltage or the lower side (limit) of the signal to be cross-connected. A single n-channel whose value is given a blocking potential below the level produced by raising the transistor by the pinch-off voltage-a wideband signal formed by the transistor-
Spatial coupling devices have already been proposed (cf. DE 3604605).

Thus, the coupling elements, which are provided in the coupling point matrix and are each controlled by one coupling point individual holding memory cell in a simple manner, have a minimum transistor cost and do not require an inverter and also a C-MOS transfer. Without the need to provide a p-channel transistor in the gate (which requires a large area because of its high resistivity), and therefore also with a correspondingly small footprint (which is of particular significance for integration), and It can be realized with a small circuit capacity.

In order to further reduce the size of the circuit and thus also the occupied area, a separate junction memory cell driven in two coordinates by two drive decoders (row decoder, column decoder) has one n-channel transistor and two memory cells. It is formed by cross-coupled inverter circuits, in which case one inverter circuit is connected on the input side to the decoder output end of one of the drive decoders via an n-channel transistor. A transistor has its control electrode fed to the output signal of the associated decoder output of the other drive decoder, and in this case one inverter circuit is connected on the output side to the control input of the associated coupling element. Signal-space combiners have also been proposed.

170 Mbi via the previously proposed wideband signal-spatial combiner as described above with a connection point matrix according to FET technology having, for example, 64 inputs and 32 outputs.
Any asynchronous signal with a bit rate up to the order of t / s, and thus also especially a signal filling the so-called H4 channel (eg 140 Mbit / s), respectively has one input and one output (or distributed service) respectively. In some cases, there may be transit connections between many outputs). However,
Not only can each replace all one H4 channel,
It has become desirable to be able to also exchange sub-channels, for example so-called H3 channels for 34 Mbit / s signals. In principle, such a subchannel exchange is provided with a demultiplexer in front of the combiner that decomposes each (H4) channel into its (H3) subchannels, and also a multiplexer that combines the subchannels into one channel again. It is achieved by providing after the coupling device. The coupling device itself then replaces each individual subchannel individually, which is subject to a corresponding increase in the number of input and output terminals of the coupling point matrix,
In this example, instead of 64 × 32 connecting points, for example, 256 × 1
It must have 28 points of attachment. Since in this case a full distribution service capability of the connection point matrix is required, each (eg 256) input end of one such connection point matrix is connected to every (eg 128) output end of the connection point matrix. Causes the problem that they must be loadable at the same time. This in itself requires 256 overly large input driver circuits, the lateral current and power dissipation of which will make manufacturability of such junction point matrix modules difficult.

[Problems to be solved by the invention]

The object of the present invention is to provide a wideband signal-combining device which can meet the requirements outlined above without difficulty.

According to the invention, the object is, according to the invention, to provide a wideband signal combiner of the type mentioned at the beginning, in which the connecting point is an internal resistance applied to one matrix input in pass-through connection. At least one negative C-, which is formed by a coupling element each having a larger internal resistance than the other, and an output amplifier circuit is inserted in the output line concerned.
A MOS logic operation element, preferably a C-MOS inverter, and one holding element, preferably a D flip-flop, each connected in cascade, and a main electrode connected to the input terminal of the negative C-MOS logic operation element. A switch having a smaller passage resistance than the resistance of one coupling element, the control electrode of the switch having one bit passage connection time width to one previous stage and one original passage connection stage. One joint field-pass connection clock to be divided is given, and the corresponding output line of the joint point matrix is at least approximately at each preceding stage via the switch to a potential corresponding to the switching threshold of the logical operation element. Bits that are recharged and are connected from each of these potentials via their respective coupling elements in the subsequent pass-through stage. It is achieved by the broadband signal coupling apparatus characterized by being recharged to the corresponding potential.

It should be mentioned here that scanning amplifiers (sense amplifiers) operating on the so-called auto-zero principle are known per se (eg US Pat. No. 4,443,381).

The problem of one particularly advantageous embodiment of the broadband signal combiner is not mentioned here. The present invention shows one way for this.

The present invention, which takes advantage of the fact that C-MOS logic elements have a high voltage amplification near their switching thresholds, allows the logic to operate without excessive demands on the input driver circuits and their side current and power dissipation. A small signal change width and a respective logical operation are produced at each output of the arithmetic element, and thus also at the output line portion connected thereto, in order to cause a unique transition from one signal state to the other signal state. There is the advantage that a small recharge of the output line portion leading to the element input is sufficient.

In another embodiment of the invention, the other main electrode of the switch can be connected to the output of the logical operation element.
Alternatively, the other main electrode of the switch is connected to the output of a special reference voltage generator, which
In another embodiment of the present invention, it may be formed by a dimensioned and fed back C-MOS inverter in the same manner as the above-mentioned logical operation element is formed, and in some cases, a plurality of switches are connected to a common reference voltage. It can also be used as a generator.

〔Example〕

Hereinafter, the present invention will be described in more detail with reference to embodiments shown in the drawings.

In FIG. 1, to the extent necessary to understand the present invention,
1 shows an overview of a wideband signal-space combining device according to the invention. The input driver circuits El ... Ej ... are connected to the input ends el ... ej ... en leading to the column lines sl ... sj ... sn of one connection point matrix.
En is provided, and the row line zl… zi of the connection point matrix
Output amplifier circuits Al ... Ai ... Am are provided at output terminals al ... ai ... am to which zm is connected. The knot point matrix has knot points KPll ... KPij ... KPmn, each of these knot elements holding a respective knot point (at the knot point KPij), as described in detail with respect to the knot point KPij of the knot element Kij. It is controlled by the memory cell Hij, and its output s leads to the control input of each coupling element (Kij at the coupling point KPij).

The holding memory cells ... Hij ... Are driven in two coordinates by two drive decoders, namely a row decoder DX and a column decoder DY, via corresponding drive lines xl ... xi ... xm; yl ... yj ... yn.

As is apparent from FIG. 1, both drive decoders DX and DY are given common connection point row or connection point column address to one matrix (row or column) of connection points from input registers RegX and RegY, respectively. A "1" drive signal may be applied to the drive lines corresponding to the respective connection point addresses.
Due to the simultaneous occurrence of the row driving signal “1” and the column driving signal “1” at the intersection of the matrix row and the matrix column, a holding memory cell located there, for example Hi
j is activated, so that the coupling element controlled by the holding memory cell (Hij) in question, eg Kij, becomes conductive.

The drive decoder DX is again used so that the coupling element Kij devised as an example is again blocked during the formation of the connection concerned.
Is given the row address of interest from the input register RegX,
Therefore, the row decoder DX again applies the row drive signal "1" on its output line xi, and at the same time the column decoder DY is supplied from its input register RegY with eg the empty address or the column address of the unconnected junction, and The column decoder DY provides the column drive signal "0" on its output line yj. The co-occurrence of the row drive signal "1" and the column drive signal "0" resets the holding memory cell Hij and consequently blocks the coupling element Kij controlled thereby.

As is more apparent from FIG. 2, the memory cell Hij driven in two coordinates by both drive decoders (row decoder DX and column decoder DY in FIG. 1) is one n-channel-transistor Tnh and two. It is formed by cross-coupled inverter circuits Tn ′, Tnl ′; Tn ″, Tnl ″, and one of the two inverter circuits (Tn, Tnl ′) is one drive decoder (DY in FIG. 1) on the input side. Is connected to the decoder output terminal yj attached to the other of the drive channels via the n-channel transistor Tnh, and this n-channel transistor Tnh has its control electrode attached to the decoder output terminal of the other drive decoder (DX in FIG. 1). The output signal of xi is applied and, on the other hand, the other of the two inverter circuits leads on the output side to the control input of the associated coupling element Kij.

The coupling element Kij passes to the gate electrode between the column line (input line) sj and the row line (output line) zi, for example by one tri-state driver or as also shown in FIG. Transit connection potential (“H” level) that exceeds the upper (limit) value of the signal to be connected by a voltage greater than the transistor-pinch-off voltage or between the column line (input line) sj and the row line (output line) zi Formed by a single n-channel transistor Tnk which is provided with a blocking potential ("L" level) below the level caused by the transistor-pinch-off voltage raising the lower (limit) value of the signal to be cross-connected. Good. The realization of such a holding memory cell Hij and the coupling element Kij has already been described in another document (DE 3604605) and therefore need not be described further here. The important thing here is
The passing resistance of such a coupling element is only larger than the internal resistance given to the matrix column line sj of the input driver circuit Ej (FIG. 1) provided therein.
This can easily be achieved by a corresponding design of the transistor geometry.

For this reason, the write switch WR is connected after the output terminal of the column decoder DY in FIG.
Is closed only on the appearance of a write command on the release line wr, and after that, in some cases, "1" drive signal ("L") that occurs at the decoder output and "0" drive that occurs at other decoder outputs The signal ("H") is connected with low resistance to the individual column drive lines yl ... yj ... yn, so that the coupling elements respectively driven in the above-mentioned manner reach a connection or blocking state.

On the other hand, the binding state of one row should simply be read out from the binding points of the binding point matrix, so that the row drive line in question, eg line xi, is again connected as in the case of connection formation or disconnection. , If a "1" drive signal ("H") is given, the write switch WR is opened because no write command appears on the release line wr, and as a result, the column drive lines yl ... yj ... yn become column decoders. No control potential is now received from DY. The holding memory cell Hj of the relevant connection point row ... Kpij ... which is still unlocked from its gate electrode by the row drive signal “H” -via the n-channel transistor Tnh (FIG. 2) of the holding memory cell The signal state at that time in the Hij is the column drive line (y in FIG. 2).
An "L" potential can appear on more than one column drive line yl ... yj ... yn (FIG. 1), which is connected in transit to j) and in error-free operation. As also shown in FIG. 1, the address of this column drive line, and thus also the address of the connection point in question, is obtained by the coder CZ and can then be transmitted to the subsequent register RegZ.

The output amplifier circuit Ai provided between one row line zi (FIGS. 1 and 2) of the connection point matrix and the subsequent output terminal ai (FIG. 1) is shown in FIGS. 3 and 4. As shown therein, a C-MOS inverter J formed by two MOS transistors Tp, Tn inserted between the relevant output line portions zi and ai and one edge controlled D flip-flop. It has a cascade circuit with the transistor DK and a switch formed by another MOS transistor S, and the pass resistance of this transistor-switch is the pass resistance of one coupling element Kij (FIGS. 1 and 2). Smaller than The switch-transistor S is connected at its one main electrode to the input zi of the inverter J. Its control electrode, together with the clock input C of the D flip-flop DK, has one bit pass connection time width, one pre-stage pv and one main stage ph, as also shown below in FIG. It is connected to a clock line pv which can be given a clock to divide into.

In the output amplifier circuit Ai shown in FIG. 3, the other main electrode of the switch-transistor S is connected to the output terminal of the inverter J and thus also to the input terminal D of the D flip-flop DK. During the previous step pv (see FIG. 5) the switch-transistor S connecting the output (D) of the inverter J to its input is conducting, so the matrix row line zi leading to the input of the inverter is the inverter J. Is charged to a potential corresponding to the switching threshold of. Starting from this state, then, in the subsequent main stage ph (see FIG. 5) in which the switch-transistor S is cut off, the associated column line sj
The matrix row line zi, which leads to the input of the inverter J via the coupling element Kij (FIGS. 1 and 2), is thereby recharged to the potential corresponding to the bit connected to it. Since the inverter J has a high voltage amplification factor in the vicinity of its switching threshold, the inverter output terminal (the input terminal D of the D flip-flop DK) may have a unique signal state from one signal state to the other signal state in some cases. A small recharge of the matrix row line zi is sufficient to cause the transition, and this signal state is passed from the D flip-flop DK by the clock edge at the end of the main phase and thus also the associated output of the coupling device ai. Is given to.

The resistance of both inverter-transistors Tp, Tn must be so low that the potential of the matrix row line zi should be closer to the switching threshold of the inverter J during the previous stage pv called the auto-zero stage. However, the associated inverter-transverse current and the resulting loss of power, on the other hand, if inverter J is designed as having a higher resistance,
Can be reduced. In this case, the main stage ph (see Figure 5)
At the beginning of the inverter, there remains a potential difference between the potential obtained at the inverter input zi and the inverter-switching threshold, which requires extra time for the recharging of the line to exceed the switching threshold. Therefore, it is necessary to optimize the trade-off between critical power loss and switching time when dimensioning a circuit.

The signal curve obtained in the output amplifier circuit Ai according to FIG. 3 is shown in principle in FIG. FIG. 5 starts from the signal course shown on the curve sj underlying the bit sequence -1,0 on the matrix column line sj (FIGS. 1 and 2) and shows how the input driver operates. The changes in the signal course involved are indicated by dashed and dotted lines. Curve in Fig. 5
zi shows the potential course occurring at the inverter input zi (FIG. 3), and the curve D in FIG. 5 shows in the output amplifier circuit Ai according to FIG. The signal course occurring at the input D of the D flip-flop DK is shown. A switching threshold of the inverter J (FIG. 3) is shown by a curve T shown by a broken line in FIG.

The same signal course as outlined in FIG. 5 also occurs in the output amplifier circuit Ai constructed in the manner shown in FIG. In the output amplifier circuit Ai according to FIG. 4, which corresponds to the circuit arrangement according to FIG. 3 with respect to the connection of the cascade connection of the C-MOS inverter J and the D flip-flop DK and the control electrode of the switch-transistor S, the switch-transistor S is Similarly, one of the main electrodes is connected to the inverter input terminal zi, while the other main electrode is connected to the output terminal b of the reference voltage generator B. During the previous step pv (see FIG. 5), the matrix row line zi leading to the input terminal of the inverter J is switched by the reference voltage generator B through the switch-transistor S which is conducting. It is recharged to the potential corresponding to the threshold. Since this recharging process is no longer performed by the inverter J itself, the inverter J can be designed with a high resistance value without penalizing the recharging process. In the subsequent main phase ph (see FIG. 5), the third phase has already been reached.
In the same way as explained in the figure, the attached column line sj (first
(FIGS. And 2) via the coupling element Kij (FIG. 1) to the input end of the inverter J, the matrix row line zi
Are thereby recharged to the potential corresponding to the bit connected through.

As the reference voltage generator B, as is apparent from FIG. 4, negative feedback C- is dimensioned in the same manner as the inverter J and is blocked by a capacitor to achieve a low dynamic internal resistance. MOS
An inverter may be provided. An anti-coupled (connected as a voltage follower) difference amplifier is inserted in the connection line from the negative feedback inverter to the capacitor. This difference amplifier is not shown in FIG. As shown in FIG. 4, one common reference voltage generator B may be provided for a plurality of switch-transistors S. Although not shown in FIG. 4, a plurality of reference voltage generators may be provided distributed within one broadband signal combiner according to the present invention.

Last but not least, FIGS. 3 and 4
In the embodiment outlined in the figures, one D flip-flop (DK) may be provided as each holding element in the cascade circuit of the C-MOS inverter and the holding element. However, the present invention is not limited to such an embodiment. On the contrary, the holding element may also be realized in another way, for example by a capacitor, which may be realized by the input capacitance of one (another) C-MOS inverter, and (at least one) C-
Instead of a MOS inverter, (at least) one other negative C-MOS logic element may be provided.

[Brief description of drawings]

1 and 2 are schematic diagrams of a wideband signal coupling device and its coupling point, FIGS. 3 and 4 are detailed diagrams of an embodiment of the circuit according to the present invention, and FIG. 5 shows its signal course. It is a figure. al to ai to am ... Connection point matrix output end, output end part, Al to Ai to Am ... Output amplifier circuit, b ... Reference voltage generator output end, B ... Reference voltage generator, C ... Hold Memory, CZ ... Corder, DK ... D flip-flop, DX ...
... Row decoder, DY ... Column decoder, el ~ ej ~ en ... connection point matrix input line, El ~ Ej ~ En ... input driver circuit, Hij ... holding memory cell, J ... C-MOS inverter, K …… Comparator, Kij …… Coupling element, KPll to KPi
j to KPmn …… coupling point, pv …… clock line, R1, R2 …… resistor, RegX, RegY …… input register, RegZ …… register,
sl ~ sj ~ sn ... Connecting point matrix column line (input column), S
...... Transistor switch, T ... Switching threshold, Tn ', Tn ", Tnl', Tnl" ... (N-MOS) inverter circuit, n-channel inverter circuit, Tnh, Tnk ... n
Channel-transistor, Tp, Tn ... C-MOS transistor, U _DD , V _CC ... Supply potential, WR ... Write switch,
wr …… Release line, xl ～ xi ～ xm …… Row decoder output end,
Drive line, yl-yj-yn ... Column decoder output end, drive line, zl
〜Zj〜zn …… The line of the connecting point matrix and the output line.

Claims (7)

(57) [Claims] 1. A broadband coupler having a coupling point matrix according to FET technology, wherein one output amplifier circuit (Ai) is provided at each output end (zi to ai) of the coupling point (KPij). It is formed by coupling elements (Kij) each having one internal resistance larger than the internal resistance given to one matrix input terminal (sj) in the pass-through state, and an output amplifier circuit (Ai) is provided for the output. At least one negative C-MOS logical operation element and one holding element (DK) inserted in the line (zi to ai)
, Each of which is connected to the input terminal of the negative C-MOS logical operation element by the main electrode, and one switch (S) having a smaller passage resistance than the resistance of one coupling element (Kij). And the control electrode of the switch (S) divides the time width of one bit-passage connection stage into one pre-passage stage (pv) and one original pass-through stage (ph), one combined field pass connection A clock is given, and the output line (zi) of the connection point matrix at each previous stage (pv) is at least approximately via the switch (S) to the switching threshold of the logical operation element (J). It is recharged to the corresponding potential and, starting from this potential, is recharged in the subsequent pass-through stage (ph) via the respective coupling element (Kij) to the potential corresponding to the bit respectively passed through. Ruko Broadband signal coupling device according to claim. 2. The wideband signal coupling device according to claim 1, wherein the logical operation element is formed by one C-MOS inverter (J). 3. Wideband signal coupling according to claim 1 or 2, characterized in that the other main electrode of the switch (S) is connected to the output of the logical operation element (J). apparatus. 4. The other main electrode of the switch (S) is connected to the output end (b) of one reference voltage generator (B). A wideband signal combining device according to the item. 5. A plurality of switches (S) is provided with one (or more) reference voltage generator (B), which is common to each of the plurality of switches (S). Wideband signal combiner. 6. The reference voltage generator (B) is formed by a dimensioned and negatively fed back C-MOS inverter in the same manner as the inverter (J) of one cascade circuit. The wideband signal coupling device according to any one of the second, fourth, and fifth ranges. 7. A holding element is formed by a D flip-flop (DK) whose clock input is supplied with a coupled field passing connection clock, according to any one of claims 1 to 6. The wideband signal coupling device according to item 1.