JP2553032B2 - Charged particle beam deflection circuit - Google Patents

Charged particle beam deflection circuit

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Publication number
JP2553032B2
JP2553032B2 JP60055289A JP5528985A JP2553032B2 JP 2553032 B2 JP2553032 B2 JP 2553032B2 JP 60055289 A JP60055289 A JP 60055289A JP 5528985 A JP5528985 A JP 5528985A JP 2553032 B2 JP2553032 B2 JP 2553032B2
Authority
JP
Japan
Prior art keywords
main
sub
deflection
deflection system
drive amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60055289A
Other languages
Japanese (ja)
Other versions
JPS61214342A (en
Inventor
佐藤  裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Original Assignee
Nippon Kogaku KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Kogaku KK filed Critical Nippon Kogaku KK
Priority to JP60055289A priority Critical patent/JP2553032B2/en
Publication of JPS61214342A publication Critical patent/JPS61214342A/en
Application granted granted Critical
Publication of JP2553032B2 publication Critical patent/JP2553032B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 (発明の技術分野) 本発明は,電子ビーム露光装置等に用いられる荷電粒
子ビーム偏向系に関するものである。
TECHNICAL FIELD OF THE INVENTION The present invention relates to a charged particle beam deflection system used in an electron beam exposure apparatus or the like.

(発明の背景) 電子ビーム露光装置等に用いられる荷電粒子ビーム偏
向系に,要求される条件は(1)高分解能でかつ高安定
である事。(2)ダイナミツクレンジが大きい事。
(3)高速である事。の3つであるが,これらの要求
を,1つの偏向系で同時に満足するのが,困難な為,主偏
向及び副偏向系の2つの偏向系を用い描画領域(メイン
フイールド)を100〜10,000程度の小領域(サブフイー
ルド)に分割し描画する方法が従来よく採用されて来
た。この方式は前記条件の(1)と(2)の要求を満足
する主偏向系で,描画するサブフイールドの中心に荷電
粒子ビーム(以下単にビームと称す)を偏向し,このサ
ブフイールド内に含まれているパターンを前記条件の
(3)を満足する副偏向系で高速にビーム駆動して描画
する事により前記(1)〜(3)の3つの条件を,同時
に満足する事が出来るすぐれた方法である。すなわち,
主偏向系のダイナミツクレンジが大きく高分解能の駆動
系はセトリング(目標値に到達する迄の時間)に時間
が,かかるのでサブフイールドの移動の時にのみ使用
し,サブフイールド内のパターン描画は,ダイナミツク
レンジも小さく,分解能も低いので,高速駆動が可能な
副偏向系を使用して描画速度を上げる方法であつて,ト
ータルの描画時間を1つの偏向系で描画する場合に比べ
大幅に短縮する事が出来る方法である。
(Background of the Invention) The requirements for a charged particle beam deflection system used in an electron beam exposure apparatus and the like are (1) high resolution and high stability. (2) A large dynamic range.
(3) High speed. However, since it is difficult to satisfy these requirements with one deflection system at the same time, the drawing area (main field) is 100 to 10,000 by using two deflection systems, a main deflection system and a sub deflection system. A method of dividing into small areas (subfields) and drawing has been often used. This method is a main deflection system that satisfies the requirements (1) and (2) of the above conditions, deflects a charged particle beam (hereinafter simply referred to as a beam) to the center of a subfield to be drawn, and includes it in this subfield. It is an excellent feature that the three conditions (1) to (3) can be satisfied at the same time by performing beam writing at high speed on a sub-deflection system that satisfies the above condition (3) to draw the pattern. Is the way. That is,
Since the main deflection system has a large dynamic range and a high-resolution drive system takes time to settle (time to reach the target value), it is used only when moving the subfield, and the pattern drawing in the subfield is Since the dynamic range is small and the resolution is low, it is a method of increasing the drawing speed by using a sub-deflection system that can be driven at high speed, and the total drawing time is greatly reduced compared to the case of drawing with one deflection system. It is a method that can be done.

しかし,このような方法でも,主偏向系が,描画し終
わった,サブフイールドから,次に描画するサブフイー
ルドの中心の位置に,ビームをセトリングするのに,か
かる時間のロスは無視出来ず,特に,サブフイールド数
が多い場合の描画時間を,さらに短縮する為のネツクに
なつている。
However, even with such a method, the loss of time required for the main deflection system to settle the beam from the subfield after the drawing is completed to the position of the center of the subfield to be drawn next cannot be ignored, In particular, it is a net to further shorten the drawing time when the number of subfields is large.

(発明の目的) 本発明は、これらの欠点を解決し、主駆動アンプのセ
トリングに要する時間を実質的に短くすることにより、
トータルの描画時間の飛躍的短縮をはかる事を目的とす
る。
(Object of the Invention) The present invention solves these drawbacks and substantially shortens the time required for settling of the main drive amplifier.
The purpose is to dramatically reduce the total drawing time.

(発明の概要) 本発明の発明者は第1に,従来主偏向系の位置決めに
は,16〜18bitのDACが使用されていたがサブフイールド
に分割して描画する方式に於いて,ビーム偏向及び位置
決めに関する諸々の補正をすべて,副偏向系で行なうよ
うにすれば,主偏向系駆動回路は,各サブフイールドの
中央位置に対応する信号を発生するだけでよく,その場
合精度及び安定度さえ良ければ4〜7bit程度の高速のDA
Cを使用する事が出来る事。第2に主偏向系を駆動する
アンプは,ダイナミツクレンジが大きい為高電圧あるい
は大電流となり高速化には限界があるが,主偏向の位置
決め情報と主偏向アンプの出力信号間の誤差を検出して
副偏向系に帰還する事により,主偏向駆動アンプのセト
リングタイムを実質的に極めて短かくする事が出来る事
の2つの事項に着目し本発明を成すに至つた。
(Outline of the Invention) First, the inventor of the present invention firstly used a 16-18 bit DAC for positioning the main deflection system, but in the method of dividing into subfields and writing, If all corrections relating to positioning and positioning are performed by the sub-deflection system, the main-deflection-system drive circuit only needs to generate a signal corresponding to the central position of each sub-field, in which case accuracy and stability are even required. High-speed DA of about 4 to 7 bits if good
You can use C. Secondly, the amplifier that drives the main deflection system has a high dynamic range and a high voltage or a large current, which limits the speedup. However, it detects the error between the positioning information of the main deflection and the output signal of the main deflection amplifier. The present invention has been completed by paying attention to two points that the settling time of the main deflection drive amplifier can be substantially shortened by returning to the sub deflection system.

本発明はビーム偏向及び位置決めに関する補正を副偏
向系で行なう様構成し,さらに主偏向の位置決め情報
(目標データ)と主偏向用アンプの出力信号との誤差を
副偏向系に帰還し,該帰還誤差データに従つて副偏向系
を主偏向系と同時に動作することを技術的要点としてい
る。
The present invention is configured such that the beam deflection and the correction relating to the positioning are performed by the sub-deflection system, and further the error between the positioning information (target data) of the main deflection and the output signal of the main-deflection amplifier is fed back to the sub-deflection system. The technical point is to operate the sub deflection system at the same time as the main deflection system in accordance with the error data.

(実施例) 第1図は,本発明を用いた電子ビーム露光機の一実施
例を示す概略図であり,11は電子銃,12は第1コンデンサ
レンズ,13はブランキング偏向器,14は第2コンデンサレ
ンズ,3は主偏向器,7は副偏向器,15は対物レンズ,16はXY
ステージ,10は主偏向駆動回路,20は副偏向駆動回路であ
る。また第1図の各ブロツクの他にもいくつかの補正用
の電子光学系が設置されるのが普通であるが,本発明に
直接関係がないので省略する。
(Embodiment) FIG. 1 is a schematic view showing an embodiment of an electron beam exposure apparatus using the present invention, 11 is an electron gun, 12 is a first condenser lens, 13 is a blanking deflector, and 14 is 2nd condenser lens, 3 main deflector, 7 sub-deflector, 15 objective lens, 16 XY
The stage, 10 is a main deflection drive circuit, and 20 is a sub deflection drive circuit. In addition to the blocks shown in FIG. 1, a number of correction electron optical systems are usually installed, but they are omitted because they are not directly related to the present invention.

第2図は,本発明の実施例を示す回路であつて点線で
囲んだブロツク10が主偏向系駆動回路20が副偏向系駆動
回路30が偏向電子光学系である。実際の使用に当たつて
は電子ビームをX,Yの直交座標系の情報で偏向しなけれ
ばならないので,第1図の偏向系をもうひと組必要とす
る訳であるが,両軸ともまつたく同じ偏向系になるので
ここでは,簡略の為一軸の偏向系についてのみ説明す
る。
FIG. 2 is a circuit showing an embodiment of the present invention, in which a block 10 surrounded by a dotted line is a main deflection system drive circuit 20 and a sub deflection system drive circuit 30 is a deflection electron optical system. In actual use, the electron beam must be deflected by the information in the X, Y Cartesian coordinate system, so another set of deflection systems shown in Fig. 1 is required. Since only the same deflection system is used, only the uniaxial deflection system will be described here for simplification.

1は主偏向系のサブフイールドの中心位置情報(デジ
タル信号)をアナログ信号に変換する主偏向D/Aコンバ
ータ(以下D/AコンバータをDACと称す)であり,たとえ
ばメインフイールドを100×100個のサブフイールドに分
割描画する場合は最低7bitのDACが必要となるが位置精
度を上げる為10〜12bitの高速DACを使用するのが適当と
思われる。
Reference numeral 1 is a main deflection D / A converter (hereinafter, the D / A converter is referred to as a DAC) that converts the center position information (digital signal) of the subfield of the main deflection system into an analog signal, for example, 100 × 100 main fields. When dividing and drawing into subfields of, at least 7bit DAC is required, but it seems appropriate to use 10 to 12bit high-speed DAC in order to improve the position accuracy.

2は,主偏向器3の駆動用の主偏向器駆動アンプであ
る。主偏向器3が静電偏向ならば数百ボルトの高電圧,
電磁偏向ならば数アンペアの大電流出力が要求される
為,必要な精度にセトリングするのに数μsec〜数100μ
secの時間がかかる。従つて主偏向DAC1として高速のも
のが使用できるようになつても,この主偏向器駆動アン
プ2のセトリングを短縮できなければ全体の描画時間を
短かくする事はできない。
Reference numeral 2 is a main deflector drive amplifier for driving the main deflector 3. If the main deflector 3 is an electrostatic deflector, a high voltage of several hundred volts,
In the case of electromagnetic deflection, a large current output of several amperes is required, so it takes several μsec to several 100μ to settle to the required accuracy.
It takes sec. Therefore, even if a high-speed main deflection DAC 1 can be used, the total drawing time cannot be shortened unless the settling of the main deflector drive amplifier 2 can be shortened.

4は,主偏向器駆動アンプの誤差検出器であり主偏向
駆動アンプ2がセトリングするまでの間その入出力間の
誤差を出力する。
Reference numeral 4 denotes an error detector of the main deflector drive amplifier, which outputs an error between its input and output until the main deflector drive amplifier 2 settles.

5は,副偏向系を駆動してパターンを描画する為のパ
ターンの位置情報デジタル信号を逐次アナログ信号に変
換する副偏向DACであり高速変換機能が要求され,10〜12
bitの高速DACが使用される。
Reference numeral 5 is a sub-deflection DAC that sequentially converts the position information digital signal of the pattern for driving the sub-deflection system to draw a pattern into an analog signal, which requires a high-speed conversion function.
A bit high speed DAC is used.

6は副偏向器7の駆動用の副偏向器駆動アンプであ
る。本発明に於いてはこのアンプのダイナミツクレンジ
は2サブフイールド分の偏向電圧出力が必要となるが,
それにしても主偏向器駆動アンプ2の数10分の1のダイ
ナミツクレンジでよくそのセトリング時間は,主偏向器
駆動アンプ2のそれに比べ,はるかに短かくおよそ数百
nsecくらいである。
Reference numeral 6 is a sub-deflector driving amplifier for driving the sub-deflector 7. In the present invention, the dynamic range of this amplifier requires the deflection voltage output for two subfields.
Even so, the settling time is much shorter than that of the main deflector drive amplifier 2 and is about several hundreds, compared with that of the main deflector drive amplifier 2.
It is about nsec.

7は副偏向器で,高速応答が要求される為,ほとんど
の場合静電偏向器が用いられる。
A sub-deflector 7 is required to have a high-speed response, and therefore an electrostatic deflector is used in most cases.

8は補正用DACである。これまでの説明では省略した
が,実際にワークピース上に電子ビームでパターンを描
画する場合,ワークピースをXYステージ上に固定し,描
画するメインフイールドの中心が電子光学系の真下に来
るようにステージを移動する作業が必要となる。この時
ステージは確ずしも目標の位置には,止まらないので通
常は停止位置誤差検出器(不図示)の出力を電子ビーム
の偏向系にフイードバツクして,等価的に位置補正を行
なつている。主としてこの補正量をアナログ信号に変換
するのが,補正用DAC8である。また該補正用DAC8は外部
磁場の影響や偏向系の歪等を,補正する為にも用いられ
る。
Reference numeral 8 is a correction DAC. Although omitted in the explanation so far, when actually drawing a pattern on the workpiece with an electron beam, the workpiece is fixed on the XY stage so that the center of the main field to be drawn is directly below the electron optical system. Work to move the stage is required. At this time, the stage does not certainly stop at the target position, so normally the output of a stop position error detector (not shown) is fed back to the electron beam deflection system to perform position correction equivalently. There is. The correction DAC 8 mainly converts this correction amount into an analog signal. The correction DAC 8 is also used to correct the influence of the external magnetic field, the distortion of the deflection system, and the like.

第3図に,主偏向DAC1の出力(a)主偏向器駆動アン
プ2の出力(b)誤差検出器4の出力(c)のセトリン
グの様子を示す。主偏向器駆動アンプ2のセトリング時
間TAが一番長く数μsec〜数百μsecかかる事はすでに記
述した通りである。従来の描画システムでは,サブフイ
ールドから次のサブフイールドへ電子ビームを移動する
時は,常にTAだけ待ち時間を作って,この時間描画を休
止していた。本発明では,高速の作動アンプを使用して
誤差検出器4を組み主偏向器駆動アンプ2の入出力間の
誤差(同図Cに示す。)を副偏向器駆動アンプ6の入力
に帰還し,主偏向系駆動回路10のセトリング時間内の誤
差を副偏向系で補正する。副偏向器駆動アンプ6はパタ
ーンを高速描画する為,高速のアンプが使われており,
数10〜数100μsecオーダーでゆつくり変化する誤差検出
器4の出力Cには充分追従し,主偏向器駆動アンプ2の
セトリング前の誤差を完全に補正でき,しかも主偏向器
駆動アンプ2の誤差を補正しながら副偏向DAC5から入力
されるパターン情報もアンプの入力点で加算しているの
で,同時にパターンを描画する事が出来る。第3図
(d)に副偏向DAC5の出力信号,同図(e)に該副偏向
DAC5の出力信号dとセトリング誤差信号cとを重畳した
副偏向器駆動アンプ6の出力の様子をそれぞれ示す。図
からわかるように,副偏向器駆動アンプ6は,セトリン
グ誤差を重畳するため,実際に描画するエリアの倍,す
なわち2サブフイールド分偏向できるダイナミツクレン
ジが必要になる為コストが上昇するというデメリツトが
あるが,描画の休止(待ち時間)時間を短縮できるメリ
ツトの方がはるかに大きく,サブフイールド移動時の休
止時間を従来の1/10〜1/100程度に短縮し,トータルの
スループツトを大幅に改善する事ができる。
FIG. 3 shows how the output of the main deflection DAC 1 (a), the output of the main deflector drive amplifier 2 (b) and the output of the error detector 4 (c) are settled. As described above, the settling time T A of the main deflector drive amplifier 2 is the longest and takes several μsec to several hundred μsec. In the conventional writing system, when moving the electron beam from one subfield to the next, a waiting time of T A was always made and writing was paused at this time. In the present invention, the error detector 4 is assembled using a high-speed operation amplifier, and the error between the input and output of the main deflector drive amplifier 2 (shown in FIG. 6C) is fed back to the input of the sub deflector drive amplifier 6. The error within the settling time of the main deflection system drive circuit 10 is corrected by the sub deflection system. The sub-deflector drive amplifier 6 uses a high-speed amplifier because it draws a pattern at high speed.
It sufficiently follows the output C of the error detector 4 which varies in the order of several tens to several hundreds of microseconds, and can completely correct the error before settling of the main deflector drive amplifier 2 and also the error of the main deflector drive amplifier 2. Since the pattern information input from the sub-deflection DAC5 is also added at the input point of the amplifier while correcting the, it is possible to draw the pattern at the same time. The output signal of the sub-deflection DAC5 is shown in FIG. 3 (d), and the sub-deflection is shown in FIG. 3 (e).
The output states of the sub-deflector drive amplifier 6 in which the output signal d of the DAC 5 and the settling error signal c are superimposed are shown. As can be seen from the figure, since the sub-deflector drive amplifier 6 superimposes the settling error, the cost increases because it requires a dynamic range that is twice as large as the actual drawing area, that is, capable of deflecting two subfields. However, the merits that can reduce the pause (waiting time) of drawing are much larger, and the pause time when moving the subfield is shortened to about 1/10 to 1/100 of the conventional one, and the total throughput is greatly increased. Can be improved.

尚,本発明において主偏向系に用いるDACは精度と安
定度さえよければ,各サブフイールドに対応した出力だ
けで良いので高速で低分解能のものを使う事ができ,こ
のようなDACを製作する事は可能である。しかし市販の
高速低分解能(10〜12bit程度)DACを使用する場合その
精度は,ほとんどのものが±1/2LSB位であり,主偏向系
で必要な位置精度を満足しない。そこで市販DACを使用
する時は,各サブフイールド中心位置に対応する目標出
力と主偏向DAC2の出力間の誤差量をあらかじめ測定し
て,メモリーに保存しておき,各サブフイールドに電子
ビームを振る際,そのサブフイールドに対する誤差量を
メモリーから読み出し,補正用DAC8に減算して入力し,
補正する事により,高精度DACとして使用する事が出来
る。このような使い方をすると1,5,8,のDACは,すべて
同じものを使用する事ができ設計,メンテナンスの上で
も大変有利になる。
It should be noted that in the present invention, the DAC used for the main deflection system need only have an output corresponding to each sub-field as long as the accuracy and stability are good, so that a high speed and low resolution one can be used, and such a DAC is manufactured. Things are possible. However, when using a commercially available high-speed low-resolution (about 10 to 12 bits) DAC, the accuracy is almost ± 1/2 LSB, which does not satisfy the position accuracy required for the main deflection system. Therefore, when using a commercially available DAC, the amount of error between the target output corresponding to each subfield center position and the output of the main deflection DAC2 is measured in advance and stored in memory, and the electron beam is swung to each subfield. At this time, the error amount for the subfield is read from the memory, subtracted into the correction DAC8, and input.
By correcting, it can be used as a high precision DAC. With this usage, the same DAC can be used for all 1,5,8 DACs, which is very advantageous in terms of design and maintenance.

(発明の効果) 以上の様に本発明によれば、主偏向駆動系の主駆動ア
ンプのセトリングタイム内に主駆動アンプの入力と出力
との誤差量を求め、これに基づき副偏向駆動系を同時に
動作させるようにしたので、主駆動アンプのセトリング
タイムを実質的に短くすることができ、全フィールドの
描画時間を飛躍的に短縮することができる。
As described above, according to the present invention, the error amount between the input and output of the main drive amplifier is determined within the settling time of the main drive amplifier of the main deflection drive system, and the sub-deflection drive system is determined based on the error amount. Since they are operated at the same time, the settling time of the main drive amplifier can be substantially shortened, and the drawing time of all fields can be drastically shortened.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示す概略図, 第2図は本発明の一実施例を示す回路系のブロツク図, 第3図は第2図の回路系に於ける各所の信号波形図であ
る。 (主要部分の符号の説明) 1……主偏向DAC 5……副偏向DAC 8……補正用DAC 2……主偏向器駆動アンプ 4……誤差検出器 6……副偏向器駆動アンプ 3……主偏向器 7……副偏向器 10……主偏向系駆動回路 20……副偏向系駆動回路 30……偏向電子光学系
FIG. 1 is a schematic diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a circuit system showing an embodiment of the present invention, and FIG. 3 is a signal waveform at various points in the circuit system of FIG. It is a figure. (Description of symbols of main parts) 1 ... Main deflection DAC 5 ... Sub deflection DAC 8 ... Correction DAC 2 ... Main deflector drive amplifier 4 ... Error detector 6 ... Sub deflector drive amplifier 3 ... … Main deflector 7 …… Sub deflector 10 …… Main deflection system drive circuit 20 …… Sub deflection system drive circuit 30 …… Deflection electron optical system

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】メインフィールドを分割してなるサブフィ
ールドそれぞれの所定位置に荷電粒子ビームを偏向する
主偏向系と、セトリング時間の長い主駆動アンプを有し
前記主偏向系を駆動する主偏向駆動系と、前記サブフィ
ールド内にパターンを形成すべく荷電粒子ビームを偏向
する副偏向系と、セトリング時間が前記主駆動アンプよ
りも短い副駆動アンプを有し、前記副偏向系を駆動する
副偏向駆動系と、を具備する荷電粒子ビーム偏向装置に
おいて、 前記主駆動アンプのセトリング中に前記主駆動アンプの
入力値と出力値との誤差量を検出し、該誤差量を前記副
偏向駆動系に出力する誤差量検出手段をさらに設け、 前記主駆動アンプのセトリング中に、前記パターンの位
置情報に前記誤差量検出手段からの出力を重畳して前記
副駆動アンプに入力し前記副偏向系による前記パターン
の形成を可能としたことを特徴とする荷電粒子ビーム偏
向装置。
1. A main deflection system for driving a main deflection system having a main deflection system for deflecting a charged particle beam at a predetermined position in each subfield formed by dividing a main field and a main drive amplifier having a long settling time. A system, a sub-deflection system for deflecting the charged particle beam to form a pattern in the sub-field, and a sub-drive amplifier having a settling time shorter than the main-drive amplifier, the sub-deflection system for driving the sub-deflection system. In a charged particle beam deflector including a drive system, an error amount between an input value and an output value of the main drive amplifier is detected during settling of the main drive amplifier, and the error amount is detected by the sub-deflection drive system. An error amount detecting means for outputting is further provided, and during settling of the main drive amplifier, the output from the error amount detecting means is superposed on the positional information of the pattern and the sub-driving amplifier is output. The charged particle beam deflection apparatus, characterized in that input to the flop allowed the formation of the pattern by the sub-deflection system.
JP60055289A 1985-03-19 1985-03-19 Charged particle beam deflection circuit Expired - Lifetime JP2553032B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60055289A JP2553032B2 (en) 1985-03-19 1985-03-19 Charged particle beam deflection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60055289A JP2553032B2 (en) 1985-03-19 1985-03-19 Charged particle beam deflection circuit

Publications (2)

Publication Number Publication Date
JPS61214342A JPS61214342A (en) 1986-09-24
JP2553032B2 true JP2553032B2 (en) 1996-11-13

Family

ID=12994420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60055289A Expired - Lifetime JP2553032B2 (en) 1985-03-19 1985-03-19 Charged particle beam deflection circuit

Country Status (1)

Country Link
JP (1) JP2553032B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6231118A (en) * 1985-08-01 1987-02-10 Fujitsu Ltd Electron beam exposure
JP2000306808A (en) * 1999-04-21 2000-11-02 Advantest Corp Charged particle beam exposure system
DE10034412A1 (en) * 2000-07-14 2002-01-24 Leo Elektronenmikroskopie Gmbh Process for electron beam lithography and electron optical lithography system
EP2438961B1 (en) 2009-06-03 2015-03-04 Mitsubishi Electric Corporation Particle beam irradiation device
JP5574838B2 (en) * 2010-06-16 2014-08-20 三菱電機株式会社 Particle beam therapy system
JP5438161B2 (en) * 2012-04-13 2014-03-12 株式会社アドバンテスト DA converter

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114425A (en) * 1981-12-28 1983-07-07 Fujitsu Ltd Electron beam exposure device
JPS58154230A (en) * 1982-03-10 1983-09-13 Jeol Ltd Method of electron beam exposure

Also Published As

Publication number Publication date
JPS61214342A (en) 1986-09-24

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