JP2549834B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a high breakdown voltage.

The use of high power semiconductor devices is wide. It is mainly used for DC power transmission, including various motor control and DC / AC exchange. Of course, there are various performances required for high power semiconductor devices, of which the desired breakdown voltage is
It is required that the on-voltage during conduction be as low as possible.
The on-voltage usually tends to increase as the distance between the main electrodes increases. Therefore, it is desired to achieve a desired breakdown voltage with the space between the main electrodes as thin as possible.

There are two causes that lower the breakdown voltage of a semiconductor device from the value obtained by a one-dimensional pn junction. One is electric field concentration at the end of the gate or base electrode, which lowers the breakdown voltage to about 60 to 70% of the one-dimensional breakdown voltage. The other is a surface problem. A variety of problems are related to the decrease in breakdown voltage on the surface, but in a nutshell, charges existing on the surface protective film and the interface generate a carrier accumulation layer on the semiconductor surface, and The width of the depletion layer is narrowed, the electric field strength is increased, and the breakdown voltage is lowered.
One of the causes is that the electric field strength along the surface increases due to the dielectric constant of the SiO ₂ film or the like provided as the surface protective film being smaller than that of silicon.

These inevitably occur in actual semiconductor devices,
Various methods are used as a method for preventing a decrease in breakdown voltage due to the presence of a two-dimensional structure or a three-dimensional structure and a surface.
Typical ones are (1) guard ring and (2) field.
plate, (3) field limiting ring, (4) equipotent
ial ring with resistive film, (5) beveling (posi
(tive beveling, negative beveling), (6) depletio
There are six n etch methods. Without doubt, these methods improve the breakdown voltage of semiconductor devices.

An object of the present invention is to provide a semiconductor device equipped with a new means for improving the breakdown voltage.

 Hereinafter, the present invention will be described in detail with reference to the drawings.

Static induction thyristor (SIThy) is basically p ⁺ n ^- n ⁺
Since the structure is such that the p ⁺ gate region is provided near the n ⁺ main electrode region of the diode, the device has a low on-voltage during conduction, can be quickly shut off by the gate, and has no breakdown during the turn-off process. Very suitable for high power and high speed switching. The present invention will be described by taking SIThy as an example.

The cross-sectional structure of the semiconductor device of the present invention is shown in FIG.
Only the peripheral portion of the semiconductor device is drawn, and the semiconductor device body is configured in the left direction in this figure. 11: Anode metal electrode, 12: p ⁺ Anode region, 13: p ⁺
Immediately adjacent to the anode region, a relatively high impurity concentration thin n region, 14: extremely low impurity concentration high resistance n ^-- region, 15: SIThy p ⁺ gate region, 16, 17: floating p ⁺ Field limiting ring, p ⁺ gate area
Ohmic contact to that metal electrodes 15, 19: p ⁺ field limiting proboscis metal rings 16 are in ohmic contact with the _{electrode, 20: SiO 2, Si 3} N 4, an insulating layer made of polyimide film. The metal electrode 18 reaches above the p ⁺ region 16 and 19 reaches above the p ⁺ region 17. This is for introducing a predetermined capacitance between the metal electrode 18 and the p ⁺ region 16 and between the metal electrode 19 and the p ⁺ region 17.

For simplicity of explanation, when the maximum blocking voltage Vam is applied to the anode electrode, n ^-- region 14 is completely depleted,
At least a part of the region 13 is not depleted and a neutral region remains. Reverse bias -Vg may be applied to the gate. For simplicity, p ⁺ gate 15 and p ⁺ anode
_{Assume that} a positive voltage of V _am is applied between 12.

Therefore, the junction surface between the p ⁺ gate region 15 and the n ⁻ region 14 is reverse biased, and the highest electric field appears in this portion.

The same structure as in FIG. 1 is shown in FIG. Determine the dimensions as shown. between p ⁺ gate 15 and the p ⁺ capacitor C _1, p ⁺ gate 15 and the capacitance C ₂ between the capacitor C _12, 16 and 12 between the p ⁺ field limiting ring 16 between the anode 12, 16 and 17 Capacity of C ₂₃ , 17
Let C ₃ be between and 12. The circuit with one field limiting ring is as shown in FIG. 3, and the circuit with two field limiting rings is as shown in FIG. FLR1 and FLR2 are the first and second meanings of the field limiting ring. G and A are a gate and an anode, respectively. G-A
It is assumed that a voltage of V _am is applied between them. In the case of FIG.
G-FLR1 voltage V ₁₂ applied between the applied between FLR1-A Voltage V
_{If 2} Becomes In FIG. 4, G-FLR1, FLR1-A, and FLR1 respectively.
-FLR2, the voltage applied between _{FLR2-A, V 12, V} 2, V 23, V 3 , respectively Becomes By the way, the capacitance shown in Figs. 3 and 4
C ₁₂ , C ₂ , C ₂₃ and C ₃ are given by the following values under the approximation that the n ⁻ region is completely depleted. Let the length l in the direction perpendicular to the paper surface.

Becomes ε _s and ε _i are the dielectric constants of silicon and the insulating film 20, respectively.

First, the field limiting ring shown in Fig. 3 is 1
The case of individual pieces will be described. 1,000V etc. increase in effective carrier concentration of the silicon surface due to the charge of the electric field concentration and the surface protective film secondary to end of the p ⁺ gate regions 15 which are used for the device before and after the breakdown voltage, the one-dimensional p ⁺ n ^- junction The breakdown voltage may drop to about 50% of the breakdown voltage. If so, in the case of FIG. 3 in which one field limiting ring is provided, V ₁₂ and V ₂ given by the equations (1) and (2) are Is required. That is, a voltage must be applied between the field limiting ring, the p ⁺ gate, and the p ⁺ anode so as to be substantially equal to each other. From the equation (11) and (1) and (2), C ₁₂ ≈C ₂ (12) is required. This condition is easily achieved with the structure of the present invention. Conventional field limiting rings do not achieve this condition at all. This is because in the conventional field limiting ring structure, the second term on the right side does not exist in the capacitance C ₁₂ given by the equation (7). That is, there was no overlap between the fill limiting ring and the metal electrode. In the structure of the present invention, the desired condition is almost always realized by operating the second term on the right side. The value of W ₃ and di is designed. A specific example will be described. 1,000V-2,00
Assuming 0V class withstand voltage, L = 90μm, D = 10μm, W _g1
= 70 μm, W ₁ = 80 μm, and find W ₃ and di.

It is a value per unit length. That is, = 1 cm. From this value, 1.48 pF may be added to the second term on the right side of Expression (7). If the relative permittivity of the insulator is 4, di = 3μ
m, W ₃ = 12.5 μm, or di = 6 μm, W ₃ = 25 μm
And so on. The value of di is determined from the dielectric breakdown strength of the insulator used and the value of the breakdown voltage provided between the adjacent p ⁺ regions.

As the breakdown voltage of semiconductor devices increases, the number of field limiting rings to be inserted increases. For example, in the case of realizing a withstand voltage of 6,000 V with L = 400 μm, for example, four field limiting rings are provided, and the withstand voltage between adjacent field limiting rings is about 1,000 V. The withstand voltage between the outermost field limiting ring and the anode should be about 2,000V. In any case,
When the maximum blocking voltage state or surge voltage is applied, the applied voltage is applied to the inserted field limiting ring.
It can be designed so that a certain value is distributed and added, and extreme electric field concentration does not occur in a part. That is, the dimensions of the field limiting rings and their intervals, the area where the rings and the metal electrodes overlap, and the thickness of the insulating film between them may be designed.

A design example using two field limiting will be described.

The circuit shown in FIG. 4 is obtained. For example, the voltages applied between the field limiting rings are equal.

Determine the voltage distribution as V ₁₂ : V ₂₃ : V ₃ = 1: 1: n (13). That _{{C 2 (C 23 + C} 3) + C 23 C 3}: C 12 C 3: C 12 C 23 = 1: 1: a n (14). From formula (14), it may be determined that C ₂₃ = nC ₃ (15) C ₁₂ = (n + 1) C ₂ + nC ₃ (16). For example, a device with a withstand voltage of 3,000V, 750V between field limiting rings,
It is designed to have a voltage of 1,500 V between the second ring and the anode. n = 2.

From equations (15) and (16), the right capacity may be determined as C ₂₃ = 2C ₃ (15) ′ C ₁₂ = 3C ₂ + 2C ₃ (16) ′. When using a substrate with an impurity density N _D of n ⁻ region of 5 × 10 ¹² cm ⁻³ and L = 300 μm,
The dimensions that satisfy the above conditions are as follows, for example.
Shown using the dimensions shown in FIG.

L = 300 μm, W ₁ = 150 μm, W ₂ = 100 μm, D = 15 μ
m, W _g1 = W _g2 = 120 μm, W ₃ = 120 μm, W ₄ = 35 μm, di
= 5 μm. The average relative induction ratio of the insulator is 5. Almost 3,000V withstand voltage operation has been obtained with the SIThy designed in this way. Most of the 5 μm thick insulating layer was formed of polyimide.

For even higher pressure resistance, use the beveling and depletion on the outermost field limiting ring.
It is also useful to use the etch method together.

As described above, by using the structure of the present invention, a semiconductor device exhibiting a withstand voltage close to the original withstand voltage of silicon can be realized without lowering the withstand voltage due to electric field concentration on the gate or the base and lowering the withstand voltage on the surface. . For example, N _D = 5 ×
Using a substrate of 10 ¹² cm ^-3 and setting L = 200 μm, 4KV
If L = 400 μm, a semiconductor device with a withstand voltage of about 7 KV is realized.

Although the present invention has been described by taking the structure of FIGS. 1 and 2 as an example, it goes without saying that the present invention is not limited to this structure. In short, all of the structures having a structure in which a reverse bias is applied to a high-concentration region of the opposite conductivity type existing in contact with the high-resistance region for increasing the breakdown voltage are effective. A high-concentration region, which is the main electrode region of the device, and a high-concentration region of the same conductivity type, which is a field limiting ring, are provided apart from each other by a predetermined distance to form a floating region. What is necessary is that the metal electrodes are provided so as to overlap each other by a predetermined area. Of course, this metal electrode may be low resistance polysilicon. Here, the structure of the present invention is used only on one side of the main surface of the substrate,
For example, in the structure of FIG. 1, the impurity density of the n ^-- region 14 is very low, and the electric field strength of the portion adjacent to the n region 13 is
This structure can also be introduced to the opposite surface when it becomes strong to some extent. The number of field limiting rings can be increased.

Not only SIThy and BSIT but also static induction transistor, bipolar transistor, junction type FE
T, Vertical structure VDMOS (Vertical Diffusion Self-aligne)
d MOS) p ⁺ in ^{+ It} can be applied as it is to a diode.

Here, these are collectively referred to as a semiconductor device.

INDUSTRIAL APPLICABILITY The semiconductor device of the present invention has a high breakdown voltage and a low on-state voltage, so that it has high operation efficiency, is extremely effective in the field of high-frequency / high-speed power control that will continue to develop in the future, and has a high industrial value.

[Brief description of drawings]

FIG. 1 is a cross-sectional structure of a semiconductor device of the present invention, FIG. 2 is a schematic diagram considering the potential distribution of the device, FIG. 3 is a circuit diagram in the case of one field limiting ring, and FIG.
The figure is a circuit diagram when there are two field limiting rings.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display area H01L 29/861

Claims (1)

(57) [Claims] 1. A high-impurity-density first semiconductor region (12) serving as a first main electrode region, and a first-conductivity-type thin second semiconductor region (13) above the first semiconductor region. And a third conductive type low impurity density third layer above the second semiconductor region.
A semiconductor region (14), a fourth semiconductor region (15) having a second conductivity type and a high impurity density, which is a second main electrode region formed on a part of the surface of the third semiconductor region, At least one or more depths D and widths formed on the outer periphery of the fourth semiconductor region and on a part of the surface of the third semiconductor region.
W ₁ , W ₂ , ... Floating electrode regions (16, 17) of the second conductivity type and high impurity density, and at least an insulating layer (20) having a thickness d _i formed on a part of the upper part of the floating electrode region. ) And a conductive electrode (18, 19) extending from the second main electrode region or the floating region, and a part of the conductive electrode (18, 19) partially forms the floating electrode region (18, 19). 16 and 17) and a predetermined overlapping width (W ₃ , W ₄ ) through the insulating layer (20), and a capacitance having a capacitance value that is less determined by the thickness d _i and the overlapping width. The third semiconductor region and the fourth semiconductor region are reverse-biased during operation to deplete the third semiconductor region almost completely, and the third semiconductor region and the fourth semiconductor region are depleted. the capacitance between the floating region (C _2, C _3), the capacitance between the the floating region and the third semiconductor region (C _12), and the遊領 range capacity between each other (C
₂₃ ) so that the relationship of voltage distribution by satisfying the desired breakdown voltage between the first semiconductor region and the fourth semiconductor region is such that the thickness d _i and the overlapping width (W ₃ , W ₄ ), The depth D, the widths W ₁ , W ₂ , ..., The distance L between the second semiconductor region and the floating electrode region, and the distance between the fourth semiconductor region and the floating electrode region ( _W'g1 ) and the distance between the floating electrode regions ( _W'g2 ) are determined.