JP2548381B2 - High-speed clock regenerator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery device used for data communication and the like.

2. Description of the Related Art FIG. 2 shows the configuration of a conventional clock recovery device. In FIG. 2, reference numeral 1 is a zero-cross signal input terminal, which is connected to the zero-cross detector 6. Reference numeral 7 denotes an up / down counter 7, to which the output of the zero-cross detector is input together with the output of the fixed frequency divider 11. A correction width switching unit 9 switches the frequency division number of the variable frequency divider 10 according to an input from the correction width setting terminal 4. 12 is a reference clock.

Next, the operation of the above conventional example will be described. In FIG. 2, the up-down counter 7 counts the direction of the phase difference between the zero-cross signal input and the input from the fixed frequency divider 11 each time the zero-cross signal is input. Switch the frequency division number. As a result, the phase of the peripheral force signal of the fixed frequency divider 11 is made to coincide with the zero cross signal input.

In this way, even the conventional clock reproducing apparatus described above can reproduce the clock synchronized with the zero-cross signal.

However, in the above-described conventional clock recovery device, since the frequency division value of the variable frequency divider 10 is switched by the detection of the frame synchronization signal or the like, if there is a large phase difference at the time of reception rising, There was a problem that the clock could not be reproduced at high speed.

The present invention solves such a conventional problem, and an object of the present invention is to provide an excellent clock reproducing device capable of high-speed clock reproducing.

Means for Solving the Problems In order to achieve the above object, the present invention is provided with a reception rising detection section and a correction counter.

Therefore, according to the present invention, the reception rising detection unit detects the reception rising, the correction number counter counts the number of phase corrections from the reception rising time, and the phase correction value is sequentially decreased by the count number. By moving it, it is possible to pull in a constant phase difference at high speed.

Embodiment FIG. 1 shows the structure of an embodiment of the present invention.
In FIG. 1, reference numeral 2 is an unlock signal input terminal, and 3 is a press signal input terminal, which is input to the reception rising detection section 5. Reference numeral 8 denotes a correction counter, which is connected between the up / down counter 7 and the correction width switching unit 9 and is also connected to the output of the reception rising detection unit 5.

Next, the operation of the above embodiment will be described. In the above embodiment, depending on the input states from the unlock signal input terminal 2 and the press signal input terminal 3, the reception rising detection unit 5 detects the reception rising after power-on, after transmission, and after frequency switching.
And the correction counter is reset. The zero-cross detector 6 detects the zero-cross of the input signal of the zero-cross signal input terminal 1 to generate a pulse, and the up / down counter 7 compares the output of the fixed frequency divider 11 with the direction of the phase difference, and detects the phase shift. Count the number of times. When the number of times reaches a constant value, a signal is output to switch the frequency division value of the variable frequency divider 10. The correction counter 8 counts the number of times the signal is output. The correction width switching unit 9 switches the frequency division value of the variable frequency divider according to the count number. When the frequency division value of the variable frequency divider 10 is switched so that the correction width for one time becomes smaller as the count number of the correction number counter becomes larger, at the start of reception, even if the phase difference is large, at high speed, The clock synchronized with the zero-cross signal can be reproduced.

EFFECTS OF THE INVENTION As is clear from the embodiments, according to the present invention, the correction width can be increased at the start of reception, and when the phase difference is large, the number of corrections can be reduced and high-speed clock reproduction can be performed. In addition, there is an advantage that stable clock reproduction can be performed in a steady state by decreasing the correction width in order.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a clock recovery device according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a conventional clock recovery device. 1 ... Zero cross signal input terminal, 2 ... Unlock signal input terminal, 3 ... Press signal input terminal, 4 ... Correction width setting terminal, 5 ... Reception rising detection section, 6 ... Zero cross detection section, 7 ... ... up-down counter, 8 ... correction frequency counter, 9 ... correction width switching unit, 10 ... variable frequency divider,
11 …… Fixed divider, 12 …… Reference clock.

Front Page Continuation (72) Inventor Masaki Terashima 4-3-1 Tsunashima-higashi, Kohoku-ku, Yokohama, Kanagawa Matsushita Communication Industrial Co., Ltd. Company Toshiba Hino Plant (72) Inventor Tetsuya Hanawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Hiroshi Takegaki 8-1-1 Tsukaguchihonmachi, Amagasaki City, Hyogo Mitsubishi Electric Corporation (56) References JP-A-61-248635 (JP, A) JP-A-64-64434 (JP, A)

Claims (1)

(57) [Claims] 1. A rising edge detecting section for detecting a rising edge of reception, an up-down counter for counting a phase difference between an input of a zero-cross signal and an internal clock, a correction number counter for counting the number of phase corrections from the rising edge of reception, and a correction. A clock regenerator equipped with a variable frequency divider that switches a frequency division value such that one phase correction width is reduced as the count number of the frequency counter increases.