JP2548013B2 - Microcomputer - Google Patents

Description

The present invention relates to a microcomputer of a semiconductor integrated circuit having an address bus and a data bus externally.

SUMMARY OF THE INVENTION According to the present invention, in a microcomputer, an address decode circuit normally provided outside the chip is built into the chip, and the output of this address decode circuit is output with the same AC characteristics as the output of the address being guaranteed. It enables high-speed access to external peripheral circuits.

[Prior Art] FIG. 2 shows a circuit configuration in the prior art.

In FIG. 2, 16 is a microcomputer, 17 is an address bus, 18 is a decoding circuit, and 19 is a peripheral circuit selection signal.

In the circuit configuration of the prior art, the decoding circuit 18 for selecting a peripheral circuit arranged in the address space of the microcomputer 16 is independently configured outside the microcomputer 16. Since the decode circuit 18 decodes the address bus 17 and outputs it as the peripheral circuit selection signal 19, the peripheral circuit selection signal 19 is decoded from the address to the decode circuit.
It had the amount of delay that 18 had. That is, the peripheral circuit selection signal 19 shown in FIG.
Confirm after a delay of passing 18.

[Problems to be Solved by the Invention] However, in the prior art, the peripheral circuit selection signal obtained by decoding the address as described above is output after a delay of passing through the decoder after the address is output. There was a problem that the AC characteristics that interface with the interface were reduced by the amount of the delay.

The present invention solves such a problem, and its object is to enable high-speed access to an external peripheral circuit by making the peripheral circuit selection signal output by the decoder have the same AC characteristics as the output of the address bus. Is what you are trying to do.

[Means for Solving Problems] The microcomputer of the semiconductor integrated circuit of the present invention is
A first memory circuit that holds the internal address information in synchronization with the first block signal and an output of the first memory circuit to a second memory circuit
A second memory circuit that holds the block signal in synchronization with
A decoding circuit for decoding and outputting the output of the first memory circuit, and a third memory circuit for holding the output of the decoding circuit in synchronization with the second clock signal are provided.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, 1 is the internal address bus, 2 is the first clock signal, 4 is the first memory circuit, 8 is the output of the first memory circuit 4, 3 is the second clock signal, and 6 is the second. , 9 is the output of the second memory circuit 6, 5 is the decode circuit, 11 is the output of the decode circuit 5, and 7 is the peripheral circuit selection signal memory circuit which is the third memory circuit. Reference numeral 10 is an output of the peripheral circuit selection signal storage circuit 7. FIG. 3 is a timing chart for the corresponding numbers in FIG. Third
Referring to the figure, 12 is a delay value of the first memory circuit 4, 13 is a delay value of the decoding circuit 5, 14 is a delay value of the second memory circuit 6 and the third memory circuit 7, Reference numeral 15 is a data setup time for the third memory circuit 7 of the decoding circuit 5.

When the first clock signal 2 rises, the first memory circuit 4
Takes in the value of the internal address bus 1 and determines the output 8 after passing through the delay value 12 of its own. The decoding circuit 5 decodes the output 8 of the first storage circuit 4 and determines the output 11 after passing through the delay value 13 of its own.

When the second clock signal 3 rises, the second memory circuit 6
Takes in the output 8 of the first memory circuit 4, determines the output 9 after passing through its own delay value 14, and determines the third memory circuit 7
Takes in the output 11 of the decoding circuit 5, determines the output 10 after passing through the delay value 14 of its own.

Therefore, if 15 in FIG. 3 is at least the setup time of the third memory circuit 7, the delay values of the outputs 9 and 10 are only 14 in FIG. 3, and the output 9 (address) and the output 10
(Peripheral circuit selection signal) is output at the same time.

[Effects of the Invention] According to the above configuration of the present invention, the peripheral circuit selection signal can be output with the same AC characteristics as the output of the address guaranteed, so that high-speed access to the external peripheral circuit becomes possible.

Further, by incorporating the decoding circuit, the number of circuits configured outside is also reduced.

[Brief description of drawings]

 FIG. 1 is a block diagram of the present invention. FIG. 2 is a block diagram of a conventional technique. FIG. 3 is a timing chart of FIG. In the figure, 1 ... Internal address bus 2 ... First clock 3 ... Second clock 8 ... First memory circuit (master latch) output 9 ... Second memory circuit (slave latch) output 10 ... ... Third memory circuit (slave latch) output 11 ... Decode output.

Claims (1)

(57) [Claims] 1. In a microcomputer of a semiconductor integrated circuit having an external address bus and data bus, a first memory circuit for holding internal address information in synchronization with a first clock signal, and the first memory circuit. Second storage circuit for holding the output of the first storage circuit in synchronization with the second clock signal, a decode circuit for decoding and outputting the output of the first storage circuit, and an output of the decode circuit for the second clock. And a third memory circuit which holds the memory in synchronization with the microcomputer.