JP2546214B2 - LCD drive system - Google Patents

Description

TECHNICAL FIELD The present invention relates to a liquid crystal drive system for driving a dot matrix liquid crystal display panel.

[Prior Art] Conventionally, a dot matrix liquid crystal display panel is generally used for a portable small-sized television receiver, a display unit of a small-sized electronic computer, and the like. FIG. 8 shows the driving circuit, 11 is a dot matrix liquid crystal display panel,
12 is a common side driver that drives the common electrodes X1 to XN of the liquid crystal display panel 11, 13 is a segment side driver that also drives the segment electrodes Y1 to YM, and 14 is a common side driver 12
And a display control circuit 14 for controlling the segment side driver 13
Is. Then, the display control circuit 14 operates the liquid crystal display panel 11
As a display driving method, a time division driving method shown in FIG. 9 can be considered. This figure is a timing chart showing a simple time division drive. Common electrodes X1 to X4 are sequentially selected, and in synchronization with this, Y1,1 is applied to segment electrode Y1.
.About.Y1,4 shows a state in which a signal indicating a gradation is given. Therefore, the pixels at the intersections of the common electrodes X1 to X4 and the segment electrode Y1 are displayed at the gradation levels Y1,1 to Y4,4.

The above-mentioned driving method causes no problem in a relatively small liquid crystal display panel having a small number of common electrodes, but in a liquid crystal display panel having a large number of common electrodes, the duty ratio decreases and the contrast decreases. Currently used duty ratio is up to about 1/100. By the way, in the case of a liquid crystal display panel used in a small television receiver,
As the number of common electrodes, generally around 240 which is the number of effective scanning lines corresponding to one field is used. If this is simply driven in time division as described above, the duty ratio will be 1 /
240, the contrast is significantly reduced.

Several methods have been proposed as measures against the above problem, but as a typical one, there is a method of simultaneously selecting a plurality of common electrodes adjacent to a common electrode that should be originally selected. FIG. 10 shows the driving method. In the common electrodes X1 to X4, four adjacent electrodes are sequentially selected at the same time, and in synchronization with this, Y1 is applied to the segment electrode Y1.
It shows a state where gradation signals of −2 to Y1,4 are given. For example, while the common electrode X4 is selected, if the grayscale signals "Y1,1", "Y1,2", "Y1,3", "Y1,4" are applied to the segment electrode Y1, the common electrode X4 and the segment electrode
In the pixel at the intersection of Y1, the gradation value is (Y1,1 + Y1,2 + Y1,3 + Y1,4) / 4, and the average value of the display gradation values of the four pixels before and after is 4 times the time width of FIG. 9 above. Will be displayed. Therefore, compared with the method of FIG. 9, for example, in a liquid crystal display panel for a small television device having 240 scanning lines, its duty ratio is 4 times as high as 1/60 (4/240), and the contrast is sufficient. It will be of a practical level.

[Problems to be Solved by the Invention] However, in the driving method shown in FIG. 10, the contrast is improved, but as described above, one pixel is equal to the average value of the gradation values of three adjacent pixels. The gradation will be displayed. This is because the amount of transmitted light of the liquid crystal cell depends on the effective voltage, so that the display content of the pixel includes a gradation degree other than the gradation that should be originally displayed, and the resolution is lowered. There's a problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal drive system for driving a liquid crystal display panel capable of high-resolution display without lowering contrast.

[Means and Actions for Solving the Problem] According to the present invention, a gradation signal from which an influence component obtained by attenuating a gradation signal applied to an adjacent pixel is removed is applied to a segment electrode and is applied as an adjacent pixel. The voltage at that time is applied to the common electrode as a value corresponding to the above attenuation rate.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of the whole thereof, and an image input signal of an analog is sent to a synchronous control circuit 16 of an A / D converter 15. The A / D converter 15 quantizes the input video signal in N × M pixel units and sends it to the signal processing unit 17. The signal processing unit 17 is provided with a line memory and an arithmetic circuit inside, and the digital signal sent from the A / D converter 15 is processed in synchronization with the synchronization signal from the synchronization control circuit 16 to the liquid crystal drive unit 18. Output. The liquid crystal drive section 18 drives and displays the liquid crystal display panel 19 in synchronization with the sync signal from the sync control circuit 16 based on the processed digital signal.

FIG. 2 illustrates the principle of processing the gradation signal supplied to each segment electrode.

A differentiator is located on the left side in the figure, and corresponds to the signal processing unit 17 in FIG. In this differentiator, for example, a gradation signal a to a 4-bit segment electrode
Is subtracted by the output of the adder 21 in the attenuator 20 and then sent to the line memory (denoted as "M" in the figure) 22 while being sent to the left integrator as the output signal b of the differentiator. The line memory 22 temporarily holds the output of the subtractor 20, and then outputs it to the line memory 23 and the multiplier 24. Similarly to the line memory 22, the line memory 23 also temporarily holds the transmitted signal and outputs it to the multiplier 25. The multipliers 24 and 25 multiply the signals sent with the fixed coefficients a ₁ and a ₂ , respectively, and output them to the adder 21. Here, fixed coefficients a ₁ , a ₂
Has a relationship of 0 <a ₂ ≦ a ₁ ≦ 1. Above fixed coefficient added by adder 21
The outputs of the line memories 22 and 23 multiplied by a ₁ and a ₂ are sent to the subtractor 20 as a minus input.

On the other hand, the integrator on the right side of the figure is the liquid crystal drive unit 18 of FIG.
Also, the function of the optical response is simulated in order to explain the role of the differentiator on the left side, which corresponds to the display pixel of the liquid crystal display panel 19. Generally, the electro-optic effect of the display point corresponding to each matrix electrode depends on the effective voltage as described above, and is approximately calculated by the voltage value applied to the electrode and the cumulative value of the time when the voltage is applied. Proportional. That is, the optical effect is proportional to the value obtained by integrating the voltage value with respect to time. Therefore, this can be considered as an integrator with a voltage value input and an optical effect output. In the figure, the output signal b of the differentiator is sent to the line memory 26 and the adder 27 of the integrator. The line memory 26 temporarily holds the sent signal and then outputs it to the line memory 28 and the multiplier 29. Similarly to the line memory 26, the line memory 28 temporarily holds the transmitted signal and then outputs it to the multiplier 30. The multipliers 29, 30 multiply the signals sent with the fixed coefficients a ₁ , a ₂ set in the multipliers 24, 25, respectively, and adder 31
Output to. The fixed coefficients a ₁ and a ₂ added by the adder 31
The outputs of the line memories 26 and 27 multiplied by
Sent to The addition output of the adder 27 is used as the output signal c of the integrator, which is used as a signal indicating the actual optical effect, that is, the gradation at the time of display. The value of the batch is added.

In the figure, since signals of the same value are always input to the left and right line memories 22 and 26 and 23 and 28, the output of the adder 21 and the output of the adder 31 also always have the same value. Therefore, logically, no signal loss occurs between the gradation signal a which is an input signal and the output c.

The multiplier 24,25 and the multiplier 29,30 have fixed coefficients.
The delayed signal is multiplied by using a ₁ and a ₂ in order to prevent the value of the output signal b of the differentiator from changing significantly and stabilize it.

Although the line memory has two stages in FIG. 2, a circuit using a general multi-stage line memory will be described with reference to FIG.

In the differentiator on the left side of the figure, the gradation signal a to the segment electrode is subtracted by the subtractor 32 by the output of the adder 33, and then sent to the limiter 34. Limiter 34 performs a clipping when the value of the output signal d of the subtractor 32 exceeds a specific number of bits, and sends a signal e with a limited number of bits in the line memory 35 ₁ and the multiplier 36. Line memory 35 ₁
Output is sequentially sent to the line memories 35 ₂ , 35 ₃ , ..., 35 _L, and the output of each line memory 35 _{1 to} 35 _L is also
It is also output to the multipliers 37 _{1 to} 37 _L. The multipliers 37 _{1 to} 37 _L multiply the signals sent with the fixed coefficients a _{1 to} a _L , respectively, and output the multiplied signals to the adder 33. Here, the fixed coefficient a ₁ ~
a ₂ has a relationship of 0 <a _L ≤ ... ≤a ₂ ≤a ₁ ≤1. Above fixed coefficient added by adder 33
The outputs of the line memories 35 _{1 to} 35 _L multiplied by a _{1 to} a _L are sent to the subtractor 32 as a minus input.

The multiplier 36, the output of the subtractor 32, which is limiting the number of bits in the limiter 34 is multiplied with a fixed coefficient b _X. Here, the fixed coefficient b _X has a relation of “b _X > 1” and acts as an amplifier. This is the output signal d of the subtractor 32.
The average value of is compared to the average value of the input signal a In response to this, it is designed to be amplified.

On the other hand, in the integrator on the right side of the figure, the signal b is sent to the line memory 38 ₁ and the adder 39. Line memory 38 ₁ of the output lines sequentially memory 38 _2, 38 _3, ..., 38 in what is sent _L, and also the output of the respective line memories 38 ₁ to 38 DEG _L, multipliers 40 ₁ to 40 _L to be output To be done. The multipliers 40 ₁ to 40 _L multiply the signals sent with fixed coefficients a _{1 to} a _L , respectively,
Output to the adder 41. The outputs of the line memories 38 _{1 to} 38 _L multiplied by the fixed coefficients a _{1 to} a _L added by the adder 41 are sent to the adder 39. The addition output of the adder 39 is used as the output signal c of the integrator. In this integrator, the signal amplified by "b _X " times by the multiplier 36 is processed, so that the output signal c is also amplified by "b _X " times.

The limiter 34 is for keeping the output signal b of the differentiator within a constant bit range. Each input signal of the adders 41 and 39 corresponds to a voltage value applied to one display pixel of the liquid crystal display panel 19 at a time in the liquid crystal drive section 18, so that the allowable input range is limited. Therefore, the output range of the limiter 34 is set to 1 / b _X of the allowable input range of the adder 39. Whether or not the limiter 34 actually clips the input signal d depends on the sequence of the input signal a of the differentiator and the value of the fixed coefficient a _n of the multiplier 37 _n . That is, the larger the amplitude of the high frequency in the vertical direction of the input signal a, the more The larger the value of, the higher the clipping rate.
Since clipping causes a loss of signal and results in deterioration of the room, it is necessary to determine the fixed coefficient a _n of the multiplier 37 _n in consideration of the property of the input signal a.

Next, the actual configuration of the signal processing unit 17 in FIG. 1 will be described.

FIG. 4 shows the circuit configuration thereof. The gradation signal a to each segment electrode is subtracted by the output of the adder 43 by the subtractor 42 and then sent to the limiter 44. The limiter 44 performs clipping when the output of the subtractor 32 exceeds a specific number of bits, and sends a signal with a limited number of bits to the line memory 45 and the multiplier 46. The output of the line memory 45 is sent to the line memory 47, and the outputs of the respective line memories 45 and 47 are also output to the multipliers 48 and 49.
The multipliers 48 and 49 multiply the signals sent with the fixed coefficients a ₁ and a ₂ , respectively, and output them to the adder 33. here,
The fixed coefficients a ₁ and a ₂ have a function of 0 <a ₂ ≦ a ₁ ≦ 1. Above fixed coefficient added by adder 43
The outputs of the line memories 45 and 47 multiplied by a ₁ and a ₂ are sent to the subtractor 42 as a minus input.

The multiplier 46 multiplies the output of the subtractor 42, the number of bits of which is limited by the limiter 44, by a fixed coefficient b _X. Here, the fixed coefficient b _X has a function of “b _X > 1” and acts as an amplifier, and its output becomes an output signal b to the liquid crystal drive unit 18 of the next stage.

Corresponding to the configuration of the signal processing section 17, the liquid crystal driving section 18 applies a voltage having a waveform as shown in FIG. 5 to the common electrode. The same figure shows the applied voltage waveform on the right side of FIG. 2 that realizes an integrator. The applied voltage to each common electrode when not selected is V ₀ , and the applied voltage when selected is V ₁ . In this case, using the fixed coefficient a ₁ of the multiplier 48 in FIG. 4, the half-selected voltage obtained by the expression a ₁ (V ₁ −V ₀ ) + V ₀ is V ₂ , and similarly the fixed coefficient a of the multiplier 49 is _The half-selected voltage obtained by the equation a ₂ (V ₁ −V ₀ ) + V ₀ using ₂ is V ₃ .
In order to apply a voltage to such a common electrode,
The voltage selection signal for one common electrode may be set to 2 bits so that any one of the four voltage values V ₀ , V ₃ , V ₂ and V ₁ can be selected.

Also, although FIGS. 2 to 4 show an example in which a plurality of line memories are used in the signal processing unit 17 serving as a differentiator, an increase in the line memories directly leads to an increase in cost due to the circuit configuration. There is. Therefore, another embodiment of the present invention in which a differentiator having the same effect as in FIGS. 2 to 4 is constructed by using only one line memory will be described with reference to FIG.

In the figure, the gradation signal a to the segment electrode is subtracted by the subtractor 50 by the output of the line memory 52 and then sent to the multiplier 52, while it is sent to the integrator on the right side as the output signal b of the differentiator. To be The multiplier 52 multiplies the signal sent with the fixed coefficient a ₁ and outputs it to the adder 53. The adder 53 sends the addition output to the line memory 51. The output of the line memory 51 is sent to the subtractor 50 and also to the multiplier 54. The multiplier 54 multiplies the signal sent with the fixed coefficient a ₂ ′ and outputs it to the adder 53.

Here, the fixed coefficients a ₁ , a ₂ ′ have a function of 0 <a ₁ ≦ 1, 0 <a ₂ ′ ≦ 1. The output of the adder 53 is delayed by the line memory 51 and then sent to the subtractor 50, and then input again to the adder 53 via the multiplier 54, which forms an infinite loop. As a line memory
Although only one 51 is provided, the same effect as that shown in FIGS. 2 to 4 can be obtained.

In principle, the integrator corresponding to this has a configuration as shown on the right side of the figure. The signal b line memory 55 ₁ and the adder 5
Sent to 6. The output of the line memory 55 ₁ is sequentially sent to the line memories 55 ₂ , 55 ₃ , ..., and the outputs of the respective line memories 55 ₁ , 55 ₂ , ... are also output to the multipliers 57 ₁ , 57 ₂ , .... Is output. The multipliers 57 ₁ , 57 ₂ , ... have fixed coefficients a ₁ , a ₂ , ..., respectively.
The signal sent by is multiplied and output to the adder 58. The outputs of the line memories 55 ₁ , 55 ₂ , ... Multiplied by the fixed coefficients a ₁ , a ₂ , ... Added by the adder 58 are sent to the adder 56. Then, the addition output of the adder 56 is used as the output signal c of the integrator.

In order to prevent a signal loss in the above configuration, the value subtracted by the subtractor 50 from the input signal a and the value added by the adder 58 by the adder 56 may be equal. As a condition therefor, it is necessary that the integrator side has an infinite number of line memories and multipliers, and that the multipliers a _n less than a ₂ have a relationship of a _n = a _n-1 · a ₂ ′. However, in reality, even if the processing is terminated when the value of a _n becomes small to some extent (about 0.1), the signal loss is extremely small, and the image deterioration due to the error is hardly seen.

Further, the voltage waveform applied to the common electrode shown in FIG. 5 is controlled by four voltage values. As described above, attention is paid to the property of the liquid crystal display element in which the electro-optical effect depends on the effective voltage. , May be controlled by two voltage values as shown in FIG. That is, this figure shows a state in which the effective voltage value applied to each common electrode changes in four steps between V _{0 and} V ₁ by controlling the pulse width (the number of unit pulses per time). In the above, the integrator is realized by the configuration of three stages of line memory using the values of a ₁ = 1, a ₂ = 0.5, a ₃ = 0.25 as the multipliers of the multipliers of the integrator.

[Effects of the Invention] As described in detail above, according to the present invention, the gradation signal from which the influence component obtained by attenuating the gradation signal applied to the adjacent pixel is removed is applied to the adjacent pixel while being applied to the segment electrode. Since the voltage at the time of application is applied to the common electrode as a value corresponding to the above-mentioned attenuation factor, it is possible to provide a liquid crystal drive method for driving a liquid crystal display panel capable of high-resolution display without lowering contrast. You can

[Brief description of drawings]

1 to 7 show an embodiment of the present invention.
FIG. 1 is a block diagram showing the overall circuit configuration, FIG. 2 is a block diagram showing an example of the principle configuration, FIG. 3 is a block diagram showing the general principle configuration, and FIG. 4 is the signal processing of FIG. 5 is a block diagram showing a specific circuit configuration of a part, FIG. 5 is a timing chart showing a voltage waveform applied to a common electrode, FIG. 6 is a block diagram showing another example of the principle configuration, and FIG. 7 is the above-mentioned FIG. 8 is a timing chart showing the waveform of the voltage applied to the common electrode by a control method different from that of Fig. 8, Fig. 8 is a block diagram showing the general circuit configuration of the liquid crystal drive system, and Figs. 9 and 10 are the voltages applied to the common electrode of the related art. It is a timing chart which shows a waveform. 11,19 …… Liquid crystal display panel, 12 …… Common side driver, 1
3 …… Segment side driver, 14 …… Display control circuit, 15
...... A / D converter, 16 …… Synchronous control circuit, 17 …… Signal processing unit, 18 …… Liquid crystal drive unit, 20,32,42,50 …… Subtractor, 21,2
7,31,33,39,41,43,53,56,58 ... Adder, 22,23,26,28,3
_{5 1 ~35 L, 38 1 ~38} L, 45,47,51,57 1 ~57 3 ...... line _{memory, 24,25,29,30,36,37 1 ~37 L, 40 1} ~40 L, 46,48,49,52,5
4,57 _{1-57 3} ...... multiplier, 34 and 44 ...... limiter.

Claims (1)

(57) [Claims] 1. In a liquid crystal drive system in which a plurality of k scanning electrodes adjacent to each other are selected and scanned at the same time, as a gradation signal to be given at a timing of n for each signal electrode, , N, signal processing means for giving a gradation signal by subtracting an influence component obtained by attenuating each of the k-1 gradation signals provided to the signal electrode at a predetermined attenuation rate, and each scanning electrode. Scan electrode driving means for setting the applied voltage of the scan electrode for applying the voltage at the timing before n to a value corresponding to the above-mentioned attenuation rate in comparison with the voltage applied at the timing for n. LCD driving method.