JP2544803B2 - Ceiling current supply circuit - Google Patents
Ceiling current supply circuitInfo
- Publication number
- JP2544803B2 JP2544803B2 JP1088782A JP8878289A JP2544803B2 JP 2544803 B2 JP2544803 B2 JP 2544803B2 JP 1088782 A JP1088782 A JP 1088782A JP 8878289 A JP8878289 A JP 8878289A JP 2544803 B2 JP2544803 B2 JP 2544803B2
- Authority
- JP
- Japan
- Prior art keywords
- supply circuit
- current supply
- resistors
- circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Devices For Supply Of Signal Current (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ISDNのデシタル加入者回路などに用いられ
加入者線路へのシーリング電流を供給するシーリング電
流供給回路に関する。Description: TECHNICAL FIELD The present invention relates to a sealing current supply circuit which is used in an ISDN digital subscriber circuit or the like and supplies a sealing current to a subscriber line.
従来、この種のシーリング電流供給回路は、単に異常
電圧印加時の電力に耐えるように耐電力値を持たせた設
計を行っていた。Conventionally, this type of ceiling current supply circuit has been designed to have a withstand power value so as to simply withstand the power when an abnormal voltage is applied.
第３図は従来のシーリング電流供給回路の回路図で、
電圧源にそれぞれ直列接続された抵抗R1,R3およびR2,R4
と、これら抵抗の間に交差して接続されたコンデンサC1
とから構成されている。FIG. 3 is a circuit diagram of a conventional ceiling current supply circuit,
Resistors R 1 , R 3 and R 2 , R 4 connected in series with the voltage source, respectively
And a capacitor C 1 connected across these resistors across
It consists of and.
上述した従来のシーリング電流供給回路は、この回路
に用いる抵抗R1〜R4に通常時の電力値に較べ過大な耐電
力値を持たせているため、回路の物理的な大きさが大き
くなり、実装スペースの点で不利になるという欠点があ
る。In the above-mentioned conventional ceiling current supply circuit, the resistors R 1 to R 4 used in this circuit have an excessive withstand power value compared with the power value at the normal time, so the physical size of the circuit becomes large. However, there is a drawback that it is disadvantageous in terms of mounting space.
本発明の目的は、このような欠点を除き、効率的に電
流制御をできるようにし、実装スペースを少くしたシー
リング電流供給回路を提供することにある。An object of the present invention is to eliminate the above drawbacks and to provide a ceiling current supply circuit that enables efficient current control and reduces the mounting space.
本発明の構成は、加入者線路の両端にそれぞれ抵抗を
介して電圧源から電流を供給するシーリング電流供給回
路において、前記抵抗が厚膜抵抗からなりセラミック基
板の一面上に配設されると共に、前記各抵抗に直列に正
の温度係数をもつPTC抵抗がそれぞれ接続されかつ前記
セラミック基板の他面上に配設されることにより、前記
加入者線路に過電圧が印加された時前記PTC抵抗の抵抗
値が大きくなり、これら抵抗に流れる電流が制限されて
熱破壊を防止するようにしたことを特徴とする。The configuration of the present invention is a ceiling current supply circuit that supplies a current from a voltage source to both ends of a subscriber line through a resistor, respectively, and the resistor is a thick film resistor and is disposed on one surface of a ceramic substrate. The resistance of the PTC resistor when an overvoltage is applied to the subscriber line by connecting a PTC resistor having a positive temperature coefficient to each of the resistors in series and disposing the PTC resistor on the other surface of the ceramic substrate. The value is increased, and the current flowing through these resistors is limited to prevent thermal destruction.
第１図（ａ），（ｂ）は、本発明の一実施例の横断面
図およびその回路図、第２図は本実施例を使用時の内部
接続及び概略周辺回路の回路図である。1 (a) and 1 (b) are a cross-sectional view and a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of internal connections and a schematic peripheral circuit when the present embodiment is used.
本実施例のシーリング電流供給回路１は、第１図
（ｂ）の回路のように、従来の厚膜抵抗R2,R4に直列に
ポジスタのような正の温度係数をもつPTC抵抗体RP1,RP2
を接続したものであり、第１図（ａ）のように、セラミ
ック基板10の一面に抵抗R1〜R4として厚膜抵抗体12を設
け、その基板10の他面にPTC抵抗体13を設けたものであ
る。この場合、基板10からは端子11が導き出されてい
る。The ceiling current supply circuit 1 of the present embodiment has a PTC resistor R having a positive temperature coefficient such as a posistor in series with the conventional thick film resistors R 2 and R 4 , as in the circuit of FIG. 1 (b). P1 , R P2
As shown in FIG. 1A, a thick film resistor 12 is provided as a resistor R 1 to R 4 on one surface of the ceramic substrate 10, and a PTC resistor 13 is provided on the other surface of the substrate 10. It is provided. In this case, the terminal 11 is led out from the substrate 10.
第２図に示すように、電圧源VBBから回路に電圧が通
常印加されており、抵抗R1〜４は、この電源VBBから電
圧に対する電力値のみに耐えられる設計がなされてい
る。ここで、異常電圧源３が加入者線路５に印加された
場合、このシーリング電源供給回路１が発熱することに
より、PTC抵抗RP1,RP2の抵抗値が増大し回路１に流れる
電流が制限される。このシーリング電流供給回路１の発
熱量はある一定値以下に抑えることができる。したがっ
て、この回路１の熱破壊を防止することが可能となる。As shown in FIG. 2, a voltage is normally applied to the circuit from the voltage source V BB , and the resistors R 1 to 4 are designed to withstand only the power value corresponding to the voltage from the power source V BB . Here, when the abnormal voltage source 3 is applied to the subscriber line 5, the ceiling power supply circuit 1 generates heat to increase the resistance values of the PTC resistors R P1 and R P2 and limit the current flowing in the circuit 1. To be done. The heat generation amount of the ceiling current supply circuit 1 can be suppressed to a certain value or less. Therefore, it becomes possible to prevent thermal destruction of the circuit 1.
本実施例において、抵抗R1〜R4は、300Ω〜1KΩであ
り、常温時のPTC抵抗は約10Ωとなっている。このPTC抵
抗RP1,RP2は温度が上昇するとその抵抗値が数ＫΩと高
くなり、PTC抵抗に電圧降下を生ずるため、セラミック
基板が過度に温度上昇することはなくなる。In this embodiment, the resistances R 1 to R 4 are 300Ω to 1KΩ, and the PTC resistance at room temperature is about 10Ω. When the temperature of the PTC resistors R P1 and R P2 rises, the resistance value increases to several KΩ, and a voltage drop occurs in the PTC resistor, so that the temperature of the ceramic substrate does not rise excessively.
以上説明したように、本発明は、PTC抵抗を直接基板
に実装することにより、物理的な大きさが通常の耐電力
値とほぼ同等の大きさで異常電圧印加時でも、シーリン
グ電流供給回路の熱破壊を防止できるという効果があ
る。As described above, according to the present invention, by directly mounting the PTC resistor on the substrate, the physical size is almost the same as the normal withstand power value, and even when an abnormal voltage is applied, the sealing current supply circuit This has the effect of preventing thermal destruction.
第１図（ａ），（ｂ）は本発明の一実施例の横断面図お
よびその回路図、第２図は本実施例を使用時の内部接続
及び周辺回路の回路図、第３図は従来のシーリング電流
供給回路の一例の回路図である。 １……発熱防止形シーリング電流供給回路、２……デジ
タル加入者回路、３……異常時電圧源、４……加入者線
路及び終端インピーダンス、５……加入者線路、10……
基板、11……端子、12……厚膜抵抗（R1〜R4）、13……
PTC抵抗（RP1〜RP2）、C1……コンデンサ、VBB……異常
時電圧源。1 (a) and 1 (b) are cross-sectional views and circuit diagrams of one embodiment of the present invention, FIG. 2 is a circuit diagram of internal connections and peripheral circuits when this embodiment is used, and FIG. It is a circuit diagram of an example of a conventional ceiling current supply circuit. 1 ... Heat generation type sealing current supply circuit, 2 ... Digital subscriber circuit, 3 ... Abnormal voltage source, 4 ... Subscriber line and termination impedance, 5 ... Subscriber line, 10 ...
Substrate, 11 …… Terminal, 12 …… Thick film resistor (R 1 to R 4 ), 13 ……
PTC resistor (R P1 to R P2 ), C 1 …… Capacitor, V BB …… Abnormal voltage source.
Claims (1)
電圧源からの電流を供給するシーリング電流供給回路に
おいて、前記各抵抗が厚膜抵抗からなりセラミック基板
の一面に配設されると共に、前記各抵抗に直列に正の温
度係数をもつPTC抵抗がそれぞれ接続されかつ前記セラ
ミック基板の地面上に配設されることにより、前記加入
者線路に過電圧が印加された時前記PTC抵抗値が大きく
なり、これら抵抗に流れる電流が制限されて熱破壊を防
止したことを特徴とするシーリング電流供給回路。1. A ceiling current supply circuit for supplying a current from a voltage source to both ends of a subscriber line via resistors respectively, wherein each resistor is a thick film resistor and is disposed on one surface of a ceramic substrate. The PTC resistance having a positive temperature coefficient is connected in series to each of the resistors and is disposed on the ground of the ceramic substrate, so that the PTC resistance value is large when an overvoltage is applied to the subscriber line. The sealing current supply circuit is characterized in that the current flowing through these resistors is limited to prevent thermal destruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1088782A JP2544803B2 (en) | 1989-04-07 | 1989-04-07 | Ceiling current supply circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1088782A JP2544803B2 (en) | 1989-04-07 | 1989-04-07 | Ceiling current supply circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02266750A JPH02266750A (en) | 1990-10-31 |
| JP2544803B2 true JP2544803B2 (en) | 1996-10-16 |
Family
ID=13952419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1088782A Expired - Fee Related JP2544803B2 (en) | 1989-04-07 | 1989-04-07 | Ceiling current supply circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2544803B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5077630A (en) * | 1990-03-28 | 1991-12-31 | Delta Design And Development Co. | Integrated services digital network terminating resistor with line fault protector |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58108857A (en) * | 1981-12-23 | 1983-06-29 | Fujitsu Ltd | Overcurrent protecting circuit |
-
1989
- 1989-04-07 JP JP1088782A patent/JP2544803B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02266750A (en) | 1990-10-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |