JP2543354Y2 - Video signal A / D converter - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal A / D converter of an image processing apparatus compatible with the NTSC system, and more particularly to a device capable of automatically setting a reference voltage of an A / D conversion IC. It is.

[0002]

2. Description of the Related Art FIG. 3 is a waveform diagram showing an NTSC composite signal. 2. Description of the Related Art Conventionally, as a general method of an A / D converter for a video signal, there is a pedestal clamp circuit.
This is a circuit for processing an NTSC composite signal, and is a circuit for clamping a pedestal level (hereinafter simply referred to as PL) in FIG. 3 to a reference voltage (DC 0 V). The processed NTSC composite signal is A / D
Input to the converter. At this time, the reference voltage of the A / D converter is of a type that is adjusted by a variable resistor or the like, or a type that inputs a non-adjusted constant voltage.

[0003]

However, in the type in which the reference voltage is adjusted by a variable resistor or the like, the adjustment must be performed while observing the waveform of the NTSC composite signal, and it is difficult for the user to perform the adjustment. Yes, and it has to be adjusted each time an input device such as a video camera is replaced. On the other hand, the type which inputs a constant voltage without adjustment has a problem that the resolution of the A / D converter is deteriorated and the error due to the difference of the input device is increased.

The present invention has been made in view of the above-mentioned problems of the prior art, and the NT input to an A / D converter is provided.
A PL and a sync tip level (hereinafter simply referred to as SL) are detected from the SC composite signal, and a white level (hereinafter simply referred to as WL) and a black level (hereinafter simply referred to as B) are obtained from the detected values.
L is calculated and input as a reference voltage of the A / D converter, thereby realizing a high resolution of the A / D converter and eliminating an error of the input signal due to replacement of the input device. It is intended to provide a signal A / D converter.

[0005]

To solve the above-mentioned problems, the configuration of the present invention comprises an SL detection hold circuit for detecting an SL of an NTSC composite signal, and a PL detection hold for detecting a PL of an NTSC composite signal. Hold circuit, a backport pulse generating circuit connected to the PL detection hold circuit for generating a signal indicating a backport period during the horizontal scanning period, and an SL detected by the SL detection hold circuit and the SL. A differential amplifier circuit for calculating a WL which amplifies a difference from the PL detected by the PL detection hold circuit; an SL detected by the SL detection hold circuit; and a SL detected by the PL detection hold circuit. A differential amplifier circuit for calculating BL, which amplifies the difference between the PL, and a difference between the PL detected by the PL detection hold circuit and the PL obtained by the differential amplifier circuit for calculating WL, and WL; And WL calculation adder circuit that, the PL
B for adding the difference between the PL detected by the detection hold circuit and the PL and BL calculated by the differential amplifier circuit for calculating BL.
An L-calculating addition circuit, the WL determined by the WL-calculating addition circuit, and the BL determined by the BL-calculating addition circuit are input as reference voltages and the NT
An A / D converter capable of inputting an SC composite signal is provided.

[0006]

According to the present invention, the reference voltage of the A / D converter is automatically set according to the NTSC composite input signal. This eliminates the need for readjustment by replacing the input device, and realizes high-resolution conversion of the A / D converter.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a video signal A / D converter according to the present invention. In the waveform diagrams of the NTSC composite signal shown in FIGS. 1 and 3, 1 is an SL detection hold circuit having a function of detecting the SL of the NTSC composite signal, and 2 is a PL detection circuit having a function of detecting the PL of the NTSC composite signal. Hold circuit 3, PL detection hold
Hold circuit 2 and the PL detection hold circuit 2
Is a back-porch pulse generating circuit for generating a signal for notifying that it is a back-porch period (the level at this time is PL) during the horizontal scanning period in order to detect the period. 4
WL amplifies the difference between SL detected by SL detection hold circuit 1 and PL detected by PL detection hold circuit 2.
The differential amplifying circuit 5 for calculation has SL detected by the SL detection hold circuit 1 and P detected by the PL detection hold circuit 2.
BL calculation differential amplifier circuit for amplifying the difference from L, 6 is WL
WL obtained by adding the value calculated by the calculation differential amplifier 4 and the PL detected by the PL detection hold circuit 2 to obtain WL
The calculation addition circuit 7 is a BL calculation addition circuit for adding the value calculated by the BL calculation differential amplifier circuit 5 and the PL detected by the PL detection hold circuit 2 to obtain BL. 8
Is an A / D converter, and the WL calculated by the WL calculation addition circuit 6 and the BL calculated by the BL calculation addition circuit 7 are shown.
Is input as the reference voltage, and NT
An A / D converter to which an SC composite signal is input as an analog voltage.

In such a configuration, FIG. 2 is a diagram showing an example of the output voltage of each circuit constituting the device of FIG. 1 and 2, the SL detection hold circuit 1 converts the NTSC composite input signal shown in FIG.
The SL shown in (b) is detected. Similarly, the PL detection
The PL shown in FIG.
The SL detected by the SL detection hold circuit 1 and the PL detected by the PL detection hold circuit 2 are input to a WL calculation differential amplifier circuit 4 and a BL calculation differential amplifier circuit 5, respectively. Here, for example, the value of each level of the NTSC composite signal is shown in FIG. From FIG. 3, the difference between SL and PL (referred to as sync amplitude) is 40 IRE. Also,
The difference between PL and WL is 100 IRE. Therefore,
In the differential amplifier 4 for WL calculation, the sync amplitude (40IR
If E) is multiplied by 100/40, the difference between PL and WL is obtained (FIG. 2 (d)). That is, the differential amplifier circuit 4 for WL calculation
Is expressed as: output = (PL-SL) × 100/40. P calculated by the differential amplifier 4 for calculating WL
The difference between L and WL (100 IRE) and the PL (0 IRE) detected by the PL detection hold circuit 2 are input to the WL calculation addition circuit 6 and added. The sum is WL (100
IRE) (FIG. 2E). That is, the output WL of the WL calculation addition circuit 6 is expressed as WL = PL + (PL−SL) × 100/40. Similarly, the difference between PL and BL is 5IRE. Therefore, if the sync amplitude (40 IRE) is multiplied by 5/40 in the BL calculation differential amplifier circuit 5, PL and BL
Is obtained (FIG. 2F). That is, the output of the BL calculation differential amplifier circuit 5 is expressed as follows: output = (PL−SL) × 5/40. The P calculated by the BL calculation differential amplifier circuit 5
Difference between L and BL (5IRE) and PL detection hold circuit 2
The PL (0IRE) detected in is input to the BL calculation addition circuit 7 and added. The sum is BL (5IRE)
(FIG. 2 (g)). That is, the output BL of the BL calculation addition circuit 7 is expressed as follows: BL = PL + (PL−SL) × 5/40. The output WL of the WL calculation addition circuit 6 is A /
The output BL of the adder 7 for BL calculation is connected to the + reference input of the D converter 8 and the -reference input of the A / D converter 8 respectively.

In this manner, the input NTSC
PL and SL are detected from the composite signal, WL and BL are calculated from the values, and the WL and BL are input as reference voltages of the A / D converter. Therefore, according to the NTSC composite input signal, the A / D
The reference voltage of the converter can be automatically set.

[0010]

As described above, according to the present invention, the reference voltage of the A / D converter is automatically set in accordance with the NTSC composite input signal. . Therefore, readjustment due to replacement of the input device is eliminated, and conversion with higher resolution of the A / D converter can be realized. Furthermore, even if the NTSC composite signal input to the A / D converter is processed and the DC level or amplitude changes, as long as it is within the analog input range of the A / D converter.
It is possible to realize a video signal A / D converter having an effect that the pedestal clamp circuit shown in the prior art can be dispensed with.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a video signal A / D converter of the present invention.

FIG. 2 is a diagram showing an example of an output voltage of each circuit constituting the device in FIG. 1;

FIG. 3 is a waveform diagram showing an NTSC composite signal.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 sync chip level detection hold circuit 2 pedestal level detection hold circuit 3 backport pulse generation circuit 4 differential amplifier circuit for calculating white level 5 differential amplifier circuit for calculating black level 6 adder circuit for calculating white level 7 black Adder circuit for level calculation 8 A / D converter

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-56-169478 (JP, A) JP-A-60-247378 (JP, A) JP-A-1-212190 (JP, A)

Claims (1)

(57) [Scope of request for utility model registration] 1. A sync tip level detection hold circuit for detecting a sync tip level of an NTSC composite signal, a pedestal level detection hold circuit for detecting a pedestal level of an NTSC composite signal, and the pedestal level detection hold A backport pulse generating circuit connected to the circuit for generating a signal indicating a backport period during a horizontal scanning period; a sync tip level detected by the sync tip level detection hold circuit; and a pedestal level detection hold A differential amplifier circuit for calculating a white level for amplifying a difference between the pedestal level detected by the circuit and a sync chip level detected by the sync chip level detection hold circuit and detected by the pedestal level detection hold circuit Black level calculation that amplifies the difference from the adjusted pedestal level And a white level calculation circuit for adding a difference between the pedestal level detected by the pedestal level detection hold circuit and the pedestal level calculated by the white level calculation differential amplifier circuit and the white level. An adder circuit; and a black level calculating adder circuit for adding a difference between the pedestal level detected by the pedestal level detection hold circuit and the pedestal level obtained by the black level calculating differential amplifier circuit and the black level. An A / D converter capable of inputting the white level obtained by the white level calculating adder and the black level obtained by the black level calculating adder as reference voltages and inputting the NTSC composite signal. And a video signal A / D converter.