JP2830545B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for processing a video signal of a color television receiver or the like.

[0002]

2. Description of the Related Art As a conventional video signal processing apparatus, for example, there is one having the configuration shown in FIG. In FIG. 13, 50 and 51 are operational amplifiers, 52 is a digital / analog converter (hereinafter referred to as D / A converter), 53 is an analog / digital converter (hereinafter referred to as A / D converter), and 54 is A buffer, 55, 56, 57, 58, 59, 60 are resistors, 61, 62, 63, 64 are transistors, 65 is a power supply, and 66 is a variable resistor.

A video signal becomes one input of an operational amplifier 50, and the output signal is supplied to a base of a transistor 62 of an amplifier circuit composed of a transistor 61 and a transistor 62. The power supply 65 provided at the base of the transistor 61 is a bias power supply for flowing a predetermined current to the transistors 61 and 62. The gain is stabilized by feedback from the emitter of the transistor 62 to the other input of the operational amplifier 50 via the resistor 56.

A resistor 58, a resistor 55 and a transistor 6
1 and the video signal obtained by the transistor 62 at a predetermined amplification level
And the base of both transistors of the video output amplifier circuit constituted by the transistor 64, and the CRT is driven from the emitters of the transistor 63 and the transistor 64.
The video signal of the collector of the transistor 61 is divided by the resistor 55, the resistor 59 and the resistor 60, and supplied to the buffer 54 from the intersection of the resistor 59 and the resistor 60.
After matching the interface for supplying the video signal to the A / D converter 53 at 4, the video signal is supplied to the input of the A / D converter 53.

The difference between the black level V0 of the video signal input to the A / D converter 53 and the reference voltage Vref set to a predetermined value by the variable resistor 66 is as shown in FIG. . In FIG. 14, an input video signal is connected to each stage by a capacitor.
The video signal having a low APL as shown in FIG.
The difference between the reference voltage Vref and the black level V0 is as large as V1,
In a video signal having a high APL as shown in FIG. 14B, the difference between the reference voltage Vref and the black level V0 is as small as V2.
As shown in FIG. 14, the black level of the video signal changing by APL or the like is represented by A /
The D converter 53 subdivides and captures the digital signal. The A / D converter 53 also subdivides and takes in the reference voltage Vref as a digital signal, and outputs the difference between the two subdivided digital signals. The D / A converter 52 is A
The output of the / D converter 53 is converted into an analog signal and output to the operational amplifier 51.

The operational amplifier 51 decreases the output voltage if V0> Vref, and increases the output voltage if V0 <Vref. Since the output of the operational amplifier 51 is one input of the operational amplifier 50 through the resistor 57, the output finally converges to V0 = Vref.

As a result, the bias change due to the temperature drift of the transistors 61 and 62 is digitized by the A / D converter 53 and is detected by subdividing it.
, It is possible to accurately fix the black level of the video signal to a predetermined voltage.

[0008]

However, in the above configuration, even if the CRT characteristic changes with time and the cutoff level fluctuates, it cannot be detected, so that the black level actually fluctuates. Further, since the DC component of the video input greatly changes due to the brightness adjustment, the transistor 6
There is a problem that it is necessary to design a wide dynamic range of the amplifier circuit constituted by the circuits 1 and 62.

In view of the above, the present invention has been made in consideration of the AP of a video signal.
It is an object of the present invention to provide a video signal processing apparatus that suppresses a change in black level due to a change in L and a change in black level due to a change in CRT characteristics and always reproduces a good black level.

[0010]

SUMMARY OF THE INVENTION The present invention comprises a generating means for generating a test signal for controlling the brightness of a displayed image;
Superimposing means for superimposing a test signal from a generating means on a retrace period of a video signal; and a feedback type first for performing DC reproduction in a retrace period other than the test signal superimposing period of the video signal from the superimposing means.
DC regeneration means, a second DC regeneration means coupled to an output of the first DC regeneration means and performing DC regeneration in a test signal period superimposed on a video signal, and an output of the second DC regeneration means as a load. Current detecting means for detecting a test signal from the load current supplied and induced in the load and returning the test signal to the second DC regeneration means.

[0011]

According to the present invention, the first feedback control loop controls the dynamic fluctuation of the reference level of the video signal due to aperture control, matrix processing, ABL, etc. By controlling the static fluctuation of the level by the second feedback control loop, the black level of the output image can always be kept constant.

Further, by superimposing the test signal during the blanking period of the video signal, tracking of the luminance of G, B, and R can be easily performed. Further, a test signal for controlling the luminance is superimposed on the vertical retrace period and the horizontal retrace period, and the cathode current is detected for each vertical retrace period, and the horizontal retrace is performed based on the signal detected for each vertical retrace period. By clamping the test signal for each period, control by detecting the cathode current can be equivalently performed for each horizontal retrace period.

[0013]

FIG. 1 is a block diagram of a video signal processing apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a superimposing unit for superimposing a test signal on a blanking period of a video signal, 11 denotes a first DC reproducing unit,
2 is an amplifier circuit for generating a CRT drive signal, 13
Is a second DC regeneration unit, 14 is a current detection unit that detects a test signal from a cathode current induced by a video signal,
Reference numeral 15 denotes a signal generation unit that detects a reference level of a video signal from an output of the amplifier circuit 12 and generates a signal for controlling the first DC reproduction unit 11, and 16 denotes a generation unit that generates a test signal to be superimposed by the superimposition unit 10. is there.

In FIG. 1, a loop composed of a first DC regeneration unit 11, an amplifier circuit 12, and a signal generation unit 15 is defined as a first feedback control loop. The loop configured by the unit 14 is referred to as a second feedback control loop. The operation of the video signal processing apparatus according to this embodiment configured as described above will be described below.

The generator 16 generates a test signal whose amplitude changes by adjusting the brightness volume. This test signal is a signal for tracking the luminance of the video signal. Thereafter, this test signal is transmitted to the BRP ( B
R IGHTNESS P ULSE). Further, the generation unit 16 generates a sampling pulse for detecting a change in the clamp pulse or the BRP. The generation timing of these pulses will be described later.

Next, the operation of the superposition unit 10 will be described in detail with reference to FIG. In FIG. 2, reference numeral 101 denotes a video signal clamp circuit, 102 denotes a switch circuit, and 103 denotes a test signal clamp circuit. In FIG. 2, the pedestal level of the video signal is clamped by a video signal clamp circuit 101, the test signal BRP is clamped by a test signal clamp circuit 103, and the output thereof is input to a switch circuit 102. The switch circuit 102 switches and outputs a video signal and a test signal according to a switch control signal. As a result, the output of the switch circuit 102 becomes a signal in which the test signal is superimposed during the blanking period of the video signal. The BRP signal is superposed equally on both the amplitude and the phase during the retrace period of each of the G, B, and R video signals.

Next, the operation of the first feedback control loop will be described with reference to FIG. The first feedback control loop is a feedback clamp loop that controls DC reproduction of the pedestal level of the video signal in the first DC reproduction unit 11. In FIG. 3, reference numeral 11 denotes a first DC regeneration unit;
Denotes an amplification circuit, 150 denotes a level shift circuit, 151 denotes a sample and hold circuit, and 152 denotes a comparator.

The output of the amplifier circuit 12 is adjusted to an appropriate amplitude by the level shift circuit 150, and the sample and hold circuit 151
Is input to The sample hold circuit 151 detects a pedestal level from the output of the amplifier circuit 12 every horizontal retrace period. The comparator 152 is connected to the sample hold circuit 15
The pedestal level detected in step 1 is compared with the reference voltage VP, and a control voltage is output to the first DC regeneration unit 11 so that the output of the amplifier circuit 12 always performs a constant DC regeneration. At this time, the reference voltage VP is selected such that the frequency characteristics and the linearity of the amplifier circuit 12 are always in the best operation state. As a result, the output of the amplifier circuit 12 becomes
The video signal is pedestal-clamped every horizontal period by the first feedback control loop.

Next, the second feedback control loop will be described with reference to FIG. The second feedback control loop is also a feedback clamp loop. (FIG. 4)
Reference numeral 3 denotes a second DC regeneration unit; 140, a current detector; 141, a current-voltage converter (hereinafter, referred to as an IV converter); 142, a sample-and-hold circuit;
43 is a comparator.

In FIG. 4, the current detector 140 is
The output of the second DC regeneration unit 13 is supplied to the cathode, and the cathode current induced by the video signal is detected. The current signal detected by the current detector 140 is output from the IV converter 1
At 41, the current signal is converted to a voltage signal. The sample and hold circuit 142 detects and holds a signal based on BRP from the output of the IV converter 141. Further, the comparator 143 compares the output V2 of the sample and hold circuit 142 with the reference signal VB, and generates a signal for controlling the DC regeneration unit 13 so that V2 always equals VB. The DC regeneration unit 13 uses the control signal from the comparator 143 to output the BR
The peak value level of P is clamped, and DC reproduction of the video signal is performed. As a result, the video signal input to the cathode is controlled such that the cathode current induced by the BRP is always constant.

Next, adjustment of brightness will be described. As shown in FIG. 5, the brightness of the image is proportional to the third power of the voltage V _CRT from the cutoff level of the CRT drive signal. Generally, the cutoff levels of G, B, and R are different. However, by adjusting VB in G, B, and R, the peak level of the BRP can be adjusted to the cutoff level. As a result, as shown in FIG. 6, if the amplitude of the BRP is changed, the voltage relative to the cutoff level changes and the luminance changes.
In FIG. 6, the voltages from the cut-off levels of the G, B, and R CRT drive signals before and after increasing the brightness are VbG, VbB, VbR, and VbG ′, Vb, respectively.
If B 'and VbR', the BRP is superimposed on G, B and R with the same amplitude, so that VbG'-VbG = VbB'-VbB = Vb
R′−VbR, and the change in luminance becomes uniform for G, B, and R, and the brightness can be adjusted.

Here, the brightness and bias adjustment reference is not the pedestal level or the like but the voltage of the peak value of the BRP. This is because the hue changes depending on the gradation. The description will be made in detail with reference to (FIG. 7), (FIG. 8), and (FIG. 9).

When the pedestal level is used as a reference for adjusting the bias without superimposing the BRP, the contrast and brightness are adjusted as shown in FIG. FIG. 8 shows how the hue changes at the final gradation of the staircase wave when the pedestal level is set to the reference potential when the contrast is changed from the upper stage (a) to the lower stage (b). It was done. The hue is determined by the brightness ratio of GBR, and the brightness ratio is proportional to the voltage ratio from the reference potential. In the upper stage (FIG. 8), the voltage ratio from the clamp level, which is the reference potential, to the last stage of the staircase wave is, for example, VBG: VBB: VBR = 33: 23: 13, whereas in the lower stage, the voltage ratio is The ratio becomes, for example, VBG ': VBB': VBR '= 18: 13: 8, and the hue changes.

FIG. 9 shows a case where the BRP pulse is superimposed and the amplitude of the BRP pulse also changes with the change of the contrast amount. Unlike FIG. 8 (FIG. 9), the voltage ratio between the reference potential of each GBR and the last stage of the staircase wave is, for example, VBG even if the contrast changes from the upper stage (a) to the lower stage (b). : VBB: VBR = VBG ': VBB': VBR '= 13: 8:
3 and thus no change in hue.

As described above, the first feedback control loop clamps the video signal every horizontal period to remove horizontal sag due to APL change, aperture control, and the like, and further, the amplifier circuit 12 operates optimally. Thus, the DC value of the video signal is monitored. As a result, the dynamic range of the amplifier circuit 12 can be designed to be narrow, and the power consumption of the circuit can be reduced. The control of the second feedback control loop is as follows:
Since the fluctuation of the cathode current is monitored, even if the cathode current fluctuates due to the time-dependent change of the CRT characteristic, the fluctuation is suppressed automatically.

Next, FIG. 10 shows a circuit diagram of the second feedback control loop. In FIG. 10, 31 is a PNP transistor, 32 is a diode, 33 is a resistor, 34,
35 is a buffer, 36 is a switch, 37 is a hold capacitor, 38 is an operational amplifier, 39 is an analog switch,
40 is a capacitor and 41 is a resistor.

FIGS. 11 and 12 are timing charts of each pulse generated by the generator 16. FIG.
(FIG. 11) shows a case where the video signal is viewed during the horizontal retrace period. (FIG. 11 (a)) is a video signal, (FIG. 11 (b)) is a BRP, and (FIG. 11 (c)) is a sample hold. Circuit 15
One sampling pulse (FIG. 11D) is a control signal for the analog switch 39.

FIG. 12 shows a case where the video signal is viewed during the vertical blanking period. FIG. 12A shows the video signal and FIG.
2 (b)) is the BRP, (FIG. 12 (c)) is the sampling pulse of the sample and hold circuit 151, (FIG.
(D)) is a control signal of the analog switch 39,
FIG. 12E shows a sampling pulse of the sample hold circuit 142.

The cathode current Ik induced at the cathode by the video signal applied to the base of the PNP transistor 31 passes through the emitter of the PNP transistor 31 and almost entirely flows from the collector to the resistor 33. The cathode current flowing into the resistor 33 is subjected to current-voltage conversion, and Vk = IkR (R: resistance value of the resistor 33)
Becomes The buffers 34 and 35, the switch 36, and the hold capacitor 37 constitute a sample and hold circuit. The signal that has been converted in voltage by the resistor 33 and passed through the buffer 34 is converted into a peak value level signal VkB of the BRP for each vertical retrace period by opening and closing a switch 36 controlled by a sampling pulse shown in FIG. Only passes through and is stored in the hold capacitor 37. VkB is buffer 3
After 5, it is compared with the reference signal VB by the operational amplifier 38.

The output of the operational amplifier 38 is shown in FIG.
The capacitor 40 is charged through the analog switch 39 which opens and closes every horizontal retrace period by the pulse of (d)).
At this time, if VkB> VB in the operational amplifier 38, the charging voltage of the capacitor 40 increases, so that the base potential of the PNP transistor 31 increases and the PNP transistor 31
The cathode current flowing into the emitter of the transistor decreases. Therefore, VkB also decreases. In addition, VkB <VB
Then, since the charging voltage of the capacitor 40 decreases,
The base potential of the PNP transistor 31 drops,
The cathode current flowing into the emitter of the transistor 31 increases. Therefore, VkB increases. As a result, the peak value of the BRP finally becomes the operational amplifier 38 every horizontal retrace period.
Converges to a level where VkB = VB.

The reason why the detection of the cathode current is performed only from the BRP superimposed for each vertical blanking period depends on the characteristics of the cathode current detection circuit composed of the PNP transistor 31 and the resistor 33. The current due to the BRP must be set at several μA to several tens μA so as not to impair the image quality of the output image. At such a low current, the pulse characteristics of the detection circuit are poor, and a signal due to BRP cannot be detected in a short period such as a horizontal blanking period. Therefore, by superimposing a BRP having a wide pulse width in the vertical flyback period, a low-current signal is detected without affecting the signal in the effective scanning period.

By detecting the BRP superimposed in each vertical blanking period and clamping the BRP in each horizontal blanking period based on this detection signal, the control of the cathode current by the BRP is equivalently performed in each horizontal blanking period. Can be done.

As described above, the dynamic control of the black level due to the change in the signal level of the APL or the like and the static fluctuation of the black level due to the change in the CRT characteristic are suppressed by the two feedback control loops of the DC regeneration. Reproduces a good black level. Further, by superimposing and monitoring a test signal equal to G, B, and R, it is possible to easily and favorably track the luminance.

Note that the present embodiment is an example of a television receiver, and does not limit equipment in which the present apparatus is incorporated. Also, the operation of the first feedback control loop has been described as clamping the pedestal level of the video signal.
Another level may be set as the reference level of the video signal, and the operation may be such that the level is clamped.

The BRP for current detection superimposed on the vertical flyback period has been described with reference to FIG. 12 (b). It is not limited. Further, the operation of the superimposing unit 10 has been described in the superimposition method by switching between the video signal and the test signal using the switch circuit 102. For example, a test signal is added to the video signal, or the test method is applied to the video signal by another method. It goes without saying that the signal may be superimposed.

[0036]

As described above, according to the present invention, the system is constituted by two DC reproduction circuits, namely, a feedback clamp for holding the optimum bias of the operation of the amplifier circuit and a feedback clamp for adjusting the brightness of the video signal. Can improve the overall frequency characteristics and dynamic range.

Further, in the present invention, since the control is performed by detecting the cathode current, it is possible to detect the characteristic change on the CRT side and automatically suppress the change. Further, in the present invention, the detection of the cathode current by the test signal is performed for each vertical blanking period, and the test signal for each horizontal blanking period is clamped based on the signal detected for each vertical blanking period. Since control by detection can be equivalently performed for each horizontal retrace period, the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a superimposing unit of the embodiment.

FIG. 3 is a block diagram showing a detailed configuration of a first feedback control loop of the embodiment.

FIG. 4 is a block diagram showing a detailed configuration of a second feedback control loop of the embodiment.

FIG. 5 is a waveform diagram of a video signal for explaining the operation of the embodiment.

FIG. 6A is a diagram showing GBR waveforms of a CRT drive signal according to the embodiment. FIG. 6B is a graph showing a case where the brightness is increased from the state shown in FIG.
GBR waveform chart of RT drive signal

7A is a waveform diagram of a video signal. FIG. 7B is a waveform diagram of a video signal in which contrast is increased from the state of FIG. Waveform diagram when raised

8A is a waveform diagram of a video signal based on a pedestal level. FIG. 8B is a waveform diagram when the contrast is lowered from the state of FIG.

9A is a waveform diagram of a video signal based on the level of the peak value of BRP. FIG. 9B is a waveform diagram when the contrast is lowered from the state of FIG. 9A.

FIG. 10 is a circuit diagram of a first feedback control loop of the embodiment.

FIG. 11 is a timing chart of each pulse during a horizontal retrace period showing the operation of the embodiment.

FIG. 12 is a timing chart of each pulse in a vertical flyback period showing the operation of the embodiment.

FIG. 13 is a block diagram showing a configuration of a conventional video signal processing device.

14A is a waveform diagram of a video signal for explaining the operation of the conventional example. FIG. 14B is a waveform diagram of a video signal having a higher APL than the state of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Superposition part (superposition means) 11 1st direct current reproduction | regeneration part (1st direct current reproduction | regeneration means) 12 Amplifier circuit 13 2nd direct current reproduction | regeneration part (2nd direct current reproduction | regeneration means) 14 Current detection part (current detection means) 15 Signal generator (signal generator) 16 Generator (generator)

Continuation of the front page (56) References JP-A-60-186185 (JP, A) JP-A-50-88927 (JP, A) JP-A-3-79167 (JP, A) JP-A-1-2502072 (JP, A) , A) Hikaru 1-162972 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/14-5/217

Claims (2)

(57) [Claims] A generating means for generating a test signal for controlling the luminance of a display image; a superimposing means for superimposing the test signal from the generating means on a blanking period of a video signal; A feedback-type first DC regeneration unit that performs DC regeneration in a flyback period other than the test signal superimposition period of the output signal of the superimposition unit; and an output of the first DC regeneration unit, wherein the test signal is A second DC regeneration unit for performing DC regeneration in the superimposed period, supplying an output from the second DC regeneration unit to a load, detecting the test signal from a load current induced in the load, A video signal processing device comprising: a current detection unit that feeds back a detection signal to the second DC regeneration unit. A generating means for generating a test signal during a horizontal retrace period and a vertical retrace period of the video signal; a current detecting means for detecting a current based on the test signal during the vertical retrace period; 2. The video signal processing apparatus according to claim 1, wherein said means performs DC reproduction using the test signal during a horizontal blanking period.