JP2543353Y2 - Automatic gain adjustment device for image reading device - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain adjusting device for an image reading device, and more particularly, to an image reading portion, and an A / D converter for converting an analog image signal read by the image reading portion into a digital signal. The present invention relates to an automatic gain adjusting device for an image reading device provided between the automatic gain adjusting device and the image reading device.

[0002]

2. Description of the Related Art In an image forming apparatus such as a facsimile apparatus, image information read by a CCD sensor or the like is converted into a digital signal by an A / D converter and input to an image processing circuit. In this case, particularly when a color background document or the like is read, the intensity of an image signal such as a character is lower than that of a normal white background document. In order to avoid a change in contrast on an image due to a decrease in the image signal intensity, in a conventional facsimile apparatus, an automatic gain adjustment circuit (hereinafter, referred to as an AGC circuit) is provided before an A / D converter.
Is provided.

[0003] In an AGC circuit in a conventional facsimile apparatus, the signal strength of an image signal itself input to an analog signal input terminal of an A / D converter is adjusted to control the level of an output signal of the A / D converter.

[0004]

As described above, in the conventional AGC circuit, the signal strength of the image signal itself is adjusted. Therefore, in order to perform A / D conversion with high accuracy, it is necessary to configure an AGC circuit having good linearity. To realize such an AGC circuit,
An expensive FET transistor with good linearity is required, resulting in an increase in the cost of the entire device.

An object of the present invention is to provide excellent linearity.
Another object of the present invention is to provide an automatic gain adjusting device for an image reading device which does not require expensive FET transistors.

[0006]

An automatic gain adjusting device for an image reading apparatus according to the present invention comprises an image reading section for reading an image of a document, and an analog image signal read by the image reading section. This is a device provided between an A / D converter for converting into a digital signal and includes an A / D output level detecting means and a reference voltage controlling means. A / D output level detection means from the A / D converter
The signal level of the image data of the output original is detected.
The reference voltage control means controls the reference voltage of the A / D converter according to the detection result of the A / D output level detection means. Then, the reference voltage control means includes:
It has a charge / discharge circuit for inputting an output voltage to a reference voltage terminal of the A / D converter, and a switch element. The switch element is provided between the charging / discharging circuit and the power supply, and is turned on and off in accordance with the detection result of the A / D output level detecting means.

[0007]

In the automatic gain adjusting device of the image reading apparatus according to the present invention, the output signal level of the A / D converter is detected. Then, the reference voltage of the A / D converter is controlled according to the detection result.

For example, when the output signal of the A / D converter is large, this is detected and control is performed so that the reference voltage of the A / D converter is increased. Specifically, when the output signal of the A / D converter is large, the switch element is turned on and the power supply charges the charge / discharge circuit.
The output voltage of this charging / discharging circuit is input to the reference voltage terminal of the A / D converter, which is equivalent to a decrease in the analog image input signal of the A / D converter compared with the reference voltage. The output signal level of the / D converter decreases. Conversely, when the level of the output signal of the A / D converter is low, the switch element is turned off. As a result, the voltage from the power supply is not supplied to the charge / discharge circuit, and the voltage charged in the charge / discharge circuit is discharged. As a result, the reference voltage decreases and the analog image input signal of the A / D converter relatively increases.

In the A / D converter, the linearity with respect to the reference voltage is good. Therefore, automatic gain adjustment with good linearity can be realized without using expensive FET transistors as in the conventional device.

[0010]

EXAMPLES Overall Configuration FIG. 1 is a general block diagram of a facsimile apparatus to which an embodiment of the present invention is employed. In FIG. 1, the present apparatus has a CPU 1 for controlling the whole system control, transmission of image information, communication control and network control. A ROM 2 and a RAM 3 for storing image data and the like are connected to the CPU 1 via a bus 4. Further, the CPU 1 includes a line memory and a control unit 5 thereof, and an information compression / decompression unit 6 for removing redundancy of image information and restoring redundancy, and for performing transmission control, error control, and the like. A communication control unit 7, a network control unit 8 connected to a line, a reading processing unit and a recording processing unit 9 for performing image processing for reading and recording, and an interface 1
0 is connected. Read processing unit and recording processing unit 9
Is connected to a reading scanning unit 11 including a CCD and the like, and a recording scanning unit 12 including a thermal head and the like. Further, a modem 13 for performing modulation and demodulation is connected to the communication control unit 7. The interface 10 is connected to a panel unit 14 in which key switches and a display unit are arranged, and a mechanism control unit 15 such as a driver and a sensor. The reading and recording processing unit 9 and the panel unit 14 are connected to each other via an interface 16.

[0011] shows a block diagram of an image data reading system of the image data reading system diagram 1 in Fig. The reading processing unit (and the recording processing unit) 9 is provided with an image processing circuit 20 for performing shading correction and dither processing for halftone image data. The CCD 21 of the scanning section 11 is driven by an image processing circuit 20 via a driver circuit 22.
A sample hold (SH) circuit 23, an automatic reference control (ARC) circuit 24, and an A / D converter are sequentially provided between the CCD 21 and an image processing circuit 20 for processing image data read by the CCD 21. 25 are connected. The sample hold circuit 23 is a circuit for temporarily holding each pixel data from the CCD 21 and removing a DC voltage superimposed on each pixel data. ARC circuit 24
Is a circuit for controlling the reference voltage of the A / D converter, as described later. A / D converter 2
Each pixel data digitized by 5 is stored in the RAM 26 (corresponding to the RAM 3 in FIG. 1) via the image processing circuit 20. Here, the A / D converter 25 of the present embodiment has a 6-bit configuration. The RAM 26 has an 8-bit configuration. In addition,
Fluorescent lamp 27 as a light source constituting reading scanning section 11
Are controlled to be turned on by the CPU 1 via the inverter 28.

[0012] FIG. 3 shows a schematic configuration of a reading scanning unit scanning and reading unit 11. The reading and scanning unit 11 includes the CCD 21 and the fluorescent lamp 27 as described above.
And At a position facing the CCD 21, a reference plate 30 which guides the conveyance of the document and serves as a white reference when generating shading correction data is arranged. And, between the CCD 21 and the reference plate 30,
A lens 31 is provided. A transport system 34 for transporting the original is provided between the original placing tray 32 and the discharge tray 33. The transport system 34 includes a paper feed roller 35 for taking in the original placed on the original placing tray 32 into the apparatus, first and second transport rollers 36 and 37 for transporting the original, And a motor 38 for driving the rollers. A document detection sensor 39 for detecting that a document is loaded is provided below the document loading tray 32.

ARC Circuit The ARC circuit 24 amplifies the signal from the sample and hold circuit 23 as shown in FIG.
5, an amplifier 24b for inputting to the analog signal input terminal of No. 5,
And a reference voltage control unit 24a connected to a reference voltage input terminal of the A / D converter 25. Reference voltage control unit 24
a is a circuit for controlling the reference voltage of the A / D converter 25 in response to the overflow signal from the A / D converter 25, and its circuit diagram is shown in FIG.

In FIG. 5, the reference voltage control section 24a has a switch 41 provided between the power supply 40 and the A / D converter 25. The switch 41 is provided for the shading correction circuit 5 of the image processing circuit 20.
2 (see FIG. 6), the on / off control is performed by the overflow signal. The data is turned on when the data after shading correction overflows, and is turned off when the data does not overflow. That is, the switch 41 has a function of detecting the output signal level after the shading correction. The power supply 40 and the switch 4
1, a resistor 42 is provided, and between the A / D converter 25 and the switch 41, an operational amplifier 43 as a buffer is provided. A capacitor 4 is provided between the switch 41 and the operational amplifier 43 and the ground.
4 and the resistor 45 are connected in parallel. The A / D converter 2 is configured by these capacitors 44 and the resistor 45.
5 means for controlling the reference voltage. A capacitor 46 is provided between the operational amplifier 43 and the A / D converter 25.

The image processing circuit then the image processing circuit 20 of the reading system by FIG 6 will be described in detail. The image processing circuit 20 includes a timing generation circuit 50 that exchanges signals with the CPU 1 and the driver circuit 22 for driving the CCD, a data conversion circuit 51 for generating shading correction data, and shading for performing shading correction. A correction circuit 52, a data timing operation circuit 53 including a line memory and exchanging data with the RAM 26, an area dividing circuit 54 for distinguishing between a halftone image and a binary image, and a binary image data An edge enhancement circuit 55 for performing edge enhancement processing on
It mainly has a comparator 56 for performing dither processing and the like.

When the shading correction data is read, the data conversion circuit 51
Is to convert the 6-bit parallel data output from the CPU into serial data. Further, the shading correction circuit 52 has a multiplication and division circuit 52b, for example, as shown in FIG. The shading correction data is input from the RAM 26 via the data conversion circuit 51, and the multiplication and division circuit 52b performs multiplication and division with the pixel data. The multiplication and division circuit 5
From 2b, an overflow signal indicating that the data after shading correction has overflowed is output to the ARC circuit 24.

As shown in FIG. 8, the data timing operation circuit 53 includes a 5-bit target pixel D0 used for image area division processing to be described later, and 2-bit 3-bit target pixels D0.
This is a circuit for writing and reading one peripheral pixel DA, DB, and DC to and from the RAM 26. Here, in the following description, the pixel DA is referred to as the current pixel before the previous line, the pixel DB is referred to as the previous pixel in the previous line, and the pixel DC is referred to as the current line current pixel. As shown in FIG. 9, the image area dividing circuit 54 includes a determining unit 54a and a data converting unit 54b. Discriminator 54a
Indicates whether the target pixel is a pixel forming a halftone image based on the pixel data from the data timing operation circuit 53,
This is a circuit for determining whether or not the pixel constitutes a binary image. The data conversion unit 54b is a circuit that forcibly converts the target pixel to a white or black level when it is determined that the target pixel is a pixel forming a binary image.

An I / O selector 57 for controlling data input / output is provided between the data conversion circuit 51 and the data timing operation circuit 53, and the RAM 26. In addition, the area increase division circuit 54 and the edge enhancement circuit 55
And a comparator 56, a selector 58 for selecting data from either one of the circuits is provided. Further, the image processing circuit 20 is provided with a halftone comparator level circuit 59 in which a comparator level to be set in the comparator 56 is stored, and a binary comparator level circuit 60. The halftone compare level circuit 59 stores dither pattern data for dither processing. This dither pattern
It consists of a dot matrix of n × n pixels, and n ²
The black-and-white determination threshold value of each pixel is changed for each pixel. By setting the dither pattern data to the comparator level of the comparator 56, dither processing can be performed. Also, the binary compare level circuit 60 stores level data for making a black / white determination in a plurality of stages. Each comparator level circuit 5
A selector 61 for selecting one of the two compare level circuits 59 and 60 is provided between the comparators 9 and 60 and the comparator 56. The selectors 58 and 61 are controlled by a control signal from the CPU 1.

System Control Next, the control operation of the entire system of the facsimile apparatus of this embodiment will be described with reference to the flowchart of FIG. When the program of the present apparatus starts, initialization is performed in step S1. Next, in step S2, it is determined whether a calling signal for communication has been received. In step S3, it is determined whether or not the original is placed on the original placing tray 32. Further, in step S4, it is determined whether or not a key for transmission has been pressed. In step S5, it is determined whether another key has been pressed.

When a calling signal is received from any of the calling terminals, the determination in step S2 is YES, and the process proceeds to step S6. In step S6, transmission control is performed with the destination terminal to prepare for communication.
Next, when the preparation for communication is completed, the process proceeds to step S7. In step S7, a signal indicating that the reception preparation is completed is transmitted to the destination terminal. In this state, waiting for transmission from the destination terminal side, and when a signal is sent, a reception process is executed in step S8.

At the time of the reception processing in step S8, the image information received from the line passes through the network control unit 8 and passes through the modem 1
And demodulated by the RAM 3 via the communication control unit 7 and the bus 4
3 is stored. The data stored in the RAM 3
The information is sequentially sent to the information compression / decompression unit 6, where the redundancy is restored, and sent to the line memory / control unit 5. Then, the image information once stored in the line memory / control unit 5 is sent to the recording scanning unit 12 via the recording processing unit 9, and is recorded and reproduced on a sheet. When the receiving process has been completed, “YES” is determined in the step S9, and the process returns to the main routine.

When an original is placed on the original placing tray 32 to send the original to the destination, this is detected by the original detection switch 39, and the program shifts from step S3 to step S10. . Step S
In 10, the document is taken in by rotating the paper feed roller 35 by a predetermined amount, and the first transport roller 36 nips the leading end of the document. Next, in step S11, the fluorescent lamp 27 is turned on. Thus, the reference plate 30 is irradiated with light.
Next, in step S12, the CCD 21 is driven to generate image data for shading correction (data of the reference plate 30).
Read. Then, in step S13, the shading correction data obtained in step S12 is stored in an extra area (details will be described later) in the RAM 26 in which image data is stored. Upon completion of the process in step S13, the process returns to the main routine.

Next, when the transmission key is pressed, the process proceeds from step S4 to step S20. Step S2
At 0, it is determined whether or not a document is placed on the document placing tray 32. If a document is not placed, the process proceeds to step S21, outputs an alarm, and returns to the main routine.

If the original is placed on the original placing tray 32, the process proceeds from step S20 to step S22. In step S22, transmission control is performed with the destination terminal to prepare for transmission. If a reception preparation completion signal has been sent from the destination terminal in this transmission control process, the process proceeds to step S23. In step S23, image information of the document is read. In this case, the original is first and second transport rollers 36 and 37.
And the information is read by the CCD 21. Next, in step S24, the shading correction data stored when the original is placed is read out and sent to the shading correction circuit 52.

Here, the shading correction data is supplied to a multiplication and division circuit 52b of the shading correction circuit 52, where the read pixel data and the shading correction data are multiplied and divided to perform shading correction.

Next, in step S25, it is determined whether or not image data subjected to image processing such as shading correction processing and edge enhancement processing has been sent from the image processing circuit 20. If image data has been sent, a transmission process is performed in step S26.

At the time of transmission processing, the data sent from the image processing circuit 20 is temporarily stored in the line memory / control unit 5. Then, while reading the image data from the line memory / control unit 5, the redundancy is removed, and the data is again stored in the RAM 3 via the bus 4. Next, data is read from the RAM 3 and transmitted to the modem 13 via the communication control unit 7. The modem 13 performs modulation, and the modulated signal is sent out to the line via the network control unit 8. In step S27, it is determined whether the transmission has been completed. When transmission of all originals is completed, the fluorescent lamp 27 is turned off in step S28, and the process returns to the main routine.

If another key is pressed, the flow shifts from step S5 to step S29 to execute a process corresponding to the pressed key and return to the main routine.

Shading Correction Data Creation Processing As shown in the flowchart of FIG. 10, the shading correction data is created by placing the original on the original placing tray 32 and taking it in by the paper feed roller 35 before the reference plate 30 This is performed based on the image data. When creating this shading correction data, A /
The reference voltage of the D converter 25 is kept constant. That is, in this process, the ARC circuit 24 continues to supply a constant reference voltage to the reference voltage input terminal of the A / D converter 25.

The image data of the reference plate 30 is converted into a digital signal by the A / D converter 25 and input to the image processing circuit 20. Here, the 6-bit digital data from the A / D converter 25 is input to the data conversion circuit 51 and the shading correction circuit 52. In the data conversion circuit 51, the 6-bit parallel signal is converted into serial data, and stored in the RAM 26 via the I / O selector 57 bit by bit. here,
The RAM 26 has an 8-bit configuration as described above, of which 5 bits are used for storing each pixel data, and 2 bits are used for storing peripheral pixel data in an area dividing process described later. Have been. Therefore, since one bit remains, the shading correction data converted into serial data is stored in the surplus one bit area.

As described above, since the 6-bit parallel data is converted into serial data and stored in the RAM 26, no shading correction data is created for the subsequent 5 pixels. Then, the shading correction data of the sixth pixel is converted from the parallel data to the serial data in the same manner as described above, and is stored bit by bit in an extra area in the RAM 26. By such a write operation, 6
One shading correction data is stored in RAM2 for each pixel.
6 will be stored.

Reading Operation of Document Image Information When the transmission key is pressed and an image data reading command is issued from the CPU 1 in step S23 of FIG. 11, the image information of the document is read in the following procedure. That is,
The CCD 21 is driven by the driver circuit 22 to output an analog image signal which is image information of the document. The analog image signal from the CCD 21 is input to the sample and hold circuit 23. This sample and hold circuit 2
In 3, the image signal is temporarily held, and the DC voltage superimposed on the image signal is removed. The output of the sample and hold circuit 23 is input to the A / D converter 25 via the amplifying unit 24b of the ARC circuit 24. Where AR
The C circuit 24 adjusts the level of the analog image signal from the sample and hold circuit 23 by an auto reference control operation described later. A / D converter 25
Then, the analog image signal is converted into a 6-bit digital signal and sent to the image processing circuit 20.

In the image processing circuit 20, the digital signal from the A / D converter 25 is converted to a shading correction circuit 5
2 is input. On the other hand, in synchronization with the input of pixel data,
The shading correction data is read out one bit at a time from the RAM 26, and these data are converted into 6-bit parallel data by the data conversion circuit 51. The shading correction circuit 52 performs the above-described shading correction using the pixel data and the shading correction data. With this operation, one piece of 6-bit parallel data is created for six consecutive pixels as shading correction data, and the shading correction data is updated every six pixels. This is shown in FIG. That is, the pixel data D1 to D6 are subjected to shading correction by the shading correction data C1, and the pixel data D7 to D12 are subjected to shading correction by the next shading correction data C2.

The data subjected to the shading correction as described above is input to the data timing operation circuit 53. The data timing operation circuit 53 stores the pixel data of the target pixel and the peripheral pixels in the RAM 26 while sequentially updating the pixel data of the target pixel and the peripheral pixels for the later-described area division processing. Then, the pixel data read from the RAM 26 is sent to the area dividing circuit 54. The area dividing circuit 54 performs an area dividing process described later and outputs 5-bit image data. The edge emphasis circuit 55 performs edge emphasis processing as binary image processing and outputs 7-bit or 8-bit pixel data. These pixel data are
The selection is made by the selector 58, and one of them is output to the comparator 56. The comparator receives the binary comparator level or the halftone comparator level (dither pattern) selected by the selector 61. Comparator 5
6 compares the comparator level with the pixel data and transfers the obtained data to the CPU 1. The selectors 58 and 61 are controlled by the CPU 1.
As a result, when the halftone mode is selected, the pixel data from the band dividing circuit 54 is compared with the halftone compare level, dither processing is performed, and the obtained halftone data is sent to the CPU 1. Will be transferred. In the case of the binary mode, the pixel data from the edge enhancement circuit 55 and the binary
The value comparison level is compared with the white or black
The value data is transferred to the CPU 1.

Auto Reference Control Operation When image data of an original is taken into the image processing circuit 20, A
The reference voltage of the A / D converter 25 is controlled by the output of the A / D converter 25 by the RC circuit 24. The image data from the CCD 21 is sent to the sample and hold circuit 23. The output of the sample and hold circuit 23 is amplified by the amplifying unit 24b of the ARC circuit 24 and input to the analog input terminal of the A / D converter 25. On the other hand, the overflow signal of the shading correction circuit 52 is input to the reference voltage control unit 24a, and the reference voltage controlled by the overflow signal is input to the reference voltage input terminal of the A / D converter 25.

For example, when the signal level of the analog image data output from the amplifier 24b is high, the A / D
An overflow occurs when the signal is converted into a digital signal in the converter 25 and is subjected to shading correction. When an overflow occurs, a signal to that effect controls the switch 41 of the reference voltage control unit 24a. That is, the switch 41 is activated by the overflow signal.
Is turned on, whereby the capacitor 44 is charged by the power supply 40. Then, the output voltage of the operational amplifier 43, which is the reference voltage of the A / D converter 25, increases. When the reference voltage increases in the A / D converter 25, the digital data after A / D conversion decreases. As a result, even when the level of the analog image signal is high, the reference voltage increases accordingly, so that the value of the digital data output from the A / D converter 25 decreases. Then, when no overflow occurs, the switch 41 is turned off. As a result, the electric charge charged in the capacitor 44 is gradually discharged through the resistor 45, and the reference voltage is also gradually reduced. As a result, the value of the digital data output from the A / D converter 25 increases, contrary to the above.

As described above, by changing the reference voltage of the A / D converter 25, the output data of the A / D converter 25 has the same effect as gain adjustment. For this reason, an auto gain control circuit using a field effect transistor or the like is not required in the preceding stage of the A / D converter 25, and an inexpensive circuit configuration can be achieved.

The increasing area division processing this increasing area division process, if the original is a photographic information and character information coexist, subsequent halftone to determine whether the character information is picture information for each pixel The data is sent to the comparator 56 as a processing unit.

First, the data timing operation circuit 53 reads 5-bit data of the current pixel of the previous line from the RAM 26 and writes 5-bit data of the current pixel of the current line from the shading correction circuit 52. Also,
In addition to reading out the 2-bit data of the current pixel of the previous line, the 2 bit data of the current pixel of the previous line read from the RAM 26 is read out.
Write bit data. Thus, the target pixel D
0 and its surrounding pixels DA and DB are prepared. These data and 2-bit data DC of the current line current pixel from the shading correction circuit 52 are input to the image area dividing circuit 54.

In the image area dividing circuit 54, the discriminating section 54a
, It is determined from the peripheral pixels DA, DB, and DC whether the center target pixel D0 is a pixel forming photographic information as a halftone image or a pixel forming character information as a binary image. . This determination is made with reference to the table shown in FIG.

For example, as shown in FIG. 13A, the upper two bits of the peripheral pixels DA, DB, and DC are each "1".
“0”, “01”, and “10” are intermediate densities, and the target pixel D0 (5 bits) is “F ₁₆ (hexadecimal)” (hereinafter simply referred to as F) and has an intermediate density. For example, the target pixel D0 is determined to be a halftone pixel (photo information). Also,
As shown in (B), the upper two bits of the peripheral pixel are “1”.
If the target pixel D0 is "8" and has a darker density, the target pixel D0 is determined to be character information, and the target pixel D0 is determined to be character information. Is black “0”. Also, as shown in (C), the upper two bits of the peripheral pixel are “00”, “01”,
If the target pixel is “01” and has an intermediate density or a dark density, and the target pixel is “1A” and has a whitish density, the target pixel is determined to be character information and is determined to be white “1”.
F ".

In this way, it is determined whether the target pixel is photographic information or character information in accordance with the density of the surrounding pixels, and in the case of photographic information, the pixel data is sent to the comparator 56 as it is. Here, a dither pattern for dither processing is passed. If the pixel data is determined to be character information, the pixel data is converted to pure white or pure black by the data conversion unit 54b, and then sent to the comparator 56 to pass a dither pattern for dither processing. As a result, even when the image reading process is performed in the halftone mode, the dither process is performed for the photographic information, and the characters are prevented from being blurred for the character information.

In the above embodiment, the present invention is applied to a facsimile apparatus. However, the present invention can be applied to other image reading apparatuses.

As described above, according to the present invention, since the automatic gain adjustment is performed by controlling the reference voltage of the A / D converter, the automatic gain adjustment with good linearity can be performed without using an expensive FET transistor as in the conventional device. It can be carried out. Further, since a charge / discharge circuit is used to control the reference voltage, the cost is lower.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of a facsimile apparatus to which an embodiment of the present invention is applied.

FIG. 2 is a block diagram of a reading system of the facsimile apparatus.

FIG. 3 is a schematic configuration diagram of a reading scanning unit of the apparatus.

FIG. 4 is a block diagram of an ARC circuit.

FIG. 5 is a circuit diagram of a reference voltage control unit of the ARC circuit.

FIG. 6 is a block diagram of an image processing circuit.

FIG. 7 is a block diagram of a shading correction circuit.

FIG. 8 is a layout diagram of pixels used for image area division processing.

FIG. 9 is a block diagram of an image area dividing circuit.

FIG. 10 is a control flowchart of the facsimile machine.

FIG. 11 is a control flowchart of the facsimile machine.

FIG. 12 is a diagram for explaining the operation of a shading correction unit.

FIG. 13 is a view for explaining the operation of the area increase division processing.

FIG. 14 is a view for explaining the operation of the area increase division processing.

[Explanation of symbols]

 21 CCD 24 ARC circuit 24a Reference voltage control unit 24b Amplification unit 25 A / D converter 41 Switch circuit 44 Capacitor 45 Resistance

Claims (1)

(57) [Scope of request for utility model registration] An image reading unit for reading an image of a document ;
An automatic gain adjusting device for an image reading device provided between the image reading unit and an A / D converter for converting an analog image signal read by the image reading unit into a digital signal, wherein the document output from the A / D converter is provided. Image data
A / D output level detecting means for detecting a signal level of the reference signal; and reference voltage control means for controlling a reference voltage of the A / D converter in accordance with a detection result of the A / D output level detecting means. A voltage control unit provided between the charge / discharge circuit and a power supply; and a detection result of the A / D output level detection unit. An automatic gain adjustment device for an image reading device, comprising: a switch element that is turned on and off according to the following.