JP2537902B2 - Basic logic circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit such as an inverter circuit or a NOR circuit, and a basic logic circuit preferably used in a frequency dividing circuit between analog and digital circuits.

Conventional technology Conventionally, FETs (field effect transistors), especially one of them, gallium arsenide metal-semiconductor FET (GaA
Many high-speed logic circuits using sMESFET) have been proposed that take advantage of the high speed and low power consumption of GaAs MESFET.

Such a high-speed logic circuit can be used as a silicon bipolar (Si
ECL (Emitter Coupled Logi) using a bipolar element
Compared to logic circuits such as c), it has the performance of extremely high speed and low power consumption. However, when a logic circuit of MSI (medium-scale integrated circuit) with several hundred gates or more is constructed, the performance is not as high as expected.

This is because the load driving capacity of Si bipolar element is almost proportional to the element current (collector current), while GaAsMESFET
It is only proportional to the 1/2 power of the device current (drain current), and the load driving capability of GaAs MESFET is inferior, and the deterioration of its operating speed is large when many loads are connected. caused by.

As a countermeasure against this, it has been conventionally performed to increase the load driving capability by providing a buffer formed by a source follower circuit in the logic circuit.
BFL (Buffered FET Logic) circuit, SBFL (Super Buffer)
FET Logic) is performed in the basic logic circuit such as the circuit.

FIG. 5 is an electric circuit diagram showing the BFL circuit 1. The FETs used in the BFL circuit 1 are all N-channel. Input terminal T
A high-level or low-level input signal Vin is applied to 1 and the input signal is applied to the gate terminal of a FET (hereinafter referred to as a transistor) Q1. The source terminal of transistor Q1 is grounded and its drain terminal is the transistor
Connected to the source terminal of Q2 and the gate terminal of transistor Q3. The gate terminal and the source terminal of the transistor Q2 are short-circuited. A positive voltage Vdd is applied to the drain terminals of the transistors Q2 and Q3.

The source terminal of transistor Q3 is diode D1, D2, D3
Via the output terminal T2 and the drain terminal of the transistor Q4. The gate terminal and the source terminal of the transistor Q4 are short-circuited, and a negative voltage Vss is applied to the source terminal.

In the above BFL circuit 1, the transistor Q2 is provided as a load and the transistor Q4 is provided as a constant current source. The diodes D1, D2, D3 are provided for the purpose of lowering the potential appearing at the source terminal of the transistor Q3 to an appropriate level as an output signal.

When the input signal Vin applied to the input terminal T1 is at high level, the transistor Q1 becomes conductive and the potential appearing at its drain terminal becomes low level. Therefore, a low level signal is given to the gate terminal of the transistor Q3,
The transistor Q3 is cut off, and the output signal ▲ ▼ output to the output terminal T2 becomes low level.

When the input signal Vin applied to the input terminal T1 is at low level, the transistor Q1 is cut off, and a high level potential appears at its drain terminal. Therefore, a high level signal is given to the gate terminal of the transistor Q3, the transistor Q3 becomes conductive, and the output signal {circle around (2)} output to the output terminal T2 becomes high level.

That is, in the BFL circuit 1, the transistors Q1 and Q2 form an inverter section, and the transistors Q3 and Q4 and the diodes D1, D2 and D3 form a buffer section formed of a source follower circuit.

Also, in the BFL circuit 1, the transistors Q1, Q2, Q3, Q4
Uses a depletion type FET, and is therefore easy to manufacture and has a characteristic of being resistant to variations in the characteristics of each transistor.

FIG. 6 is an electric circuit diagram of the NOR circuit 2 including the SBFL circuit. High-level or low-level input signals A and B are applied to the input terminals T3 and T4, respectively. The input signal A applied to the input terminal T3 is applied to the gate terminals of the transistors Q5 and Q6. The source terminal of the transistor Q5 is grounded, and its drain terminal is connected to the source terminal of the transistor Q7 and the gate terminal of the transistor Q8. The source terminal of the transistor Q6 is grounded and its drain terminal is connected to the output terminal T5.

The input signal B given to the input terminal T4 is the transistor Q
It is given to each gate terminal of 9, Q10. The source terminal of the transistor Q9 is grounded, and its drain terminal is connected to the source terminal of the transistor Q7 and the gate terminal of the transistor Q8. The source terminal of the transistor Q10 is grounded and its drain terminal is connected to the output terminal T5.

The transistor Q7 has its gate terminal and source terminal short-circuited, and its drain terminal is supplied with a positive voltage Vdd. Also, the transistor Q8 has a voltage Vd
d is provided and its source terminal is connected to the output terminal T5.

In the above NOR circuit 2, transistors Q5, Q6, Q9, Q10
Is an N-channel enhancement type FET, and the transistors Q7 and Q8 are N-channel depletion type FETs. The transistors Q5, Q7, Q9 form an inverter section, and the transistors Q6, Q8, Q10 form a buffer section.

When the input signal A supplied to the input terminal T3 is at high level, the transistors Q5 and Q6 are conductive, and when it is at low level, the transistors Q5 and Q6 are cut off. Similarly, input terminal T
When the input signal B applied to 4 is at high level / low level, the transistors Q9 and Q10 are turned on / off.

When at least one of the transistors Q5 and Q9 is conducting, the transistor Q8 is turned off by applying a low level signal to its gate terminal.
When both Q5 and Q9 are cut off, a high-level signal is applied to the gate terminal to make them conductive.

The output signal ▲ ▼ derived to the output terminal T5 becomes high level when the transistor Q8 is conducting. Further, when the transistor Q8 is cut off, at least one of the transistors Q5 and Q9 is conducting, and therefore at least one of the transistors Q6 and Q10 is conducting, so that the output signal output to the output terminal T5 is ▲
▼ is low level.

Thus, in the NOR circuit 2, the transistor Q
8 and the transistors Q6 and Q10 are pushed and pulled,
The load drive capacity is enhanced. In addition, DCFL (Direct Coupled
FET Logic) Low power consumption of circuit level is realized.

Problems to be Solved by the Invention In the BFL circuit 1 shown in FIG. 5, the power consumption of the buffer portion composed of the transistors Q3, Q4 and the like is large and is not suitable for high integration. Further, in the NOR circuit 2 configured by the SBFL circuit shown in FIG. 6, when a multi-input circuit is configured, the inverter unit and the buffer unit are added to increase the number of inputs (fan-in) by one. Each FET must be added one by one, which hinders high integration. Furthermore, since one input signal is given to the gate terminals of two FETs, the input capacitance is equivalent to the gate capacitance of two FETs, which increases the load in the case of a multi-input / output configuration. There is.

An object of the present invention is to provide a basic logic circuit which solves the above-mentioned problems, realizes high speed, high load driving capability, low power consumption, and is advantageous for high integration.

Means for Solving the Problems The present invention is directed to a plurality of field effect transistors Tr connected in series by connecting the source of a certain field effect transistor and the drain of another field effect transistor.
A field-effect transistor Tr13 on one side of the field-effect transistors connected in series in the input section, the input section consisting of 13, Tr14 is connected to the drain via the first load element Trl and is positive with respect to the common potential. To the source of the first bias voltage generating means Vdd for applying the voltage and the source of the field effect transistor Tr14 on the other side of the field effect transistors connected in series in the input section,
The second bias voltage generating means Vpd for giving a negative voltage to the common potential is connected via the load element Dpd, and the connection point between the first load element Trl and the drain of the field effect transistor Tr13 on the one side. Is connected to the gate of the first field effect transistor Tr2, and the gate of the second field effect transistor Tr3 is connected to the connection point between the second load element Dpd and the source of the field effect transistor Tr14 on the other side. The drain of the field effect transistor Tr2 is connected to the first bias voltage generating means Vdd, the source of the second field effect transistor Tr3 is connected to the common potential, and the source of the first field effect transistor Tr2 and the drain of the second field effect transistor Tr3. A diode D11 in the forward direction is connected between and, and an output is taken out between the drain of the second field effect transistor Tr3 and the diode D11. The plurality of field-effect transistors Tr13, Tr14, the first field-effect transistor Tr2 and the second field-effect transistor Tr3 connected in series in the input section are of the same conductivity type. It is a basic logic circuit.

Action According to the present invention, the gates of the field effect transistors Tr13 and Tr14 included in the input section are turned on / off by being supplied with the high level or low level input signal Vin, and accordingly, the field effect transistors Tr13 and Tr14 are turned on / off. Tr13, Tr1
First and second field-effect transistors Tr of the same conductivity type as that of 4, for example, N-channel as in the embodiment described later.
2, Tr3 performs push-pull operation, that is, when either one of the first and second field effect transistors Tr2, Tr3 becomes conductive, the other one cuts off.

Particularly according to the invention, the first load element Trl, the field effect transistors Tr13 and Tr14 in the input section, and the second load element Dpd are arranged in this order between the first and second bias voltage generating means Vdd and Vpd. The first and second bias voltage generating means Vdd and Vpd are connected to each other and generate positive and negative voltages with respect to the common potential. The amplitude of the signal applied to the gates of the field effect transistors Tr2 and Tr3 can be increased,
Wide operating margin.

Further, according to the invention, the signal from the source follower circuit constituted by the field effect transistor Tr14 on the other side of the plurality of field effect transistors Tr13 of the input section and the second load element Dpd serves as a buffer section. Second
It is given to the gate terminal of field effect capacitor Tr3. Therefore, the input capacitance of the basic logic circuit 11 of this case is the gate capacitance of one field effect transistor, and therefore the field effect transistors Tr13 and Tr14 connected in series at the input section.
It is possible to control the speed deterioration caused by increasing the number of FANs and increasing the fan-in, and thus the logical product NAND can be calculated.

Moreover, the number of field effect transistors to be added is one per fan-in, which is advantageous for high integration.

First Embodiment FIG. 1 is an electric circuit diagram of a basic logic circuit 11 which is a premise of the present invention. FET used in basic logic circuit 11
(Hereinafter, referred to as a transistor) is an N channel, that is, has the same conductivity type.

A high-level or low-level input signal Vin is applied to the input terminal T11. The input signal Vin is a transistor Tr
1 is given to the gate terminal. The drain terminal of the transistor Tr1 has a load element as a first bias voltage generating means.
Positive voltage Vd with respect to the ground potential, which is the common potential via L1
d is applied, and the drain terminal is connected to the gate terminal of the transistor Tr1 which is the first field effect transistor. A negative voltage Vpd with respect to the ground potential, which is a common potential, is applied to the source terminal of the transistor Tr1 via the load element L2 that is the second bias voltage generation means, and the source terminal is the second field effect transistor. Transistor Tr3
Connected to the gate terminal of. The input unit is configured to include the transistor Tr1.

The source terminal of the transistor Tr3 is grounded to a common potential, and its drain terminal is connected to the output terminal T12 while being connected to the source terminal of the transistor Tr2 via one or more diodes D11, D12, .... It The voltage Vdd is applied to the drain terminal of the transistor Tr2.

When the input signal Vin applied to the input terminal T11 is at low level, the transistor Tr1 is cut off and the transistor Tr1
The voltage Vdd (high level) appears at the drain terminal of the and the voltage Vpd (low level) appears at the source terminal. Therefore, the transistor Tr2 is turned on and the transistor Tr3 is turned off. At this time, the output signal ▲ ▼ whose level is adjusted by the diodes D11, D12, ... Is derived as a high level signal from the output terminal T12.

When the input signal Vin given to the input terminal T11 is at a high level, the transistor Tr1 becomes conductive, and a potential (low level) lower than the voltage Vdd by the voltage drop due to the load element L1 appears at the drain terminal of the transistor Tr1. At its source terminal, the voltage Vp corresponding to the voltage drop due to the load element L2
A potential (high level) higher than d appears. Therefore, the transistor Tr2 is turned off and the transistor Tr3 is turned on. At this time, the output signal ▲ ▼ output to the output terminal T12 becomes low level.

In the basic logic circuit 11, an inverter section is configured to include a load element L1, a transistor Tr1, and a load element L2,
A buffer unit is configured to include the transistors Tr2, Tr3, the diodes D11, D12 .... As described above, in the buffer section, the transistors Tr2 and Tr3 are operated in push-pull. This makes it possible to efficiently drive the load connected to the next stage.

Further, either one of the transistors Tr2 and Tr3 in the buffer section is cut off, so that the current in the buffer section is limited, the power consumption in the buffer section is suppressed, and the noise margin can be designed to be large. .

A signal from a source follower circuit composed of the transistor Tr1 and the load element L2 is given to the gate terminal of the transistor Tr3 of the buffer section, and therefore the input capacitance of the basic logic circuit 11 is the gate capacitance of one FET.
As a result, speed deterioration due to increase in fan-in is suppressed.

Further, when a NOR circuit, a NAND circuit, or the like is configured as described later, only one FET is added per fan-in, which is advantageous for high integration.

FIG. 2 shows an example of the load element L1, and FIG. 3 shows an example of the load element L2. That is, a resistance is used as the load element L1, a depletion type FET in which the gate terminal and the source terminal are short-circuited, and the like, and a resistance is used as the load element L2 and a FE in which the gate terminal and the source terminal are short-circuited.
T, diode, etc. are applied.

FIG. 4 is an electric circuit diagram of the NAND circuit 12 of one embodiment of the present invention to which the basic logic circuit 11 is applied. The NAND circuit 12 uses a transistor (FET) Trl having a gate terminal and a source terminal short-circuited as a load element L1 and a diode Dpd as a load element L2 to form a two-input NAND circuit. In FIG. 4, the basic logic circuit 11 shown in FIG.
The same reference numerals are attached to those having a function equivalent to. Transistors Tr13 and Tr14 corresponding to input terminals T13 and T14
Is provided. The drain terminal of the transistor Tr13 is the source terminal of the transistor Trl and the transistor Trl.
Connected to the gate terminal of r2. Also, the transistor Tr13
The source terminal of is connected to the drain terminal of transistor Tr14, and the source terminal of transistor Tr14 is a diode
Connected to Dpd and the gate terminal of transistor Tr3.
In the NAND circuit 12, transistors Tr connected in series
The input section is configured to include 13, Tr14.

Therefore, when the transistors Tr13 and Tr14 are simultaneously turned on, a low level potential appears at the drain terminal of the transistor Tr13 and a high level potential appears at the source terminal of the transistor Tr14. At this time, the transistor Tr2 is cut off, the transistor Tr3 is turned on, and the output signal output to the output terminal T15 is output. Becomes low level. That is, when the input signals A and B applied to the input terminal T13 and the input terminal T14 are both high level, the output signal derived to the output terminal T15 Will be low level.

When at least one of the transistors Tr13 and Tr14 is cut off, a high level potential appears at the drain terminal of the transistor Tr13 and a low level potential appears at the source terminal of the transistor Tr14. At this time, the transistor Tr2 becomes conductive,
Transistor Tr3 is cut off and output signal is output to output terminal T15 Becomes high level. That is, when at least one of the input signals A and B applied to the input terminals T13 and T14 is at a low level, the output signal derived to the output terminal T15 Becomes high level.

Connect the field effect transistors in series as above.
NAND circuit is obtained. At this time, one field effect transistor is added each time the number of fan-ins is increased, and high integration is easy.

In the basic logic circuit 11 shown in FIG.
Transistor Tr1 with gate width Wg = 10 (μm) and threshold voltage Vth = −0.2 (V)
With Wg = 10 (μm) and Vth = −0.5 (V) as transistor Tr3 Wg = 20 (μm) and Vth = −0.2
A FET (Wg = 10 (μm), Vth = −0.5) with a source terminal and a gate terminal short-circuited as a load element L1
(V)) as the load element L2 and the anode area is 10 (μm)
² ) 1 Schottky diode, diode D11, D1
As 2, 2, a circuit configuration was performed using one diode equivalent to the Schottky diode. The FE used
All Ts are N channels, and the channel layer is formed by Si ion implantation. The voltage Vdd is 2.0 (V),
The voltage Vpd is set to -0.5 (V), an odd number of basic logic circuits 11 are connected in a ring shape to form a ring oscillator, and the characteristics are examined. As a result, the propagation delay time per gate τpd = 50 (picoseconds). , Power consumption P = 850 (microwatt),
Τpd = 15 (picoseconds) per fan-out, τpd = 7 (picoseconds) per fan-in, and the noise margin was 0.35 (V). That is, the basic logic circuit 11 which has sufficiently high speed and has a large noise margin and low power consumption is realized.

Effects As described above, according to the present invention, a basic logic circuit that is high-speed, has high load driving capability, realizes low power consumption, and is advantageous for high integration can be realized.

Particularly according to the invention, a field effect transistor in the input section
The first and second bias voltage generating means Vdd and Vpd are connected to one side of Tr13 and Tr14 through the first load element Trl and to the other side through the second load element Dpd, respectively. The two bias voltage generating means Vdd, Vpd are the first and second field effect transistors Tr2, Tr that perform push-pull operation.
Since the positive and negative voltages are generated with respect to the common potential to which 3 is connected, it is possible to increase the amplitude of the signal given to each gate of the first and second field effect transistors Tr2, Tr3. Therefore, it is possible to achieve the effect that the load driving capability is high and the operation margin is widened.

Further, according to the present invention, among the plurality of field effect transistors forming the input section, the signal from the source follower circuit formed by the field effect transistor Tr14 on the other side and the second load element Dpd serves as the buffer section. It is given to the gate of the working second field effect transistor Tr3, and therefore the input capacitance of the basic logic circuit of the present invention is the gate capacitance of one field effect transistor. As a result, it is possible to suppress speed deterioration due to an increase in fan-in.

Further, according to the present invention, when a logical product NAND is formed, the number of field effect transistors added in the input section is one per fan-in, and therefore, there is an excellent effect that it is advantageous for high integration.

Further, the first and second field effect transistors Tr2, Tr3
The diode D11 in the forward direction is interposed between the two to adjust the voltage level. Therefore, the first and second field effect transistors Tr2 and Tr3 having various characteristics can be used.

[Brief description of drawings]

1 is an electric circuit diagram of a basic logic circuit 11 which is a premise of the present invention, FIG. 2 is a diagram showing an example of a load element L1, FIG. 3 is a diagram showing an example of a load element L2, and FIG. 4 is a basic diagram. An electrical circuit diagram of a NAND circuit 12 according to an embodiment of the present invention constructed by applying the logic circuit 11 is shown in FIG. 5, which is a typical prior art basic logic circuit.
FIG. 6 is an electric circuit diagram of the BFL circuit 1, and FIG. 6 is an electric circuit diagram of the NOR circuit 2 constructed by applying the SBFL circuit which is a typical conventional basic logic circuit. 11 …… Basic logic circuit, 12 …… NAND circuit, 13 …… NOR circuit, Tr1, Tr2, Tr3, Tr13, Tr14, Trl …… Transistor (FE
T), L1, L2 ... load element, Dpd ... diode

Claims (1)

(57) [Claims] 1. A plurality of field effect transistors Tr, which are connected in series by connecting a source of a field effect transistor and a drain of another field effect transistor.
Including an input section consisting of 13, Tr14, the drain of the field effect transistor Tr13 on one side of the field effect transistors connected in series of the input section,
A first bias voltage generating means Vdd for giving a positive voltage to the common potential via the first load element Trl, and a field effect transistor Tr14 on the other side of the field effect transistors connected in series in the input section. Is connected to the source of each of them via the second load element Dpd and the second bias voltage generating means Vpd for giving a negative voltage to the common potential, and the first load element Trl and the field effect transistor T on the one side are connected.
The gate of the first field effect transistor Tr2 is connected to the connection point with the drain of r13, and the second load element Dpd and the field effect transistor T on the other side are connected.
At the connection point with the source of r14, the second field effect transistor T
The gate of r3 is connected, the drain of the first field effect transistor Tr2 is connected to the first bias voltage generating means Vdd, the source of the second field effect transistor Tr3 is connected to a common potential, and the first field effect transistor Tr2 source is connected. A diode D11 in the forward direction is connected between the drain of the second field effect transistor Tr3 and the drain of the second field effect transistor Tr3 so that an output is taken out between the drain of the second field effect transistor Tr3 and the diode D11. A plurality of field-effect transistors Tr13, Tr14, a first field-effect transistor Tr2 and a second field-effect transistor Tr3 connected in series are of the same conductivity type.