JP2535734B2 - Conductive thin film deposition method - Google Patents

Conductive thin film deposition method

Info

Publication number
JP2535734B2
JP2535734B2 JP60144566A JP14456685A JP2535734B2 JP 2535734 B2 JP2535734 B2 JP 2535734B2 JP 60144566 A JP60144566 A JP 60144566A JP 14456685 A JP14456685 A JP 14456685A JP 2535734 B2 JP2535734 B2 JP 2535734B2
Authority
JP
Japan
Prior art keywords
molecules
atoms
deposited
film
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60144566A
Other languages
Japanese (ja)
Other versions
JPS627140A (en
Inventor
秀和 岡林
徹 最上
英二 長澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
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Filing date
Publication date
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Priority to JP60144566A priority Critical patent/JP2535734B2/en
Publication of JPS627140A publication Critical patent/JPS627140A/en
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Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、基板の微細な凹部に導電薄膜を埋め込んで
堆積する方法に関する。
Description: TECHNICAL FIELD The present invention relates to a method of burying and depositing a conductive thin film in fine recesses of a substrate.

(従来の技術) 基板の微細な孔な溝の内部に導電薄膜を埋め込んで堆
積することは、集積回路装置の多層配線等への応用上重
要である。基板または基板ホルダーに電圧を印加しなが
らスパッタを行うバイアススパッタを用いると、集積回
路装置の配線におけるコンタクト孔やスルーホールに導
電薄膜を埋め込んで堆積できることが知られている(最
上(T.Mogami)ほか、固体素子・材料コンファレンス
(Extended Abstracts of the 16th(1984 Internation
al)Conference on Soild State Devices and Material
s),Kobe,1984,43〜46頁)。
(Prior Art) Embedding and depositing a conductive thin film inside a fine hole groove of a substrate is important for application to a multilayer wiring of an integrated circuit device. It is known that by using bias sputtering, which performs sputtering while applying voltage to the substrate or substrate holder, conductive thin films can be embedded and deposited in contact holes and through holes in the wiring of integrated circuit devices (Most (T.Mogami) In addition, solid-state devices and materials conference (Extended Abstracts of the 16th (1984 Internation
al) Conference on Soild State Devices and Material
s), Kobe, 1984, pp. 43-46).

(発明が解決しようとする問題点) しかし本発明者は、さらに詳細な検討を行うことによ
り、微細な孔や溝のアスペクト比(深さと直径または平
面寸法との比)が0.8程度以上になると微細な孔や溝は
完全には埋め込まれず、第2図(b)に示した様に堆積
膜12中に空洞16が残ることが明らかになった。従来用い
られているバイアススパッタリングにおいては、ターゲ
ットからスパッタされた原子や分子の堆積と、スパッタ
ガスイオンが基板バイアスによって加速されて基板表面
に入射することによって生じるスパッタエッチングとが
基板表面で同時に起こっている。スパッタガスイオン
は、基板表面のバイアス電界によって加速され基板表面
にほぼ垂直に入射するが、ターゲットからスパッタされ
た原子や分子の基板表面への入射には種々の方向の成分
があり、斜めから入射する成分も大きい。従って高いア
スペクト比の微細な孔や溝にバイアススパッタリングに
よって膜堆積を行うと、第2図(a)に示した様に、膜
堆積の進行とともに、微細孔入口部(肩部)に斜め入射
成分によって14に示す横方向への“張り出し”が成長
し、微細孔内に入射する堆積原子や分子がこの“張り出
し”で捕えられる割合が増加するため微細孔内への入射
原子や分子の割合が減少する。すると、“張り出し”は
益々成長し、微細孔内への入射の割合は益々減少すると
いう悪循環となり、結局微細孔入口が塞がれ、第2図
(b)の様に堆積膜中に空洞が残るものと考えられる。
(Problems to be Solved by the Invention) However, the present inventor has conducted a more detailed study and found that when the aspect ratio (ratio of depth to diameter or plane dimension) of fine holes or grooves becomes about 0.8 or more. It was clarified that the fine holes and grooves were not completely filled, and the cavities 16 remained in the deposited film 12 as shown in FIG. 2 (b). In conventional bias sputtering, the deposition of atoms and molecules sputtered from the target and sputter etching that occurs when sputter gas ions are accelerated by the substrate bias and enter the substrate surface occur simultaneously. There is. Sputtering gas ions are accelerated by the bias electric field on the substrate surface and are incident almost vertically on the substrate surface, but the atoms and molecules sputtered from the target are incident on the substrate surface in various directions, and are incident at an angle. It also has a large ingredient. Therefore, when a film is deposited on a fine hole or groove having a high aspect ratio by bias sputtering, as shown in FIG. 2 (a), as the film deposition progresses, an oblique incident component on the entrance (shoulder) of the fine hole is obtained. As a result, the lateral "overhang" shown in Fig. 14 grows, and the proportion of the deposited atoms and molecules incident in the micropores is increased by this "overhang". Decrease. Then, the "overhang" grows more and more, and the rate of incidence into the micropores further decreases, resulting in a vicious circle, which eventually blocks the micropore inlets and creates cavities in the deposited film as shown in Fig. 2 (b). It is thought to remain.

また、バイアススパッタによって微細孔内に埋め込み
堆積を行う様な高いバイアス電圧を印加して導電膜を堆
積した場合には、放電ガスであるアルゴン等の不活性ガ
スイオンが堆積膜中に取り込まれ、堆積した導電膜の抵
抗が著しく増加することをも見出した。この様な空洞の
発生や不純物の混入は、堆積した膜を集積回路装置の配
線等への応用において、歩留りの低下、信頼性の低下や
回路の電気特性(動作速度等)の低下を引越すので好ま
しくない。
In addition, when a conductive film is deposited by applying a high bias voltage such that it is embedded in fine holes by bias sputtering, an inert gas ion such as argon, which is a discharge gas, is taken into the deposited film, It has also been found that the resistance of the deposited conductive film increases significantly. The generation of such cavities and the mixing of impurities cause a decrease in yield, a decrease in reliability, and a decrease in electrical characteristics (operating speed, etc.) of the circuit when the deposited film is applied to wiring of an integrated circuit device. Not preferable.

本発明は、この様な従来法の問題点を解決した新規な
微細な凹部への導電膜の堆積方法を提供する。
The present invention provides a novel method for depositing a conductive film on a minute recess, which solves the problems of the conventional method.

(問題点を解決するための手段) 本発明は、溶融した導電材料より蒸発した原子や分子
の一部をイオン化して加速し、該イオン化した原子や分
子もイオン化していない原子や分子もともに表面に微細
でアスペクト比の充分大きい凹部を有する基板にほぼ垂
直方向から入射せしめ、かつ、イオン化した原子や分子
の堆積膜への衝撃による凹部肩部での堆積膜の横方向ス
パッタエッチング速度が凹部肩の部分での堆積膜の横方
向成長速度よりも大となる様にイオン化率やイオンの加
速エネルギーを選ぶことを特徴とした導電薄膜の堆積方
法である。
(Means for Solving Problems) The present invention is to ionize and accelerate a part of atoms and molecules evaporated from a molten conductive material, and to accelerate both the ionized atoms and molecules and non-ionized atoms and molecules. It is incident on a substrate having a minute concave portion with a sufficiently large aspect ratio on the surface from almost vertical direction, and the lateral sputter etching rate of the deposited film at the shoulder portion of the concave portion due to the impact of ionized atoms and molecules on the deposited film This is a method for depositing a conductive thin film, which is characterized in that the ionization rate and the acceleration energy of ions are selected so as to be higher than the lateral growth rate of the deposited film at the shoulder portion.

(作用) 本発明の方法では、原子や分子は基板表面にほぼ垂直
な方向から入射するので、微細孔入口での横方向への
“張り出し”の成長速度は小さく、かつ、微細孔内への
入射の割合も大きい。従って、原子や分子のイオン化率
や加速エネルギーを材料等によって決まるある値以上に
することによりイオン化した原子や分子の衝撃により微
細孔入口での横方向成長を抑制し、微細孔内に“す”が
生じるのを防止することができる。具体的には、イオン
化粒子による堆積膜のスパッタ率の逆数程度以上のイオ
ン化粒子の全入射粒子に対する割合、あるいは、イオン
化粒子によるスパッタ率がイオン化粒子の全入射粒子に
対する割合程度以上となるイオン化粒子の加速エネルギ
ー、を用いることにより、孔の入口肩部での孔の中心方
向への横方向成長速度をほぼゼロあるいは負の値にする
ことができる。必要なイオン化粒子の割合やイオン化粒
子の加速エネルギーを決定するためのスパッタ率は、イ
オンの種類や堆積膜の材料によって異なるが、スパッタ
率の加速エネルギー依存性の報告値(例えば、R.Behris
ch編1981年Springer−Verlag社発行の「Sputtering by
Particle Bombardment I」と題する本に多くの結果がま
とめられている)を参考にして、あるいは、実験によっ
て求めたスパッタ率の加速エネルギー依存性を用いて決
定することができる。従って、微細孔肩部では、第1図
に示した様に入口が広がる方向にテーパーを付けること
ができるので、微細孔内に薄膜を埋め込んで堆積するこ
とができる。さらに、本発明による方法では、導電材料
は10-3Pa程度の高真空中で蒸発させることができ、か
つ、微細孔入口での横方向成長を抑制するためのイオン
衝撃も堆積すべき導電材料の原子や分子のイオンを用い
て行われるので、堆積した膜中への不純物の混入が極め
て少なく、バイアススパッタの際に問題となる不純物の
混入による導電薄膜の電気抵抗の増加も生じない。
(Operation) In the method of the present invention, since atoms and molecules are incident from a direction substantially perpendicular to the substrate surface, the growth rate of the lateral “overhang” at the entrance of the micropores is small, and at the entrance of the micropores, The incidence rate is also high. Therefore, by setting the ionization rate and acceleration energy of atoms and molecules above a certain value determined by the material, etc., lateral growth at the micropore entrance is suppressed by the impact of ionized atoms and molecules, and " Can be prevented. Specifically, the ratio of ionized particles to the total number of incident particles that is greater than or equal to the reciprocal of the sputter rate of the deposited film due to ionized particles, or the ratio of ionized particles whose sputter rate due to ionized particles is greater than or equal to the ratio of the ionized particles to all incident particles. By using the acceleration energy, the lateral growth rate toward the center of the hole at the entrance shoulder of the hole can be made almost zero or a negative value. The sputter rate for determining the required ratio of ionized particles and the acceleration energy of ionized particles depends on the type of ion and the material of the deposited film, but the reported value of the acceleration energy dependence of the sputter rate (for example, R. Behris
ch edition 1981 Springer-Verlag issue "Sputtering by
Many results are summarized in a book entitled "Particle Bombardment I") or by using the acceleration energy dependence of the sputter rate obtained by experiments. Therefore, at the shoulders of the fine holes, as shown in FIG. 1, it is possible to form a taper in the direction in which the inlet is widened, so that a thin film can be embedded and deposited in the fine holes. Further, in the method according to the present invention, the conductive material can be evaporated in a high vacuum of about 10 −3 Pa, and the ion bombardment for suppressing the lateral growth at the entrance of the micropores should also be deposited. Since the impurities are mixed into the deposited film very little, the electric resistance of the conductive thin film does not increase due to the problem of mixing impurities when bias sputtering is performed.

(実施例) 本発明の実施例においては、第4図に模式図を示した
様なアーク放電型イオン化蒸着装置を用いて行った。導
電材料(蒸着材料40)としてモリブデン(Mo)を用い、
真空槽45中で電子銃42によって加熱溶融し蒸発させる。
電子銃の近傍に配置されたアーク電極44にアーク電源46
より数十Vの電圧を印加しアーク電極44近辺でアーク放
電を発生し、蒸発したモリブデン蒸気の一部をイオン化
する。モリブデン原子48やイオン50は基板52に入射する
が、その際モリブデンイオン50は基板ホルダー54に加速
電源56によって印加された加速電圧によって加速されて
基板52を衝撃する。第1図に加速電圧−1.6kV,基板での
イオン電流密度6mA/cm2,膜堆積速度15Å/秒(基板へ入
射するモリブデン原子のイオン化率約40%)の条件で幅
1.5μm,深さ1.2μmの溝部にモリブデンを堆積した試料
の断面形状の概略を示す。第3図に示した加速電圧を印
加しない場合や第2図(b)に示した従来のバイアスス
パッタの場合に比して、モリブテンが溝の中に一様に堆
積されていることが分る。第1図に示した様な形状は、
加速電圧−0.5kV,−1kV,−3kVでも実現できた。既に述
べた様に、この様な形状が得られるのは、段差肩部での
堆積膜12の横方向成長がイオン衝撃によって抑えられる
からである。イオン衝撃によるエッチングはイオンの加
速電圧とイオン電流密度に依存することが良く知られて
いるので、イオン化率を上げる等の方法でイオン電流密
度を増加することにより、加速電圧が−0.5kVより低い
負バイアスでも第1図に示した様な断面形状を得ること
が可能である。また、本実施例によって堆積したモリブ
デン薄膜の電気抵抗は、8μΩ・cmと従来の高いバイア
スでスパッタした場合の約1/2に減少した。
(Example) In an example of the present invention, an arc discharge type ionization vapor deposition apparatus having a schematic view shown in Fig. 4 was used. Using molybdenum (Mo) as the conductive material (vapor deposition material 40),
It is heated and melted in the vacuum chamber 45 by the electron gun 42 to be evaporated.
Arc power supply 46 to arc electrode 44 located near the electron gun
By applying a voltage of several tens of V, arc discharge is generated in the vicinity of the arc electrode 44, and a part of the evaporated molybdenum vapor is ionized. The molybdenum atoms 48 and the ions 50 are incident on the substrate 52. At that time, the molybdenum ions 50 are accelerated by the acceleration voltage applied to the substrate holder 54 by the acceleration power source 56 and bombard the substrate 52. Fig. 1 shows the width under the conditions of an accelerating voltage of −1.6 kV, an ion current density on the substrate of 6 mA / cm 2 , and a film deposition rate of 15 Å / sec (the ionization rate of molybdenum atoms incident on the substrate is about 40%).
An outline of the cross-sectional shape of a sample in which molybdenum is deposited in a groove portion having a depth of 1.5 μm and a depth of 1.2 μm is shown. It can be seen that the molybdenum is uniformly deposited in the groove as compared with the case where the accelerating voltage shown in FIG. 3 is not applied and the case of the conventional bias sputtering shown in FIG. 2 (b). . The shape shown in Fig. 1 is
It was also possible to achieve acceleration voltages of −0.5 kV, −1 kV, and −3 kV. As described above, the reason why such a shape is obtained is that the lateral growth of the deposited film 12 at the step shoulder is suppressed by the ion bombardment. It is well known that etching by ion bombardment depends on the acceleration voltage and ion current density of ions, so by increasing the ion current density by methods such as increasing the ionization rate, the acceleration voltage is lower than -0.5 kV. Even with a negative bias, it is possible to obtain the cross-sectional shape as shown in FIG. Further, the electric resistance of the molybdenum thin film deposited according to this example was 8 μΩ · cm, which was about half that of the conventional sputtering with a high bias.

上記実施例においては、金属材料としてモリブデンに
ついて述べたが、タングステンやアルミニウムについて
も同様に有効であった。
In the above embodiments, molybdenum was used as the metal material, but tungsten and aluminum were also effective.

(発明の効果) 本発明の方法を用いることにより、基板表面のアスペ
クト比の高い微細な凹部に金属を埋め込んで堆積するこ
とが可能となる。
(Effects of the Invention) By using the method of the present invention, it becomes possible to bury and deposit metal in fine recesses having a high aspect ratio on the surface of a substrate.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の方法によって基板表面の微細な溝に金
属薄膜を堆積した試料の断面模式図。第2図(a),
(b)は、従来のバイアススパッタ法で堆積した場合の
断面模式図、第3図は、イオン化蒸着で加速電圧をゼロ
Vで行った場合の試料断面模式図。第4図は本発明の方
法の実施例で用いたアーク放電型イオン化蒸着装置の模
式図。 図中の番号は以下のものを示す。 10……基板、12……堆積膜 42……電子銃、44……アーク電極 56……加速電源
FIG. 1 is a schematic sectional view of a sample in which a metal thin film is deposited in fine grooves on the surface of a substrate by the method of the present invention. Figure 2 (a),
(B) is a schematic cross-sectional view of the sample deposited by the conventional bias sputtering method, and FIG. 3 is a schematic cross-sectional view of the sample when the accelerating voltage is zero V in the ionization deposition. FIG. 4 is a schematic diagram of an arc discharge type ionization vapor deposition apparatus used in an example of the method of the present invention. The numbers in the figure indicate the following. 10 …… Substrate, 12 …… Deposited film 42 …… Electron gun, 44 …… Arc electrode 56 …… Acceleration power supply

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭60−193336(JP,A) 特開 昭50−63883(JP,A) 特開 昭51−31187(JP,A) 特開 昭52−103978(JP,A) ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-60-193336 (JP, A) JP-A-50-63883 (JP, A) JP-A-51-31187 (JP, A) JP-A-52-1 103978 (JP, A)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】溶融した導電材料より蒸発した原子や分子
の一部をイオン化して加速し、該イオン化した原子や分
子もイオン化していない原子や分子もともに表面に微細
でアスペクト比の充分大きい凹部を有する基板にほぼ垂
直方向から入射せしめ、かつ、イオン化した原子や分子
の堆積膜への衝撃による凹部肩部での堆積膜の横方向ス
パッタエッチング速度が凹部肩の部分での堆積膜の横方
向成長速度よりも大となる様にイオン化率やイオンの加
速エネルギーを選ぶことを特徴とした導電薄膜の堆積方
法。
1. A part of atoms or molecules evaporated from a molten conductive material is ionized and accelerated, and both the ionized atoms and molecules and the non-ionized atoms and molecules are fine on the surface and have a sufficiently large aspect ratio. The film is made to enter the substrate having the concave portion from a substantially vertical direction, and the lateral sputter etching rate of the deposited film at the shoulder portion of the concave portion due to the impact of ionized atoms and molecules on the deposited film is the lateral direction of the deposited film at the shoulder portion of the concave portion. A method for depositing a conductive thin film, characterized in that the ionization rate and ion acceleration energy are selected so as to be higher than the directional growth rate.
JP60144566A 1985-07-03 1985-07-03 Conductive thin film deposition method Expired - Lifetime JP2535734B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60144566A JP2535734B2 (en) 1985-07-03 1985-07-03 Conductive thin film deposition method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60144566A JP2535734B2 (en) 1985-07-03 1985-07-03 Conductive thin film deposition method

Publications (2)

Publication Number Publication Date
JPS627140A JPS627140A (en) 1987-01-14
JP2535734B2 true JP2535734B2 (en) 1996-09-18

Family

ID=15365208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60144566A Expired - Lifetime JP2535734B2 (en) 1985-07-03 1985-07-03 Conductive thin film deposition method

Country Status (1)

Country Link
JP (1) JP2535734B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5063883A (en) * 1973-10-08 1975-05-30
JPS583376B2 (en) * 1974-09-11 1983-01-21 株式会社日立製作所 Hand-made Thai Soshinoseizouhou
JPS52103978A (en) * 1976-02-25 1977-08-31 Sharp Corp Manufacture of conduction body in semiconductor device

Also Published As

Publication number Publication date
JPS627140A (en) 1987-01-14

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EXPY Cancellation because of completion of term