JP2535144B2 - Parallel processing computer - Google Patents

Description

The present invention relates to a parallel processing computer such as a data flow computer, and more particularly to exception processing in the parallel processing computer.

[Conventional technology]

(Neumann type computer) At present, as researches on a large amount of data analysis and intelligent processing progress, demands for realizing a computer capable of parallel processing are increasing. A parallel processing computer is fundamentally different from a conventional Neumann computer dedicated to sequential processing. That is, the Neumann computer is characterized in that the existence of the program counter and the data variable are expressed by replacing them with the memory address. The existence of the program counter and the memory address is fundamentally parallel processing. Since they are incompatible with each other, many concepts used in the Neumann computer are often inconvenient if they are directly applied to the parallel processing computer. A typical example of such inconvenience is a problem that occurs during exception processing (interrupt processing). Therefore, how these problems are conventionally perceived and dealt with will be described.

(Problem of exception processing) Exception processing in a Neumann type computer changes the contents of the program counter to that for exception processing by the exception processing request signal that causes the exception event, interrupts the program currently being executed, It is realized by preferentially executing a predetermined exception handling program. In addition, the program interrupted by the exception process execution is
It returns by executing the exception processing end instruction and returning to the program counter value at the time of interruption.

As described above, in the Neumann type computer, the exception processing is realized by changing and restoring the contents of the program counter, and is preferentially processed over the normal program currently being executed.

However, since the parallel processing computer does not have a program counter, exception processing cannot be performed by the method of the Neumann computer.

[Problems to be solved by the invention]

An object of the present invention is to propose a parallel processing computer capable of exception processing in a parallel processing computer which has not conventionally been considered for exception processing.

[Means for Solving Problems and Their Actions]

In order to achieve the above object, the present invention provides an arbiter that gives an exception handling request signal generated from an exception handling request signal generation circuit to one of a plurality of functional units (hereinafter referred to as FUs), and a token that controls a normal program. An exception complete token packet is created in the normal token memory that stores the exception token, the exception token memory that stores the token that controls the exception handling program generated by the FU to which the exception handling request signal is given, and the exception token memory. At this time, the complete token packet input part of each FU is switched from the normal token memory to the exception token memory, and the exception processing request signal is directly given to the FU configured by the switching circuit to separate the exception token memory and the normal token memory. It is a parallel processing computer characterized by the above, and another invention is an exception processing request signal generation. An arbiter that gives the exception processing request signal generated from the circuit to one of a plurality of FUs, a priority token generated by the FU that receives the exception processing request signal, a means for generating the token, and a complete token in the token memory. When a packet is created, a FU that is composed of a token packet allocation circuit that gives a complete token packet to a FU that is ready to accept a complete token packet according to the priority of the token
Is a parallel processing computer characterized by directly giving an exception processing request signal to a token, and the token receives the processing priority, and another invention is an exception processing request signal generated from an exception processing request signal generation circuit. The exception token generation circuit that activates the exception handling program, the exception token memory that stores this exception token, the normal token memory that stores the normal token that controls the normal program, and the exception complete token in the exception token memory. When a packet exists, the FU input section is switched from the normal token memory to the exception token memory, and a circuit that generates a token for the exception token memory and is composed of a switching circuit is separated from the exception token memory and the normal token memory. It is a parallel processing computer characterized by Is a token generation circuit with a priority that starts an exception processing program by the exception processing request signal generated from the exception processing request signal generation circuit, and when a complete token packet is created in the token memory, according to the order of the priority of the token, Complete token packet A token with priority assigned for exception processing, which consists of a token packet allocation circuit that gives a complete token packet to a FU that is ready to accept, and multiple FUs that execute programs by this token packet. It is a parallel processing computer characterized in that the processing priority is determined by.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to a data flow computer which is an example of a parallel processing computer will be described in more detail with reference to the accompanying drawings.

(Data Flow Computer) FIG. 5 shows the structure of a data flow computer to which the present invention is applied. A data flow computer is a type of non-Neumann computer that starts execution from an instruction that has all the data to be processed.It does not depend on the program counter as in a Neumann computer. Instead, the origin of the name is based on the data flow.

TM51 in FIG. 5 is a memory called a talk memory,
Stores data called tokens. FU1, FU2, and FUn are the data processing devices called functional units, which input the complete token packet given by TM51, process the data in the token packet, and output the resulting token packet.

[Complete token packet] = <node name><dataA>
<Data B> ... The above example shows the form of a complete token packet (CTP). The CTP is composed of data A, data B, and a node name indicating the method of processing these data.

[Result token packet A] = <node name><dataA><empty> ... [Result token packet B] = <node name><empty>
<Data B> ... is the result token packet A, B (hereinafter RTPA or RTP
It shows an example of the shape of B). RTPA is the node name,
It consists of data A, and the part corresponding to data B of CTP is missing. On the other hand, RTPB has a form in which data A of CTP is missing.

Now, as shown in FIG. 6 (a), the result token 7
The operation will be described by taking as an example a case where 1a and 72a are included and the result tokens 73a and 74a are about to be output from FU1 and FU2.

Result token 73a about to be output from FU1,75a
Has a node name of <PLUS>, which is equal to the node name of the result token 71a in the first stage of TM70, so it is placed in this stage.

Also, the result token 74a that is about to be output from FU2
Has a node name of <MUL> and the node name is the same as the result token 72a in the second row of TM70a, so it is placed in this row.

Then, a complete token packet a71b and a complete token packet b72b are formed in the first and second stages of the TM 70b as shown in FIG. 6 (b).

At this time, TM70b is connected to FU1 (73b), CTPa71b to FU2 (74b).
Assign CTPb (72b) to b). (Possible to reverse) Here, the node name <PLUS> in CTPa is “a node for adding data A and data B and outputting the operation result as data A to the node <MINS>”. FU1 means data A and data B
Addition is performed and <MINS><+ 1 as shown in Fig. 6 (c).
1> Write the result token 71c <empty> to TM70c. (At this time, the stage to be written may be any space as long as it is empty.) Similarly, the node name <MIL> in CTPb (72b) in FIG. 6 (b) is “multiply data A and B and call it <MINS>”. "Min"><empty><+10> as shown in Fig. 6 (c).
Is output to the TM 70c.

Here, the result tokens 71c and FU2 output by FU1 (74c)
As the result token (72c) output from token (75c) has the same node name, it is put in the same row and complete token packet 73c.
Then, execute either FU again.

Here, the details of the token memory are omitted because the inventors of the present invention have already clarified the details. (Reference, Sowa et al., “A bata flow computer arc
hitecture with program and token memories "IEEE Tra
nsactions on computers, Vol.C31 No9 September 198
2) [Embodiment of the present invention] In the present invention, a configuration method for realizing exception handling is
Propose and explain as follows. All exception handling requests that occur in the description are when a normal program is running.

(1) “Parallel processing computer characterized by directly giving an exception processing signal to FU and distinguishing between normal token memory and exception token memory.” FIG. 1 realizes the method (1). It is an example for this.

Now, if an exception processing request is entered in the exception processing request signal generation circuit 10, an exception processing request signal 11 is generated. This signal is input to the arbiter 12 and assigned to any of FU1, 13 to FUn15 that can receive this signal.

The FU, to which the request signal is assigned by the arbiter 12, switches the switching circuit 16 that is normally switched to NTM (normal token memory) to ETM18 (exception token memory), sets the exception token, and switches the switching circuit 16. Return to the original NTM17 side.

If the exception handling complete token packet is configured in the ETM 18, the ETM 18 switches the switching circuit 16 to the ETM side, and if there is an acceptable FU, allocates the complete token packet to the FU and activates it. Further, the FU activated by the complete exception token packet of the ETM 18 outputs the switching circuit 16 to the ETM side 18 as the exception result token unless the node of the token packet is the exception processing end node. This allows the exception perfect token packet to be assigned to the FU in preference to the normal perfect token packet.

(2) “Parallel processing computer characterized by directly giving an exception processing signal to FU and giving priority to tokens.” FIG. 2 is an embodiment for realizing the method (2). .

Now, assuming that an exception processing request is input to the exception processing request signal generation circuit 20, an exception processing request signal 21 is generated. This signal is input to the arbiter 22 and FU1 (2
Assigned to any of 3) to FUn (25).

The FU supplied with the exception processing request signal 21 generates a token having a higher priority than that for controlling a normal program to the token memory TM27. In the token memory TM27, when the node name and the priority are the same, it is determined that they are the same token packet.

If multiple complete token packets with different priorities are simultaneously generated in TM, TM27 allocates to FUs in a state in which the priority can be executed by the priority detection circuit 28 in TM27 in the order of higher priority. A high-priority complete token packet causes the FU to output a token that retains its priority unless the node returns the priority to the normal level. By this mechanism, exception handling is executed with priority over a normal program.

(3) "A parallel processing computer characterized by directly giving an exception processing result token to an exception token memory and distinguishing an exception token memory from a normal token memory." FIG. 3 shows the method (3). It is an example for realizing.

Now, if there is an exception processing request to the exception processing token generation circuit 30, an exception processing result token 37 is generated and the ETM
It is output to (exception token memory) 31. Switching circuit
33 is normally switched to NTM32 (normal token memory), but even if the complete token packet is configured in NTM32, if the exception handling complete token packet is configured in ETM31, it is switched to the ETM31 side. The FU activated by the exception processing complete token packet of the ETM31 switches the switching circuit 33 to the ETM31 side and outputs the result token as the exception processing result token unless the node of the token packet is the exception processing end node.

By this mechanism, exception handling is executed with priority over a normal program.

(4) "A parallel processing computer characterized by giving a token with a high priority directly to a token memory in response to an exception processing request." FIG. 4 is an embodiment for realizing the method (4). .

Now, the exception processing request is the exception processing result token generation circuit 40.
Upon entering, an exception processing result token 41 is generated. Tokens are given priority, and especially exception handling result tokens are given higher priority than normal result tokens.

The exception processing result token 41 output from the exception processing result token generation circuit 40 is the same as the normal result token TM
Stored in 42.

The TM42 treats those having the same priority as the node name as the same token packet, and operates to form a complete token packet.

If the TM has a plurality of complete token packets having different priorities, the TM 42 uses the priority detection circuit 43 in the TM 42 to assign to the FUs in a state in which the program can be executed in descending order of priority.

The high-priority complete token packet causes the FU to output the token as a result of maintaining the priority unless the node returns the priority to the normal level.

By this mechanism, exception handling is executed with priority over a normal program.

〔The invention's effect〕

The configurations shown in FIGS. 1 and 2, namely, "a parallel processing computer characterized by directly giving an exception processing signal to FU and distinguishing a normal token memory from an exception token memory" and "FU On the other hand, the configuration of the parallel processing computer, which is characterized by directly giving an exception processing signal and giving priority to tokens, is used for exception processing such as system reset, when the memory range is exceeded or when the memory is divided by zero. It is suitable. Further, the configuration shown in FIG. 3 and FIG. 4, that is, "a method of directly giving an exception processing result token to an exception token memory and a parallel processing characterized by distinguishing between an exception token memory and a normal token memory" The configuration of "Computer" and "Parallel processing computer characterized by giving tokens with high priority directly to token memory by exception processing request" is suitable for exception processing from peripheral I / O devices such as disks. .

As described above, any of the configurations of the present invention can perform exception processing in a parallel processing computer.

Moreover, the present invention does not hinder the parallel processing, which is a feature of the parallel processing computer, and the exception processing can be performed in parallel.

[Brief description of drawings]

FIG. 1 is a block diagram according to an embodiment of the configuration (1) of the present invention, FIG. 2 is a block diagram according to an embodiment of the configuration (2) of the present invention, and FIG. 3 is a configuration (3) of the present invention. FIG. 4 is a block diagram according to an embodiment of the configuration (4) of the present invention, FIG. 5 is a block diagram of a data flow computer that is a basic example of the present invention, and FIG. )-(C) is a figure explaining operation | movement of a data flow computer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-175822 (JP, A) Hiraki, Shimada “Interrupt processing in the data driven computer Sigma-1 for scientific and technological computation, 27th IPSJ National Convention Lecture Collection Vol. 1 (1983-10-18-20) PP. 79-80 Sowa, Hayashi "Fundamental Study of Interrupt Handling in Parallel Operating System (SSS)" IEICE Technical Report Vol. 85 No. 184 (EC85-45) (1985-10-25) PP. 53-60 Sowa, Hayashi "Fundamental Study of Interrupt Processing in Parallel Operating System (SSS)" Information Processing Society of Japan Research Report Vol. 85 No. 43 (CA59-15, OS29-15) (1985-10-24) PP. 133-140

Claims (4)

(57) [Claims] 1. A plurality of functional units for inputting a complete token packet, processing data in the token packet, and outputting a result token, and an exception processing for giving an exception processing request signal to one of the functional units. A request signal generation circuit, a normal token memory that stores a token that controls a normal program, and an exception token that stores a token that controls an exception processing program generated by a functional unit given the exception processing request signal. The exception token memory, and a switching circuit for switching the connection of the complete token packet input portion of each functional unit from the normal token memory to the exception token memory when an exception complete token packet is generated in the exception token memory. Received a processing request signal By serial functional unit outputs an exception token to the exception token memory, a parallel processing computer and performs exception handling. 2. A plurality of functional units for inputting a complete token packet having a priority, processing data in the token packet, and outputting a result token having a priority, and an exception processing request signal of the functional unit. When an exception processing request signal generating circuit given to one, a memory means for storing a token having the priority and a complete token packet are formed therein, a complete token packet can be accepted according to a high priority order of the token. A token memory having token packet allocating means for giving the complete token packet to the functional unit, and the functional unit directly receiving the exception processing request signal,
If a token having a higher priority than a token controlling a normal program is output, and if the contents of a complete token packet having a high priority output from the token memory does not change the priority, The parallel processing computer, wherein the functional unit outputs a result token that holds the high priority. 3. An exception processing token generation circuit which outputs an exception processing result token based on an exception processing request, an exception token memory which stores the exception processing result token, and a normal memory which stores a token for controlling a normal program. When a token memory and a complete token packet are input, a plurality of functional units that process the data in the token packet and output a result token, and when the exception complete token packet is created in the exception token memory, each functional A switching circuit for switching the connection of the complete token packet input section of the unit from the normal token memory to the exception token memory, and the functional unit to which the exception processing complete token packet output from the exception token memory is input, Exception handling complete Unless token packet is not the one whose content the exception processing is ended, the result in order to output the token with the exception processing result token, parallel processing computer, characterized in that operate to switch said switching circuit to the exception token memory. 4. An exception processing token generation circuit that outputs an exception processing result token having priority based on an exception processing request, and a plurality of circuits that input a complete token packet, process data in the token packet, and output a result token. Functional unit, memory means for storing the exception processing result token and a normal token having a priority and for controlling a normal program, and when a complete token packet is formed therein, the token has a high priority. According to the order, a token memory having token packet assigning means for giving the complete token packet to a functional unit in a state in which the complete token packet can be received, and the priority of the exception processing result token is Parallel processing computer being higher than normal token.