JP2534303B2 - Test method for semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor memory device, and more particularly, for example, a DRAM (Dynamic Random Access M).
emory) test method.

2. Description of the Related Art Among semiconductor memory devices, DRAM has a structure in which electric charge accumulated in a capacitor is used as stored data, and data is lost in the form of leakage current over time. A refresh operation is required in which data is periodically read, amplified, and rewritten. This DR
In AM, memory cells for each row of a memory cell array configured by arranging memory cells in a matrix are connected to one word line, respectively, and are different for each cycle of the refresh operation. One word line is selected, and all the memory cells connected to the word line, that is, the data in the memory cells for one row are simultaneously refreshed.

Conventionally, as one of the tests of this DRAM, a function test for confirming whether or not the data written in each memory cell is correctly read out next over all the memory cells has been performed by the following procedure.

First, test patterns such as a march pattern, a checkerboard pattern, and a diagonal pattern in which all DRAM memory cells are associated with test data according to a certain corresponding format are set in a predetermined test device, and the test pattern The test data output from the test device is sequentially written into the corresponding memory cells according to the address order. At this time, the writing order, that is, the address order of the test pattern is an address order obtained by assigning the row address of the memory cell as a numerical value in the lower digit and the column address of the memory cell as a numerical value in the upper digit. That is, in the memory cell group in the first column of the memory cell array, starting from the memory cell in the first row, and then the memory cells in the second and third rows, the addressing for one column is performed according to the row order. When this is completed, the memory cell group of the second column is moved to and addressing is performed according to the row order in the same manner. Then, addressing is performed to the last row in the same manner.

FIG. 3A shows a timing chart of the write operation in the function test. In the figure, the address of the test data to be written first is [0,0], that is, both the upper digit value and the lower digit value are "0", and the DRAM has a row address of "0" and a column address of "0". Are input, the row address “0” is sampled by activating the row address strobe signal ▲ ▼, and the column address “0” is sampled by activating the column address strobe signal ▲ ▼. , Test data is written in the memory cell at the row address “0” and the column address “0”. The address of the second test data to be written is [0,1], the row address "1" and the column address "0" are input to the DRAM, and the row address "1" and the column address "0" are input. Test data is written in the memory cell. Hereinafter, when the test data is sequentially written to all the memory cells of the same column address “0”, the column address is moved up to “1” next, and all the memory cells of the column address “1” are written. Similarly, test data is sequentially written. The above operation is repeated for all column addresses. As a result, the test data is written in all the memory cells of the memory capacity n.

FIG. 3 (b) shows a timing chart of the read operation in the above function test, and the address order is exactly the same in the write operation.

By the way, as a DRAM test, there is a refresh test for confirming whether refreshed data is read as correct data after a certain time. As described above, the refresh operation selects different words for each cycle. That is, a refresh operation is performed by designating a different row address for each cycle.

In order to improve the efficiency of the whole test, it is desirable to perform the refresh test in parallel with the above function test, but the row address of the memory cell is assigned to the lower digit of the address of the test pattern used for the function test. Therefore, the row address specified by the function test is switched in a short cycle. Therefore, to prevent the row address specified in the function test and the row address specified in the refresh test from overlapping,
It becomes necessary to shorten the cycle time of the refresh test, that is, the time from the refreshing to the data reading. Therefore,
Conventionally, in order to perform a refresh test having a long cycle time, another test pattern is used to perform the refresh test separately from the function test.

SUMMARY OF THE INVENTION However, in the above-described conventional test method, in order to perform a refresh test with a long cycle time,
Since the test must be performed separately from the function test, there is a problem that the test time becomes long and it takes time and effort to create the test pattern separately.

Therefore, it is an object of the present invention to provide a semiconductor device test method that can shorten the overall test time and that does not require any effort to create a test pattern.

Means for Solving the Problems The present invention was prepared as a test pattern in which all memory cells of a memory cell array in which memory cells are arranged in a matrix are addressed in a fixed order and each memory cell is associated with them. After writing the test data, all the memory cells are addressed in a fixed order to read the stored data in each memory cell, and the function test is performed to compare the read data with the test data to judge the pass / fail. In the method of testing a memory device, of the row address and the column address of a memory cell, the row address is assigned as a numerical value in the higher digit and the column address is assigned as a numerical value in the lower digit, and the write and read operations are performed according to the address order. By performing addressing, the funk In parallel with the test test, the rows not subjected to the function test are refreshed and the stored data in the memory cells after a certain time has elapsed are read, and the read data and the test data are read. A semiconductor memory device test method is characterized in that a refresh test for comparing pass / fail is performed with the same test data prepared as a test pattern used in the function test.

According to the present invention, the writing and reading of the function test are performed in parallel with the order of addresses in which the column address of the memory cell is the lower digit value and the row address of the memory cell is the upper digit value. , After a certain period of time after refreshing the memory cells in the row for which the function test has not been performed, the stored data in the memory cells is read, and the read data is compared with the test data to determine the pass / fail. Since the determination refresh test is performed, the switching cycle of the row address designated in the function test becomes long, and a refresh test having a long cycle time can be performed in parallel with this test.

Embodiment FIG. 1 is a schematic diagram showing the configuration of a DRAM memory cell array having a memory capacity of k × k (= n) bits to which a test method according to an embodiment of the present invention is applied. In the figure, 1 is a plurality of word lines arranged in parallel with each other, 2 is a plurality of bit lines arranged in parallel with each other in a direction intersecting with the word line 1, each at a crossing position of the word line 1 and the bit line 2. The memory cells M _{1 to} M _n are arranged and arranged in a matrix as a whole. The word line 1 corresponds to the row direction of the memory cell array, and the bit line 2 corresponds to the column direction of the memory cell array. A row address is assigned to each word line 1 and an address is assigned to each bit line 2. Has been. Reference numeral 3 denotes an amplifier circuit called a sense amplifier that amplifies the data read from the memory cells M _{1 to} M _n .

In this embodiment, the function test is performed on the DRAM as follows.

First, the test data prepared in a one-to-one correspondence with the memory cells M _{1 to} M _{n of the} memory cell array are set in the test device as a test pattern in a predetermined address order. The address of this test pattern is determined by assigning the row address of each of the memory cells M _{1 to} M _n of the memory cell array as the numerical value of the upper digit and the column address of each of the memory cells M _{1 to} M _n as the numerical value of the lower digit. To be That is, the address in the test pattern of the test data associated with the memory cell having the row address R and the column address C is defined as [R, C].

The test data set in the test device is output from the test device according to the address order of the test pattern described above, and the corresponding memory cell of the memory cell array is output.
Sequentially written to M _{1 to} M _n . That is, the test data
In parallel with the input to the DRAM, the numerical value of the high-order digit of the array of the test data is input to the DRAM as the row address and the numerical value of the low-order digit is input to the DRAM, respectively, and addressed by the row address and the column address. Test data is written in the memory cell.

FIG. 2 (a) shows a timing chart of the write operation. In the figure, the address of the test data to be written first is [0,0], that is, the upper digit is "0", the lower digit is "0", and the DRAM has "0" as the row address and "0" as the column address. The row address “0” is sampled by activating the row address strobe signal ▲ ▼, and then the column address strobe signal ▲ ▼.
CAS and the column address "0" by activating is sampled, the row address "0", the test data is written to the memory cell M ₁ Ri column address "0".
The address of the second test data written is [0,
1], the row address “0” and the column address “1” are input to the DRAM, and the row address “0”,
The test data is written in the memory cell M ₂ of the column address “1”. Hereinafter, when test data is sequentially written to all k memory cells of the same row address “0”,
Next, the row address is moved up to "1", and the test data is similarly written sequentially to all the k memory cells of the column address "1". The above operation is repeated up to k rows. As a result, M ₁ , M ₂ , ..., M _k , M _{k + 2} , shown in FIG.
…, M _2k , M _{2k + 1} , M _{2k + 2} ,… M 3 _k , M 3 _{k + 1} ,…, M _{n-k + 1} , M _{n-k + 2} , M _n
The test data is written in all the memory cells M _{1 to} M _n in this order.

Next, the data of all the memory cells M ₁ ~M _n is issued write successively in the same address sequence as in the write operation described above. FIG. 2B shows a timing chart of the read operation. In parallel with this, the test device outputs test data according to the address order of the test pattern as in the write operation described above, and the test data and DR
The data read from AM is compared. At this time,
The memory cell from which data is read corresponds to the memory cell to which the same test data as the test data to be compared was written in the previous write operation, and if these data match, it is judged as “good”. If they do not match, it is determined to be “defective”.

As described above, in the function test, the access to the memory cells M _{1 to} M _n is sequentially switched in the row direction, so that the specified row is accessed until all k memory cells for one row are accessed. Does not switch. Therefore, if another row is designated to perform the refresh test during that period, the refresh test having a long cycle time can be performed in parallel with the function test using the same test pattern.

As described above, according to the semiconductor memory device testing method of the present invention, the switching cycle of the row access designated in the function test becomes long, and in parallel with this, the refresh test having a long cycle time is performed. As a result, the efficiency of the test is improved and the labor required for creating the test pattern can be reduced. The present invention is particularly effective for testing a large-capacity memory, and further achieves an effect that it does not take time and effort to create or modify a test pattern.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of a DRAM memory cell array to which a test method according to an embodiment of the present invention is applied, and FIG. 2 (a) is a timing chart showing a write operation in the test method. FIG. 3B is a timing chart showing the read operation in the test method, FIG. 3A is a timing chart showing the read operation in the conventional test method, and FIG. 3B is the read operation in the test method. It is a timing chart. 1 ...... word line, 2 ...... bit lines, M ₁ ~M _n ...... memory cell

Claims (1)

(57) [Claims] 1. After all memory cells of a memory cell array in which memory cells are arranged in a matrix are addressed in a fixed order and test data prepared as a test pattern associated with these is written to each memory cell. In a method of testing a semiconductor memory device, a function test is performed, in which all memory cells are addressed in a fixed order to read the storage data of each memory cell, and the read data is compared with the test data to determine pass / fail. Of the row address and the column address of the memory cell, the row address is assigned as a numerical value in the upper digit, and the column address is assigned as a numerical value in the lower digit. Function test and flat Then, the stored data of the memory cell after a certain period of time is refreshed after the refresh is performed on the row where the function test is not performed, and the read data is compared with the test data to determine the pass / fail. A test method for a semiconductor memory device, characterized in that a refresh test for judging is performed with the same test data as the test data prepared as a test pattern used in the function test.