JP2528468B2 - Stable display method of digital display and its circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a stable display method for a digital display and its circuit, and prevents flickering of a display value.

[Conventional technology]

In many cases, the measured values of the length measuring machine, the angle measuring machine, the displacement detector, etc., and the movement displacement amount of the machine tool table, etc. are displayed on the digital display. For example, in the digital display type caliper 1 shown in FIG. 7, an encoder 60 for detecting the relative movement displacement amount of the main scale 2 and the slider 4 is built in the slider 4, and the output signal of the encoder 60 is applied to the surface of the slider 4. It has a structure for driving the digital display 6 provided. Therefore, if the object 4 to be measured is sandwiched between the pair of jaws 3 and 5 by moving the slider 4, the diameter D thereof is digitally displayed, so that reading is easier, quicker and more accurate than the conventional mechanical scale method. I was able to.

[Problems to be solved by the invention]

However, in the above-mentioned conventional exemplary digital display 1, since the resolution (graduation) is set to 0.01 mm, when the true value of the diameter D of the measuring object 8 is 15.569 mm, the device configuration is 15.5 mm.
Where it should be displayed as 6 mm (see FIG. 8 (A)), the measured value is displayed as 15.57 mm as shown in FIG. 8 (B) due to the improper clamping by both jaws 3 and 5, vibration, etc. Sometimes. That is, it is displayed faithfully based on the output signal of the built-in encoder 60. Therefore, 15.56mm and 15.57
The so-called flicker phenomenon occurs in which mm and mm are alternately switched and displayed within a short time, and there is a problem that it is particularly difficult to read the lowest display digit. Furthermore, the flicker phenomenon in the above case caused a probability of reading as 15.58 mm, and significantly lowered the measurement accuracy and work efficiency.

The present invention has been made based on the above conventional circumstances, and an object of the present invention is to provide a stable display method for a digital display capable of eliminating the flicker phenomenon in the lowest digit of the display value and achieving stable display that is easy to read. It is to provide the circuit.

[Means for Solving Problems] The present invention focuses on the fact that the above-mentioned conventional problems directly display an input value from an encoder or the like and that the flicker phenomenon occurs at the lowest display digit. The display value of the lowest display digit is stabilized by a predetermined process.

Therefore, the first aspect of the invention is to perform the first step of presetting the same initial value in each of the first data register and the second data register having the display digit and the fractional digit, and the input value to the first data register. The value D _{1 of the} display digit stored and stored is compared with the value D _{2 of the} display digit stored in the second data register, and D ₁ = D ₂ , D ₁ >
The second step of selecting a different offset value C depending on whether D ₂ and D ₁ <D ₂ and the contents of the second data register are stored in the selected offset value C and the first data register. And a third step of outputting the value (D ₂ ) of the display digit of the updated addition value to the digital display, and repeating the second step and the third step. The above-mentioned object is achieved by a configuration in which the display value of the digital display is updated.

A second aspect of the present invention is directed to first and second data registers having a display digit and a fractional digit, a preset circuit for presetting the same initial value in each of the first and second data registers, and a first invention. The value D ₁ of the display digit stored in the data register is compared with the value D _{2 of the} display digit stored in the second data register, and D ₁ = D ₂ , D ₁ > D ₂ and D ₁ <D ₂ A comparison circuit that outputs a determination signal indicating which of the two is selected, a selection circuit that selects an offset value C that is predetermined based on the determination signal from this comparison circuit, the selected offset value C, and the first offset value C. Adder for adding the input value stored in the data register of, the set circuit for updating and setting the added value from the adder in the second data register, and the adder stored in the second data register Digital display of the value D ₂ of the display digit of the value A drive circuit for displaying on a display is provided to achieve the above object.

[Action]

In the first aspect of the present invention configured as above, the same initial value (for example, zero value or arbitrary numerical value) is preset in the first data register and the second data register in the first step. Next, the input value input from the encoder or the like is stored in the first data register, and the values D ₁ and D ₂ stored in the display digits of both data registers are compared and predetermined based on the comparison result. A specific offset value C is selected from among the plurality of selected offset values. In this way, the offset value C obtained in the second step is added to the stored value of the second data register (the preset value for the first time) in the third step.
While the second step and the third step are repeated, the value (D ₂ ) of the display digit of the added value stored in the second data register is displayed on the digital display. Therefore, even if an input value that changes repeatedly is input, the input value is not displayed immediately, but is corrected by the offset value determined in relation to the value displayed on the digital display and the value of the display digit (D ₂ ) Is displayed, the flicker phenomenon can be eliminated.

Further, in the second invention, the same initial value is preset in the first and second data registers from the preset circuit. The next input value is stored corresponding to the display digit and the fractional digit of the first data register. Then, the comparator circuit stores the value (D ₁ ,
D ₂ ), and _one of D ₁ = D ₂ , D ₁ > D ₂ and D ₁ <D ₂ is determined, and the corresponding offset value C is selected by the selection circuit.

The content of the second data register is updated and set to an addition value obtained by adding the selected offset value to the value stored in the first data register. Here, the value (D ₂ ) stored in the display digit of the updated and set second data register is displayed on the digital display. Therefore, the flicker phenomenon can be removed as in the case of the first invention.

〔Example〕

An embodiment of a stable display method of a digital display and a circuit thereof according to the present invention will be described in detail with reference to the drawings.

(First Embodiment) This first embodiment is provided with a stable display circuit for carrying out a stable display method in a digital display type caliper similar to the conventional digital display type caliper shown in FIG. This is the case. Therefore, the same components as those of the conventional digital display type caliper are designated by the same reference numerals.

In FIG. 2, the stable display circuit 10 includes a first data register 12, a second data register 22, and a presetter 34.
And a comparison bottleneck 35, a selection circuit 36, an adder 37, a set circuit 38, a drive circuit 39, and a controller (not shown).

First, the first and second data registers 12 and 22 are
As shown in the figure, it is composed of five display digits 14, 24 and two fractional digits 16, 26 which are equal to the number of digits of the digital display 6. The first data register 12 stores the input value from the photoelectric encoder 60 having an optical grating. Here, the input value is supposed to include a value of resolution (0.001, 0.0001 mm) which is smaller than the resolution of the lowest display digit of the value displayed on the digital display 6 (graduation: 0.01 mm). There is. Therefore, as shown in the first step S10, the measured value (for example, 11
5.2123 mm) is stored in the first data register 12 as it is. The display digit 14 of the first data register 12 is formed so as to store 115.21, and the fraction digit 16 is formed so as to store 23. The second data register 22 can also store the same 7-digit numerical value. Here, it is understood that the encoder 60 has a configuration capable of outputting the lower digit data having a resolution smaller than the resolution displayed on the digital display 6.

Next, the presetter 34 is for forming an initial state, and prior to the measurement, the presetter 34 and the second data register 12
The same numerical value (initial value) can be simultaneously preset in the data register 22 of. Preset values are both jaws 3,
It is a zero value set when 5 is abutted, a dimensional value corresponding to the diameter set when sandwiching the reference measurement object 8 or an arbitrary value.

Further, the comparison circuit 35 has the functions shown in steps S12, S14 and S16, and among the values stored in the first data register 12, the value D ₁ of the display digit 14 and the second data register 22 are stored. While comparing the value D ₂ of the display digit 24 of the values, D ₁ =
It is formed so as to be able to output a determination signal as to which one of D ₂ , D ₁ > D ₂ and D ₁ <D ₂ . On the other hand, the selection circuit
Reference numeral 36 selects one of a plurality of offset values C determined in advance based on the judgment signal of the comparison circuit 35. In this embodiment, as shown in steps S18, S20, S22, E = The offset value C when 0 (D ₁ = D ₂ ) is zero (0), and the offset value C when E> 0 (D ₁ > D ₂ ) is −
Offset value C when P ₂ (≦ 0) and E <0 (D ₁ <D ₂ ).
Is determined to be P ₁ (≧ 0), and P ₁ and P ₂ are set to 0.005 mm.

Further, the adder 37 reads the offset value C thus selected and the values stored in the first data register 12 (the value D ₁ of the display digit 14 and the value d _{1 of the} fraction digit 16). Both are added. The added value (D ₁ + d ₁ + C) indicates the value (D ₂ + d ₂ ) stored in the second data register 22. The setting circuit 38 is provided for this purpose. These are displayed in step S24 in FIG.

Here, the drive circuit 39 digitally displays the value D ₂ stored in the display digit 24 of the added value [D ₂ + d ₂ (= D ₁ + d ₁ + C)] stored in the second data register 22. It is configured to display on the display 6 (see step S26 in FIG. 1).

Next, the operation of the first embodiment will be described with reference to FIGS.

(First Step) In the first step, the same initial value is preset in each of the first data register 12 and the second data register 22, and for convenience of description, as shown in FIG. 3 (A). When the value corresponding to the least significant display digit of each data register 12, 22 is set to 0, 1, 2, ..., the value V corresponding to the fractional digit 16, 26
It is assumed that (equivalent to 0.005 mm) is set in the presetter and preset in each data register 12, 22. Further, for convenience of description, in the case of the first data register 12, V,
In case of the second data register 22, V '(= V)
Illustrated as. The preset value is the same as the value of all digits of the data registers 12 and 22 (for example, 115.2123).

(Second Step) In the second step, the input value (measured value) is stored in the first data register 12 and the stored value D _{1 of} the display digit 14 is stored.
And the value D ₂ of the display digit 24 stored in the second data register 22 are compared by the comparison circuit 35, and D ₁ = D ₂ , D ₁ > D ₂ and
It is a step of selecting the offset value C by the selection circuit 36 by any _{one of} D ₁ <D ₂ . First, step S1 in FIG.
At 0, the input value (D ₁ + d ₁ ) which is the measured value input from the encoder 60 is read and the first data register 12
To memorize. Let the input value (D ₁ + d ₁ ) be V shown in FIG. 3 (A). V is the value of d ₁ corresponding to the fractional digit 16, and in this case D ₁ corresponding to the display digit 14 is zero (0). continue,
In steps S12, S14, S16 and S18, the value D ₁ of the display digit 14 in the value stored in the first data register 12 and the display digit 24 of the value stored in the second data register 22 The value D ₂ is compared to find the corresponding offset value C. Specifically, seek E = D ₁ -D ₂ in step S12. D ₁ is zero (0), and D ₂ is naturally zero (0) because the value V ′ (= V) according to the previous preset is smaller than zero (0). Therefore E
= 0−0 = 0, and the offset value C becomes zero (0). Here, the offset value C is selected to be zero (0).

(Third step) The content of the second data register 22 is added value (D ₁ + d ₁ ) of the selected offset value C and the input value (D ₁ + d ₁ ) stored in the first data register 12. + C) and a value (D ₂ ) at the display digit 24 of the updated addition value [D ₂ + d ₂ (= D ₁ + d ₁ + C)] is output to the digital display 6.

As shown in step S24, the input value (D ₁ + d
₁ ) and offset value C are added. Here, the added value is V
Since (= D ₁ + d ₁ + C = 0 + V + 0), the value (D ₂ + d ₂ ) updated in the second data register 22 is V ′ (= V).
The value D ₂ of the display digit 24 is zero (0), and the value d ₂ of the fraction digit 26 is V ′. Therefore, since the value D ₂ of the display digit 24 of the second data register 22 in the first order is zero (0), the digital display 6 displays zero (0) by the drive circuit 39.

(Repeating Step) In the repeating step, the second step and the third step are repeated to remove the flicker phenomenon and display a stable measurement value on the digital display 6.

In FIG. 3 (A), the output of the encoder 60 is the value W.
It is assumed that the measured value of (> V) is output. Then, in the second order, in step S10, the first data register 1
The value D ₁ of the display digit 14 of 2 is rewritten to zero (0), and the value d ₁ of the fractional digit 16 is rewritten to the above W in place of the preset value V. In this case, the value D ₂ of the display digit 24 of the second data register 22 is zero (0), so E = D ₁ -D ₂ = 0-0 = 0 and C = 0. Therefore, the added value (D ₁ + d ₁ + C) is W (= 0 + W +
0), the contents of the second data register 22 to be updated become D ₂ = 0 and d ₂ = W '(= W), and as a result, the display value of the digital display 60 becomes 0.

Next, assuming that the output of the encoder 60 changes from W to X, in the third order, D ₁ = of the first data register 12
1, d ₁ = X−1. In this case the second data register
The value D ₂ of the display digit 24 of 22 is zero (0) (D ₂ = 0), so E
= D ₁ −D ₂ = 1> 0. In this case, -P ₂ ≤0 is selected as the offset value C in step S20. In this example, P ₂
= 0.005. Therefore, in step S24, D ₂ + d ₂
= The _{D 1 + d 1 + C =} 1 + X-1-P 2 = X-P 2 = X '.
Therefore, D ₂ = 0, d ₂ = X ′ <0 of the second data register 22.
Therefore, the display value of the digital display 6 is still zero (0). Here, if the output of the encoder 60 becomes W again, in the fourth order, E = D ₁ −D ₂ = 0−0 = 0,
Since C = 0, D ₂ = W ', and the display value of the digital display 6 remains the same as zero (0). Thus, even if the output of the encoder 60 repeatedly changes to the upper and lower values (W and X) of the lowest display digit, for example, "1" in Fig. 3 (A), the display value of the digital display 6 is changed. Since it does not change, the flicker phenomenon can be eliminated.

Next, as shown in FIG. 3 (B), the output of the encoder 60 is y (> 1) and D _{2 of} the second data register 22 is y ′.
It is assumed that the output (measured value = input value) of the encoder 60 changes to Z while the display of the digital display 60 is zero (0) after the above because of (<1). Then
Since D ₁ = 1, d ₁ = Z−1, D ₂ = 0, d ₂ = y ′, E
= The _{D 1 -D 2 = 1-0 = 1} . Therefore, the offset value C
Is -P ₂ and the added value is D ₁ + d ₁ + C = 1 + Z-1-P ₂ = Z-P ₂
As a result, in step S24, D ₂ + d ₂ = Z−P ₂ = Z ′. Since this is D ₂ = 1 and d ₂ = Z′−1, the display value is updated to “1”.

Subsequently, when the output of the encoder 60 decreases from Z to y, E = D ₁ −D ₂ = 1−1 = 0, C = 0, and thus D ₂ + d ₂ = D ₁ +
d ₁ + C = y, and D ₂ + d ₂ = y ″ (= y), D ₂ = 1 and d ₂
= Y ″ −1, the displayed value remains “1”. Similarly, when the output of the encoder 60 changes from y to Z again,
D ₂ + d ₂ = Z ″. Thus, even if the output of the encoder 60 changes alternately with y and Z, the display value of the digital display 6 is “1”.

In the above description, the case of fluctuation between certain values when the output of the encoder 60 is in the increasing direction has been described.
Since the offset value C is set to zero (0) or P ₁ > 0 based on steps S18 and S22 in the figure, the flicker phenomenon can be eliminated as in the above case.

According to this embodiment, the display value is updated while the output value of the encoder 60 is not directly displayed on the digital display 6 and the input value from the encoder 60 is corrected by the offset value C in relation to the previous display value. The flicker phenomenon can be completely eliminated even if the encoder output fluctuates slightly back and forth with respect to a certain value of the lowest display digit of the digital display 6. Therefore, it is possible to read quickly and accurately.

(Second Embodiment) In the second embodiment, the encoder 60 capable of outputting a measurement value having a finer resolution than the resolution (graduation) of the lowest display digit of the digital display 6 is employed in the first embodiment. On the other hand, the present invention is implemented while creating a fine resolution by averaging the measurement values having the same resolution as the resolution of the lowest display digit.

The target device is the digital display type caliper shown in FIG. 7 as in the case of the first embodiment.

4 and 6, the stable display circuit 10 is composed of a central processing unit (CPU) 31 and a data register 11, and the CPU 31 in this embodiment includes the presetter 34, the comparison circuit 35, and the presetter 34 in the first embodiment. The function is similar to that of the selection circuit 36, the adder 37, the set circuit 38, etc., and is a concept wider than that of a general CPU. In addition, the data register 11
The first has a display digit 14 and a fractional digit 16 as shown in FIG.
Data register 12 and second data register 22 having display digit 24 and fractional digit 26, and the same number of digits of display digits 14 and 24 of data register 12 and 22 for storing the measured value (input value) A third number data register 28 is incorporated.

As shown in FIG. 4, the encoder 60 of the present embodiment is of the electrostatic capacitance type, and has grid electrodes 61 arranged in the longitudinal direction of the main scale 2 at a constant pitch P and the grid electrodes 61. A ground electrode 62, which is grounded to the main scale 2 and the like disposed between 61 and 61, and 8 mounted on the slider 4.
One set of transmission electrodes 63 consisting of a total of 16 sets of transmission electrode elements, one set of two sets of transmission electrode elements, a reception electrode 64 arranged in parallel in the same length as the transmission electrodes 63, and the other (others). The same applies to the transmission circuit 73 for applying a transmission signal a of 360 ° divided into eight phases to the respective transmission electrode elements forming the same, and the relative displacement of the transmission electrode 63 and the grid electrode 61 Receiving circuit 64 that receives the receiving signal b from the changing receiving electrode 64
And the relative amount of displacement of the transmission electrode 63 (slider 4) and the grid electrode 61 (main scale 1) connected to the transmission circuit 73 and the reception circuit 74 by the phase discrimination method, that is, the measured value of the clock pulse CP. The input value (measured value) input from the counting circuit 71 to the CPU 31 is specified as binary pulse data with a unit of 10 μm.

Therefore, if the transmission signal a'applied to the leftmost transmission electrode element in FIG. 4 is a sine wave signal having the period T shown in FIG. 5 (A), the reception signal b is as shown in FIG. 4 (B). The phase is shifted according to the relative movement displacement. Here, in the counting circuit 71, the product (n × P) of the number n of the lattice electrodes 61 that have passed and the arrangement pitch P of the lattice electrodes 61 and the count value ΔZi within the pitch P (see FIG. 5). △ Z ₁ , △ Z ₂ ,…) and the count value
Calculate Zi (measured value Di). Actually, the constant value D ₀ preset at power-on and the display unit (mm or inch)
In consideration of the conversion factor k of the measured values _{Di = kZi + kZ 0 + D} 0
(However, Z ₀ is an initial value). Further, various conditions of the encoder 60 (the pitch P of the grid electrode 61, the period T of the transmission signal a, the period t of the clock pulse CP when the scale (resolution) of the lowest display digit of the digital display 6 is r _{0. 0} ) is defined as P: r ₀ = T: t ₀ to r ₀ / P = t ₀ / T.

The period T is divided from the clock pulse CP of the period t ₀ . From this relationship, the scale of the lowest display digit
To obtain a measured value (Di) with a resolution less than r ₀ , And must be. Here, in the present embodiment, since the resolution equal to or less than the scale interval r ₀ is obtained by the averaging method, the practicality that the encoder 61 and thus the entire caliper can be miniaturized is enhanced.

In this embodiment having such a configuration, the following operations are performed.

(First Step) The same initial value is preset in the first data register 12 and the second data register 22 of the data register 11. Here, the value of the least significant digit (0 or 1) of the display digit 14 of the first data register 12 is B ', and the value of the most significant digit (0 or 1) of the fractional digit 16 is b', and the data register 22 The value (0 or 1) of the least significant digit of the display digit 24 of B is designated as B, and the value (0 or 1) of the highest digit of the fractional digit 26 is designated as b.

(Second step) The second step is step S1 in the flowchart shown in FIG.
It is executed in 00 to S116.

First, the input value (measured value) di from the encoder 60 is the third
Is taken into the data register 28 and the CPU 31 performs averaging calculation processing N times (steps S102 to S106). Therefore, even if the measured value from the encoder 60 is the resolution of the lowest display digit of the digital display 6, it is possible to calculate a finer resolution value. The measured value D ₁ thus obtained is set in the first data register 12. Therefore, it is reset in advance in step S100. Specifically, B'is set to the least significant digit of the display digit 14 of the first data register 12 and fraction b'is set to the most significant digit of the fraction digit 16. Next, the CPU 31 determines the value B ′ (0 or 1) of the least significant display digit of the first data register 12 and the second data register 22.
The value B (0 or 1) of the least significant display digit of is also compared using the value b (0 or 1) of the most significant fractional digit of the second data register 12 (steps S108, S110, S11).
2). That is, each data register 12, 22 in the first embodiment
Comparing the values D ₁ and D ₂ stored in the display digits 14 and 24 of
This is equivalent to the steps S12, S14, S16 in the figure, and first, by comparing only the values B ', B of the least significant display digits of the registers 12, 22, the comparison process is simplified and speeded up. is there. That, B in step S110 '= B (D ₁ =
When it is determined to be D ₂ ), zero (0) is selected as the offset value C. When it is determined that B '≠ B (D ₁ > D ₂ or D ₁ <D ₂ ), the value b of the most significant fractional digit of the value D ₂ stored in the second data register 22 last time is “ Judging whether it is 1 "or" 0 ", D ₁ > D ₂ or D ₁ <D ₂ is judged. Since the input value (measured value) is a binary number, if the value b is "1", the value D ₁ is highly likely to be higher than the previous value, while if the value b is "0", the value is This is because it can be considered that D ₁ has fallen behind the previous time (step S112). Therefore,
When b = 1, it is judged that D ₁ > D ₂ and the offset value C to be selected is P ₁ (0 <P ₁ <1), and when b = 0, D ₁ <D ₂
Therefore, the offset value C becomes zero (0) in step S114. Incidentally, step S114 serves as both steps S20 and S18 of FIG. 1 of the first embodiment.

(Third Process) Subsequently, the CPU 31 performs D ₂ = D _{1 in} steps S118 and S120.
+ C is obtained, the value D ₂ is updated and set in the second data register 22, and the value set in the display digit 24 is output to the digital display 6. Note that S122 and S124 represent the reading procedure for the comparison (steps S100 and S112).

(Repeating Step) Hereinafter, steps S102 to S124 are repeated to stabilize the display value of the digital display 6 and remove the flicker phenomenon as in the first embodiment.

Therefore, according to the second embodiment, as in the case of the first embodiment, even if the input value (measured value) from the encoder 60 may fluctuate by a small value due to vibration or the like, the previous measured value
The flicker phenomenon can be removed by comparing and judging D ₁ and the measured value D ₂ this time. Further, since the measured value (input value) is binary data, the display stabilizing circuit 10 can be simply and economically embodied like the CPU 31 and the data register 11. Further, the first data register 12 and the second data register 22
And each value D ₁ , D ₂ is compared with the value of the least significant digit of each display digit 14,24.
Since it is performed by B and B ', high speed processing is possible. Furthermore, since the value b '(b) having a resolution finer than the resolution of the least significant digit of the displayed value is created by averaging the measured values (input values), the encoder 60 is equivalent to the least significant digit of the displayed value. Since it is possible to have resolution, not only the encoder itself but also the entire digital display type caliper can be made small, lightweight and inexpensive.

In the above embodiments, the device to be used was a digital display type caliper, but the point is that it is sufficient if the device is equipped with a digital display for displaying measured values, etc. The present invention is applied to any target device such as a goniometer, an electronic scale and the like.

Further, the photoelectric type and electrostatic capacity type encoders 60 are exemplified as the input value generating means to the display stabilizing circuit 10, but the generating means such as the type of the encoder 60 is not limited to the above disclosed range. Further, not only the model and the number of digits of the digital display 6 but also the resolution of the lowest display digit can be freely selected. This is because a value having a finer resolution may be created as in the second embodiment, for example.

Further, the display mode on the digital display 6 may be an incremental type or an absolute type, and the present invention is effectively applied regardless of the unit or the like.

〔The invention's effect〕

As is clear from the above description, the present invention is configured to determine the new display value of this time by weighing the previous display value and the input value of this time, and selecting the optimum offset value. It has an excellent effect of completely eliminating the flicker phenomenon.

[Brief description of drawings]

1 to 3 show a first embodiment of a stable display method of a digital display and a circuit thereof according to the present invention, FIG. 1 is a flow chart, FIG. 2 is a block diagram showing a circuit configuration, and FIG. FIGS. 4 (A) and 4 (B) are explanatory views of the operation, FIGS. 4 to 6 are the same as the second embodiment, FIG. 4 is a perspective view showing the overall configuration, and FIG. 5 is the timing of each signal of the encoder. FIG. 6 is a flow chart for explaining the operation, and FIG. 7 is an overall front view of a conventional digital display type caliper and FIG.
7A and 7B are front views of the digital display showing the display contents corresponding to FIG. 6 ... Digital display, 10 ... Stability display circuit, 11 ... Data register, 12 ... First data register, 14, 24 ...
… Display digit, 16,26 …… Fraction digit, 22 …… Second data register, 28 …… Third data register, 31 …… CPU, 35 ……
Comparison circuit, 36 ... Selection circuit, 37 ... Adder, 38 ... Set circuit, 39 ... Drive circuit.

Claims (4)

(57) [Claims] 1. A first step of presetting the same initial value in each of a first data register and a second data register having a display digit and a fractional digit, and storing an input value in the first data register. compared to the value D ₁ of the stored display digits, and a value D ₂ of display digits stored in the second data register _{with, D 1 = D 2, D} 1> D 2
And a second step of selecting a different offset value C depending on whether D ₁ <D ₂ and storing the contents of the second data register in the selected offset value C and the first data register. The value added to the existing value and outputting the value D ₂ of the display digit of the updated added value to the digital display, and the digital display while repeating the second step and the third step. A stable display method for a digital display, characterized in that the display value of the display is updated. 2. The method according to claim 1, wherein the second step is executed by using an average value of a plurality of input data obtained with a resolution corresponding to the least significant display digit of the first data register as the input value. A stable display method for a digital display, which is characterized in that 3. The method according to claim 1 or 2, wherein the offset value C is D ₁ = D _{2 in} the second step.
Is zero, and when D ₁ > D ₂ is zero or a negative number, D ₁
A stable display method for a digital display, which is executed as a zero value or a positive value when <D ₂ . 4. A first and a second having a display digit and a fractional digit.
Data register, a preset circuit for presetting the same initial value to each of the first and second data registers, and the display digit value D ₁ and the second digit stored in the first data register.
And compares the value D ₂ of display digits stored in the data register _{of, D 1 = D 2, D} 1> D 2 and D ₁ <comparator circuit for outputting a determination of whether the signal is either D ₂ And a selection circuit that selects a predetermined offset value C based on the determination signal from the comparison circuit, and an addition that adds the selected offset value C and the input value stored in the first data register. And a set circuit for updating and setting the added value from this adder in the second data register, and the value of the display digit of the added value stored in the second data register
A stable display circuit for a digital display, which includes a drive circuit for displaying D ₂ on the digital display.