JP2526654B2 - Electronic circuit package cage structure - Google Patents

Electronic circuit package cage structure

Info

Publication number
JP2526654B2
JP2526654B2 JP1017184A JP1718489A JP2526654B2 JP 2526654 B2 JP2526654 B2 JP 2526654B2 JP 1017184 A JP1017184 A JP 1017184A JP 1718489 A JP1718489 A JP 1718489A JP 2526654 B2 JP2526654 B2 JP 2526654B2
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
connector
guide
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1017184A
Other languages
Japanese (ja)
Other versions
JPH02197194A (en
Inventor
眞二 峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1017184A priority Critical patent/JP2526654B2/en
Publication of JPH02197194A publication Critical patent/JPH02197194A/en
Application granted granted Critical
Publication of JP2526654B2 publication Critical patent/JP2526654B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits

Landscapes

  • Casings For Electric Apparatus (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Combinations Of Printed Boards (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は電子機器における電子回路パッケージのケー
ジ構造に関する。The present invention relates to a cage structure of an electronic circuit package in electronic equipment.

［従来の技術］ 半導体素子を高密度に電子機器内に実装し接続する方
法としては、半導体素子を多数搭載した電子回路パッケ
ージ（以下ドーターボードと呼ぶ）をマザーボードへ３
次元実装するケージ構造を採るのが一般的である。[Prior Art] As a method of mounting and connecting semiconductor elements with high density in an electronic device, an electronic circuit package (hereinafter referred to as a daughter board) having a large number of semiconductor elements mounted on a mother board is used.
It is common to adopt a cage structure for three-dimensional mounting.

従来のケージ構造の例を第７図に示す。 An example of a conventional cage structure is shown in FIG.

半導体素子54,55を搭載した複数枚のドーターボード5
1はカードガイド59に案内挿入されてマザーボード52と
コネクタ53を介して電気的に接続される。ドーターボー
ド間の電気的接続は信号ケーブル66の相互接続及びコネ
クタ53,マザーボード52の内層を介して行なわれる。Multiple daughter boards 5 with semiconductor elements 54, 55
1 is guided and inserted into a card guide 59 and electrically connected to a mother board 52 via a connector 53. The electrical connections between the daughter boards are made through the interconnections of the signal cables 66 and the connectors 53, the inner layer of the motherboard 52.

ドーターボード51への給電は、給電バス56もしくは給
電ケーブル57、インサート58、マザーボード52内の導体
層、コネクタ53を介して行なわれる。Power is supplied to the daughter board 51 via the power supply bus 56 or the power supply cable 57, the insert 58, the conductor layer in the mother board 52, and the connector 53.

半導体素子54,55が発生する熱は、ケージ60の上下に
配置された送風機62による強制空冷によって電子機器の
外へ排出される。The heat generated by the semiconductor elements 54, 55 is discharged to the outside of the electronic device by forced air cooling by the blowers 62 arranged above and below the cage 60.

［発明が解決しようとする課題］ 近年来、電子機器の高性能化のため、半導体素子の高
集積度化、電子回路パッケージの大型化が必須となりそ
れに伴って消費電力も増大してきた。そのため前述した
従来技術には次のような問題点が生じてきた。[Problems to be Solved by the Invention] In recent years, in order to improve the performance of electronic devices, it has become essential to increase the degree of integration of semiconductor elements and increase the size of electronic circuit packages, and accordingly power consumption has increased. Therefore, the above-mentioned conventional technique has the following problems.

即ち、 プリント配線板（以下、PWBという）の大型化には製
造設備上の上限があるため、一枚のPWBに実装できる半
導体素子の数が制限される。That is, there is an upper limit on the manufacturing equipment for increasing the size of a printed wiring board (hereinafter referred to as PWB), and thus the number of semiconductor elements that can be mounted on one PWB is limited.

各種の半導体素子を一枚のPWBに混在実装するため、
層数が多くなる。積層数が多く、外形も大きいPWBは原
価的に不利である。Since various semiconductor elements are mixedly mounted on one PWB,
The number of layers increases. A PWB having a large number of layers and a large outer shape is disadvantageous in cost.

一般にメモリ系半導体素子は制御系半導体素子に比べ
て故障率が大きい。メモリ系半導体素子の障害時にはそ
のために高価な大型PWBを交換する必要があり、保守面
でのリスクが大きい。In general, memory system semiconductor elements have a higher failure rate than control system semiconductor elements. In the event of a memory semiconductor device failure, it is necessary to replace an expensive large PWB, which poses a major maintenance risk.

PWBの大型化のため、それを支えるカードガイドには
更なる強度が要求される。しかしそのためにカードガイ
ドの幅を広くすると、空気路の断面積が減り冷却能力が
落ちる。Due to the increase in the size of PWBs, the card guides that support them are required to have higher strength. However, if the width of the card guide is increased for that reason, the cross-sectional area of the air passage is reduced and the cooling capacity is lowered.

また、カード自体の自重のため、カードガイド上を滑
らす挿入性が悪くなる。Also, due to the weight of the card itself, the insertability of sliding on the card guide becomes poor.

従来技術ではマザーボードとドーターボードを接続す
るコネクタに、電源ピン、グランドピン、信号ピンが集
中する構造となっているため、コネクタ内のトータルピ
ン数に制約がある以上、電源の大容量化や信号数の増大
に対応できない。In the conventional technology, the power supply pins, ground pins, and signal pins are concentrated in the connector that connects the motherboard and the daughter board.Therefore, there is a limit to the total number of pins in the connector. It cannot cope with the increase in the number.

従来技術ではマザーボードに給電用の電源層を必要と
するため、また割高な電源／グランド／信号ピン内蔵コ
ネクタを使うため高価になる。In the prior art, the motherboard requires a power supply layer for power supply, and the expensive power supply / ground / signal pin built-in connector is used, which is expensive.

発熱量の大きい制御系半導体素子の冷却を空冷で実現
するには強力な送風機を必要とするが、近年要望が強い
低騒音化の実現性が乏しい。一方、個々の発熱量は小さ
いが絶対数が多いメモリ系半導体素子の冷却には適度な
能力を持つ送風機による空冷が最も効率がよい。低騒音
化を考えると両素子の冷却をまとめて空冷で実現するの
は困難である。Although a powerful blower is required to realize cooling of a control system semiconductor element, which generates a large amount of heat, by air cooling, it is not possible to realize low noise, which has been strongly demanded in recent years. On the other hand, air cooling by a blower, which has an appropriate capacity, is the most efficient for cooling a memory-based semiconductor element, which has a small amount of heat generation but a large absolute number. Considering low noise, it is difficult to realize cooling of both elements together by air cooling.

［課題を解決するための手段］ 本発明の電子回路パッケージのケージ構造は、同一平
面で一列に複数配され、かつ列方向に沿う一側面にコネ
クタを有するメモリ系半導体素子を搭載した第１のプリ
ント配線板と、制御系半導体素子が搭載され、一辺に第
１のコネクタを有し、該辺に隣り合う少なくとも一方の
辺に前記第１のプリント配線板のコネクタ群に嵌合する
複数個の第２のコネクタを有する第２のプリント配線板
とから構成される電子回路パッケージを、第３のプリン
ト配線板の一面に複数列設したコネクタに前記第２のプ
リント配線板の第１のコネクタを嵌合することによっ
て、水平に多段実装する電子回路のパッケージのケージ
構造であって、前記第２のプリント配線板の第２のコネ
クタを有する側の向かい合う二辺に設けた一対のガイド
スチフナと、前記第２のプリント配線板の両脇に配置さ
れ、前記第１のプリント配線板のコネクタ部分が挿入可
能な複数個の穴と、前記ガイドスチフナの下面に係合し
て前記第２のプリント配線板を案内挿入する複数個のこ
ろを有する一対のサイドフレームと、前記第１のプリン
ト配線板の挿入面側に配置された複数個のサイドバー
と、前記サイドフレームと前記サイドバーに両端が保持
され前記第１のプリント配線板の二辺に係合して案内挿
入するカードガイドと、 前記第３のプリント配線板と、前記一対のサイドフレ
ームと、前記複数個のサイドバーを保持するシャーシを
含む。[Means for Solving the Problems] A cage structure for an electronic circuit package according to the present invention is a first structure in which a plurality of memory semiconductor devices having a connector arranged on one side along the column direction are arranged in the same plane. A printed wiring board and a control system semiconductor element are mounted, a first connector is provided on one side, and a plurality of connectors that are fitted to the connector group of the first printed wiring board are provided on at least one side adjacent to the side. An electronic circuit package composed of a second printed wiring board having a second connector and a first connector of the second printed wiring board on a connector arranged in a plurality of rows on one surface of the third printed wiring board. A cage structure of a package of an electronic circuit that is horizontally mounted in multiple stages by fitting, and a pair provided on two opposite sides of the second printed wiring board having a second connector. Of the guide stiffener and a plurality of holes which are arranged on both sides of the second printed wiring board and into which the connector portions of the first printed wiring board can be inserted, and which engage with the lower surface of the guide stiffener and A pair of side frames having a plurality of rollers for guiding and inserting the second printed wiring board, a plurality of side bars arranged on the insertion surface side of the first printed wiring board, the side frame and the side. A card guide, both ends of which are held by a bar, which engages with and guides two sides of the first printed wiring board, the third printed wiring board, the pair of side frames, and the plurality of side bars. Including chassis to hold.

また、本発明の他の電子回路のパッケージのケージ構
造は、一端が凸部を有するＬ字型部材であって、他端が
前記第２のプリント配線板に設けたガイドスチフナの先
端に押圧された後、前記凸部を有する一端が前記ガイド
スチフナの側面を押圧保持するように、中央部に設けた
支点が回転自在に前記サイドフレームに保持された複数
対のカードホルダと、前記ガイドスチフナのもう一方の
端部を前記シャーシに固定する手段とを有する。The cage structure of another electronic circuit package according to the present invention is an L-shaped member having a convex portion at one end, and the other end pressed against the tip of a guide stiffener provided on the second printed wiring board. After that, one end having the convex portion presses and holds the side surface of the guide stiffener, and a fulcrum provided in the central portion is rotatably supported by the plurality of pairs of card holders and the guide stiffener. Means for fixing the other end to the chassis.

［実施例］ 次に本発明について図面を参照して説明する。Example Next, the present invention will be described with reference to the drawings.

第１図は本発明の実施例の平断面図である。第２図、
第３図、第４図、第５図はそれぞれ第１図のＡ−Ａ断面
図、Ｂ−Ｂ断面図、Ｃ−Ｃ断面図、Ｄ部詳細図である。
第６図は第２図のＥ−Ｅ断面図である。FIG. 1 is a plan sectional view of an embodiment of the present invention. Figure 2,
FIG. 3, FIG. 4, and FIG. 5 are a sectional view taken along the line AA, a sectional view taken along the line BB, a sectional view taken along the line CC of FIG.
FIG. 6 is a sectional view taken along line EE in FIG.

第１図において電子回路パッケージはメモリ系半導体
素子１を搭載した第１のPWB3と、制御系半導体素子２を
搭載した第２のPWB4とに分割されており、両者はコネク
タ６及び８の嵌合により電気的に接続される。電子回路
パッケージ間は第３のPWB5に列設されたコネクタ９と第
２のPWBのコネクタ７の嵌合により電気的に接続され
る。即ち複数の第１のPWB3と第２のPWB4から成る電子回
路パッケージが、第３のPWB5をマザーボードとして水平
に多段実装されている。In FIG. 1, the electronic circuit package is divided into a first PWB3 having a memory semiconductor element 1 mounted therein and a second PWB4 having a control semiconductor element 2 mounted therein, both of which are fitted with connectors 6 and 8. Electrically connected by. The electronic circuit packages are electrically connected to each other by fitting a connector 9 arranged in a line on the third PWB 5 and a connector 7 of the second PWB 5. That is, an electronic circuit package including a plurality of first PWBs 3 and second PWBs 4 is horizontally mounted in multiple stages using the third PWB 5 as a motherboard.

ところで効率のよい実装方式を実現するには、実装構
造、給電、冷却、接続等の多方面から最適解を見出す必
要がある。By the way, in order to realize an efficient mounting method, it is necessary to find an optimal solution from various aspects such as mounting structure, power feeding, cooling, and connection.

カードの案内構造について第１図、第２図、第３図、
第５図、第６図を用いて説明する。Regarding the guide structure of the card, FIG. 1, FIG. 2, FIG.
This will be described with reference to FIGS. 5 and 6.

第２のPWB4の両脇には一対のガイドスチフナ10が固定
されており、その下辺がサイドフレーム11に水平方向に
複数個設けたころ13に案内されて第２のPWB4がケージ内
に挿入される。尚、サイドフレーム11は第２のPWB4の両
側に対に配置されている。A pair of guide stiffeners 10 are fixed on both sides of the second PWB 4, and the lower side thereof is guided by rollers 13 provided in the horizontal direction on the side frame 11 to insert the second PWB 4 into the cage. It The side frames 11 are arranged in pairs on both sides of the second PWB 4.

第１のPWB3の両側かつ挿入面側にはサイドバー14が配
置されており、サイドバー14とサイドフレーム11の間に
はカードガイド15が橋わたしされている。第２のPWB4の
挿入が完了した後、第１のPWB3をカードガイド15に案内
させて挿入できる。第１のPWB3は分割タイプであり、一
般にヒートシンクを必要としないメモリ系半導体素子の
みが搭載されているため、重量が軽い。そのため、カー
ドガイド15の強度は小さくてもよい。サイドフレーム11
には第１のPWB3のコネクタ６が挿入できる大きさの穴12
が用意されており、この穴２を通過したコネクタ６は第
２のPWB4のコネクタ８と嵌合する。サイドフレーム11に
は第６図に示すように、ころ13に対応して板バネ17が用
意されており、ガイドスチフナ10を下方向へ矯正する役
目を果している。Side bars 14 are arranged on both sides of the first PWB 3 and on the insertion surface side, and a card guide 15 is bridged between the side bar 14 and the side frame 11. After the insertion of the second PWB 4 is completed, the first PWB 3 can be guided by the card guide 15 and inserted. The first PWB 3 is a split type and generally has only a memory type semiconductor element that does not require a heat sink, and thus is light in weight. Therefore, the strength of the card guide 15 may be small. Side frame 11
Has a hole 12 large enough to receive the connector 6 of the first PWB3.
The connector 6 passing through the hole 2 is fitted with the connector 8 of the second PWB 4. As shown in FIG. 6, the side frame 11 is provided with a leaf spring 17 corresponding to the roller 13 and serves to correct the guide stiffener 10 downward.

ところで第２のPWB4のコネクタ７を第３のPWB5のコネ
クタ９に嵌合させた後に、第１のPWB3を挿入すると、コ
ネクタ7,9に横方向のストレスが加わり、コネクタ7,9内
のピンを傷める危険がある。そこで本発明では第２のPW
B4の先端の両脇に第５図に示すカードホルダ35を、他端
の両脇にネジ39を用意した。カードホルダ35はＬ字型の
形状であり一端に凸部を有している。即ち第２のPWB4を
挿入すると先端のガイドスチフナ10がカードホルダ35の
他端を押圧し、支点37を中心に回転して前述の凸部36
が、第２のPWB4の両脇に設けたガイドスチフナ10を両側
面から押圧保持できる。また、第２のPWB4の残りの２角
はネジ39の締結によってサイドフレーム11に固定され
る。By the way, when the first PWB3 is inserted after the connector 7 of the second PWB4 is fitted to the connector 9 of the third PWB5, lateral stress is applied to the connectors 7 and 9, and the pins inside the connectors 7 and 9 are inserted. There is a risk of damaging. Therefore, in the present invention, the second PW
A card holder 35 shown in FIG. 5 was prepared on both sides of the tip of B4, and screws 39 were prepared on both sides of the other end. The card holder 35 is L-shaped and has a convex portion at one end. That is, when the second PWB 4 is inserted, the guide stiffener 10 at the tip presses the other end of the card holder 35 and rotates about a fulcrum 37 to rotate the convex portion 36.
However, the guide stiffeners 10 provided on both sides of the second PWB 4 can be pressed and held from both side surfaces. The remaining two corners of the second PWB 4 are fixed to the side frame 11 by fastening the screws 39.

以上により第１のPWB3の挿入力が直接コネクタ7,9に
加わるのを防止できる。As described above, it is possible to prevent the insertion force of the first PWB 3 from being directly applied to the connectors 7 and 9.

給電構造について第１図、第４図を用いて説明する。 The power feeding structure will be described with reference to FIGS. 1 and 4.

第２のPWB4の長手方向には、給電バスとスチフナを兼
ねた複数個のバススチフナ18,19,20,21が設けられてお
り、導体層とインサート等を介して導通している。さら
に各々のバススチフナ18,19,20,21には給電プレート22
が電気的に接続されている。第４図に示すようにパワー
コネクタ23を給電プレート22へ嵌合させることにより、
第２のPWB4の四隅からの給電が可能になり従来の信号用
コネクタからの給電方式は不要となる。尚、給電プレー
ト22のパワーコネクタ23を接続させる方法としては、前
述した第１のPWB3の案内構造と同じ方法が応用できる。
本実施例ではSG,V1,V2,V3の４系統の給電を実現してい
る。第１のPWB3への給電は、コネクタ８を介して実現さ
れるが、メモリ系半導体素子の消費電力は小さいので、
わずかなピン数で足りる。In the longitudinal direction of the second PWB 4, a plurality of bus stiffeners 18, 19, 20, 21 which also serve as power supply buses and stiffeners are provided, and are electrically connected to the conductor layer via inserts or the like. In addition, the power supply plate 22 is attached to each of the bus stiffeners 18, 19, 20, and 21.
Are electrically connected. By fitting the power connector 23 to the power feeding plate 22 as shown in FIG.
Power can be supplied from the four corners of the second PWB4, and the conventional power supply method from the signal connector is not required. As the method of connecting the power connector 23 of the power feeding plate 22, the same method as the guide structure of the first PWB 3 described above can be applied.
In this embodiment, four systems of SG, V 1 , V 2 and V 3 are provided. The power supply to the first PWB 3 is realized via the connector 8, but since the power consumption of the memory semiconductor device is small,
A few pins are enough.

冷却構造について第１図を用いて説明する。 The cooling structure will be described with reference to FIG.

第２のPWBに搭載させた制御系半導体素子の上部空間
には水冷コールドプレート31が前述したSG用バススチフ
ナ18に固定されている。第２のPWB4を抜く時は、カプラ
32を離してケージ外の水配管系から分離することにより
可能である。第１のPWB3上に搭載されたメモリ系半導体
素子の冷却には送風機34が用意されており、発熱量が小
さいので適度な能力の送風機34を選択できる。A water-cooled cold plate 31 is fixed to the above-mentioned SG bus stiffener 18 in the upper space of the control semiconductor device mounted on the second PWB. When removing the second PWB4, use the coupler
This is possible by separating 32 and separating it from the water piping system outside the cage. An air blower 34 is provided for cooling the memory semiconductor elements mounted on the first PWB 3, and since the heat generation amount is small, the air blower 34 having an appropriate capacity can be selected.

即ち、発熱量が大きい制御系半導体素子の冷却には水
冷方式を、搭載数は多いが発熱量の小さいメモリ系半導
体素子の冷却には空冷方式を容易に採用でき、さらに実
装密度が高い３次元実装ケージ構造の実現が可能であ
る。That is, a water-cooling system can be easily adopted to cool the control system semiconductor elements that generate a large amount of heat, and an air-cooling system can be easily used to cool the memory system semiconductor devices that have a large number of units and a small amount of heat generated. A mounting cage structure can be realized.

［発明の効果］ 以上説明したように本発明は、従来PWB一枚に混在さ
せていた制御系及びメモリ系半導体素子を別々のPWBに
分割して相互接続することにより、又このように相互接
続した電子回路パッケージを３次元実装することによ
り、 PWBを大型にしなくても搭載できる半導体素子の数を
多くできる。[Effects of the Invention] As described above, according to the present invention, the control system and the memory system semiconductor elements, which are conventionally mixed in one PWB, are divided into separate PWBs and are connected to each other. By mounting the electronic circuit package described above in three dimensions, the number of semiconductor elements that can be mounted can be increased without increasing the size of the PWB.

PWBの大型化が不要なので原価的に有利である。It is cost-effective because it does not require a large PWB.

故障率の大きいメモリ系半導体素子を搭載したPWBの
みの交換が可能なので保守面でのメリットが大きい。Since only the PWB equipped with memory-related semiconductor elements with a high failure rate can be replaced, there is a great advantage in terms of maintenance.

それぞれの素子に最適な冷却方式である空冷（メモリ
系）と水冷（制御系）の混在が可能なケージ構造が実現
できる。It is possible to realize a cage structure in which air cooling (memory system) and water cooling (control system), which are the optimal cooling methods for each element, can be mixed.

といった効果があり、 また従来、電源、グランド、信号ピンが混在したコネ
クタから電源、グランドをパワーコネクタに移すことに
より、 コネクタ内に占める信号ピン数を増やすことができ
る。In addition, by moving the power supply and the ground from the connector in which the power supply, the ground, and the signal pin are mixed to the power connector, the number of the signal pins occupied in the connector can be increased.

電源の大容量化が容易である。It is easy to increase the capacity of the power supply.

従来マザーボードに必要とした給電用の機構品や電源
層が不要なため原価面で有利である。It is advantageous in terms of cost because it does not require the power supply mechanism and power supply layer that were required for the conventional motherboard.

さらに、第２のPWBの冷却用に水冷コールドプレート
を第１のPWBの冷却用にファンを設けて水冷部と空冷部
をわけることにより、 各々の半導体素子に適した冷却方式を採用できるた
め、冷却効率、原価、信頼性の点で優れている。Furthermore, by providing a water-cooled cold plate for cooling the second PWB and providing a fan for cooling the first PWB to separate the water-cooling section from the air-cooling section, a cooling method suitable for each semiconductor element can be adopted. Excellent in cooling efficiency, cost, and reliability.

低騒音化を実現しやすい。It is easy to achieve low noise.

また、第２のPWBの両脇にガイドスチフナを、サイド
フレームにころ及び第１のPWBのコネクタ挿入穴を、サ
イドバーとサイドフレーム間にカードガイドを設けるこ
とにより、 重量的に不利な水冷カード、軽量なれどカードガイド
幅に制約がある空冷カード各々に適したカード案内構造
を同時に実現できる。Also, by providing guide stiffeners on both sides of the second PWB, rollers for the side frame and connector insertion holes for the first PWB, and a card guide between the side bar and the side frame, a water-cooled card which is disadvantageous in terms of weight. Although it is lightweight, it is possible to simultaneously realize a card guide structure suitable for each air-cooled card with a limited card guide width.

特に水冷カードの挿入性が容易である。Especially, it is easy to insert the water cooling card.

ガイドスチフナをころとバネで上下から押圧すること
によりカードのがたつきを小さくすることができる。The rattling of the card can be reduced by pressing the guide stiffener from above and below with rollers and springs.

さらに、カード挿入後バックボード側とカード挿入面
側に保持機構を設けることにより、第２のPWBの第２の
コネクタ８と、第１のPWBのコネクタ６を着脱せしめる
際に生じるコネクタ7,9へのストレスを未然に防止でき
る効果がある。Further, by providing a holding mechanism on the backboard side and the card insertion surface side after the card is inserted, the connectors 7, 9 generated when the second connector 8 of the second PWB and the connector 6 of the first PWB are detached and attached. It has the effect of preventing stress from occurring.

又、片面アクセスのため、カード保持のための保守ス
ペースがバックボード側にいらない。Also, because it is accessed on one side, there is no need for maintenance space for holding cards on the backboard side.

【図面の簡単な説明】[Brief description of drawings]

第１図は本発明の実施例の平断面図、第２図は第１図の
Ａ−Ａ断面図、第３図は第１図のＢ−Ｂ断面図、第４図
は第１図のＣ−Ｃ断面図、第５図は第１図のＤ部詳細
図、第６図は第２図のＥ−Ｅ断面図、第７図は従来の実
施例の側断面図である。 1:メモリ系半導体素子 2:制御系半導体素子 3:第１のPWB、4:第２のPWB 5:第３のPWB、6:コネクタ 7:第１のコネクタ、8:第２のコネクタ 9:コネクタ、10:ガイドスチフナ 11:サイドフレーム 12,12′：穴、13:ころ 14:サイドバー、15:カードガイド 16:シャーシ、17:バネ 18:バススチフナ（SG用） 19:バススチフナ（V1用） 20:バススチフナ（V2用） 21:バススチフナ（V3用） 22:給電プレート、23:パワーコネクタ 24:ガイドバス、25:ネジ 26:バス（SG用） 27:バス（V1用） 28:バス（V2用） 29:バス（V3用） 30:バッフル、31:コールドプレート 32:カプラ、33:空気の流れ 34:送風機、35:カードホルダ 36:凸部、37:支点 38:カードホルダの回転方向 39:ネジ、51:ドーターボード 52:マザーボード、53:コネクタ 54:メモリ系半導体素子 55:制御系半導体素子 56:給電バス、57:給電ケーブル 58:インサート、59:カードガイド 60:ケージシャーシ 61:エアストレーナ 62:送風機、63:マフラ 64:電子機器架、65:コネクタ 66:信号ケーブル1 is a plan sectional view of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA of FIG. 1, FIG. 3 is a sectional view taken along the line BB of FIG. 1, and FIG. 4 is a sectional view of FIG. C-C sectional view, FIG. 5 is a detailed view of section D in FIG. 1, FIG. 6 is a sectional view taken along line EE in FIG. 2, and FIG. 7 is a side sectional view of a conventional embodiment. 1: Memory semiconductor element 2: Control semiconductor element 3: First PWB, 4: Second PWB 5: Third PWB, 6: Connector 7: First connector, 8: Second connector 9: connector, 10: Gaidosuchifuna 11: side frame 12, 12 ': hole, 13: roller 14: sidebar, 15: card guides 16: chassis, 17: spring 18: Basusuchifuna (for SG) 19: Basusuchifuna (V for 1 ) 20: Basusuchifuna (for V 2) 21: Basusuchifuna (for V 3) 22: power supply plate 23: power connector 24: guide bus, 25: screw 26: bus (for SG) 27: bus (for V 1) 28 : Bus (for V 2 ) 29: Bus (for V 3 ) 30: Baffle, 31: Cold plate 32: Coupler, 33: Air flow 34: Blower, 35: Card holder 36: Convex part, 37: Support point 38: Card holder rotation direction 39: Screw, 51: Daughter board 52: Motherboard, 53: Connector 54: Memory semiconductor element 55: Control semiconductor element 56: Power supply bus, 57: Power supply cable 58: In Over DOO, 59: card guide 60: cage chassis 61: Air strainer 62: blower, 63: muffler 64: electronic equipment rack, 65: Connector 66: Signal cable

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】同一平面で一列に複数配され、かつ列方向
に沿う一側面にコネクタを有するメモリ系半導体素子を
搭載した第１のプリント配線板と、制御系半導体素子が
搭載され、一辺に第１のコネクタを有し、該辺に隣り合
う少なくとも一方の辺に前記第１のプリント配線板のコ
ネクタ群に嵌合する複数個の第２のコネクタを有する第
２のプリント配線板とから構成される電子回路パッケー
ジを、第３のプリント配線板の一面に複数列設したコネ
クタに前記第２のプリント配線板の第１のコネクタを嵌
合することによって、水平に多段実装する電子回路のパ
ッケージのケージ構造において、 前記第２のプリント配線板の第２のコネクタを有する側
の向かい合う二辺に設けた一対のガイドスチフナと、 前記第２のプリント配線板の両脇に配置され、前記第１
のプリント配線板のコネクタ部分が挿入可能な複数個の
穴と、前記ガイドスチフナの下面に係合して前記第２の
プリント配線板を案内挿入する複数個のころを有する一
対のサイドフレームと、 前記第１のプリント配線板の挿入面側に配置された複数
個のサイドバーと、 前記サイドフレームと前記サイドバーに両端が保持され
前記第１のプリント配線板の二辺に係合して案内挿入す
るカードガイドと、 前記第３のプリント配線板と、前記一対のサイドフレー
ムと、前記複数個のサイドバーを保持するシャーシを含
むことを特徴とする電子回路のパッケージのケージ構
造。1. A first printed wiring board, on which a plurality of memory-based semiconductor elements having a connector are mounted on one side, which are arranged in a line on the same plane and along the column direction, and a control-type semiconductor element are mounted, and on one side thereof. A second printed wiring board having a first connector and a plurality of second connectors fitted to the connector group of the first printed wiring board on at least one side adjacent to the first connector An electronic circuit package in which the electronic circuit package is horizontally mounted in multiple stages by fitting the first connector of the second printed wiring board into a connector provided in a plurality of rows on one surface of the third printed wiring board. And a pair of guide stiffeners provided on two opposite sides of the second printed wiring board on the side having the second connector, and arranged on both sides of the second printed wiring board. It is the first
A plurality of holes into which connector parts of the printed wiring board can be inserted, and a pair of side frames having a plurality of rollers that engage with the lower surface of the guide stiffener to guide and insert the second printed wiring board. A plurality of side bars arranged on the insertion surface side of the first printed wiring board, both ends of which are held by the side frame and the side bar, and are engaged with two sides of the first printed wiring board for guiding. A cage structure for an electronic circuit package, comprising: a card guide to be inserted; the third printed wiring board; the pair of side frames; and a chassis holding the plurality of side bars. 【請求項２】一端が凸部を有するＬ字型部材であって、
他端が前記第２のプリント配線板に設けたガイドスチフ
ナの先端に押圧された後、前記凸部を有する一端が前記
ガイドスチフナの側面を押圧保持するように、中央部に
設けた支点が回転自在に前記サイドフレームに保持され
た複数対のカードホルダと、 前記ガイドスチフナのもう一方の端部を前記シャーシに
固定する手段とを有することを特徴とする請求項１記載
の電子回路パッケージのケージ構造。2. An L-shaped member having a convex portion at one end,
After the other end is pressed by the tip of the guide stiffener provided on the second printed wiring board, the fulcrum provided at the center rotates so that the one end having the convex portion presses and holds the side surface of the guide stiffener. The cage of an electronic circuit package according to claim 1, further comprising a plurality of pairs of card holders freely held by the side frame, and means for fixing the other end of the guide stiffener to the chassis. Construction.
JP1017184A 1989-01-26 1989-01-26 Electronic circuit package cage structure Expired - Lifetime JP2526654B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1017184A JP2526654B2 (en) 1989-01-26 1989-01-26 Electronic circuit package cage structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1017184A JP2526654B2 (en) 1989-01-26 1989-01-26 Electronic circuit package cage structure

Publications (2)

Publication Number Publication Date
JPH02197194A JPH02197194A (en) 1990-08-03
JP2526654B2 true JP2526654B2 (en) 1996-08-21

Family

ID=11936859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1017184A Expired - Lifetime JP2526654B2 (en) 1989-01-26 1989-01-26 Electronic circuit package cage structure

Country Status (1)

Country Link
JP (1) JP2526654B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4630885B2 (en) * 2007-05-01 2011-02-09 富士通株式会社 Information processing device
CN106982535B (en) * 2016-01-15 2019-11-15 中兴通讯股份有限公司 The positive and negative exhausting air duct panel of veneer mends wind method and device
CN117135823A (en) * 2022-05-20 2023-11-28 华为技术有限公司 Packaging structure, packaging method and electronic equipment

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197891U (en) * 1984-12-04 1986-06-23
JPH0821787B2 (en) * 1987-05-22 1996-03-04 株式会社日立製作所 Information processing device mounting structure

Also Published As

Publication number Publication date
JPH02197194A (en) 1990-08-03

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