JP2526542B2 - Information processing device - Google Patents

Description

The present invention relates to an information processing apparatus suitable for use as, for example, video image processing.

[Outline of Invention]

According to the present invention, a signal indicating that processing has been completed is sent from the data processing unit to the input / output unit, and a processing start timing signal is sent from the input / output unit to the data processing unit so that the input / output unit and the data processing unit can receive the signal. By communicating, the data processing unit can continuously perform processing in which the required time is not constant.

[Conventional technology]

Various video image processing systems have been proposed (for example, IEICE Transactions 85/4 Vol.J68-DNo4, JP-A-58-2).
15813). FIG. 6 shows an example of this video image processing apparatus.

That is, this is the input / output unit (1) as shown in FIG.
A memory unit (2) including an input image memory (2A) and an output image memory (2B), and a data processing unit (3).

The input / output unit (1), for example, A / D-converts the video signal from the video camera (4) into digital image data, writes this in the input image memory (2A), and outputs it from the output image memory (2B). Read the processed image data, convert it to D / A and return to analog video signal, record it on VTR (5) or supply it to monitor receiver (6) so that video image can be monitored. To

The data processing unit (3) reads the image data stored in the input image memory (2), applies various processing to the image data, and writes the processed data in the output image memory (2B).

Writing and reading to and from the memory unit (2) are performed in units of an image, that is, in units of one field or one frame. Therefore, input image memory (2A) and (2B)
Each has a plurality of memories each having a capacity of one field or one frame of image data.

Here, a group of images (field or frame)
The data processing unit (3) must process the data at the timing of the start of the processing, but the processing start timing is managed by the input / output unit (1) having the start information of the field or frame of the video signal. In FIG. 6, the signal ST is the processing start timing signal.

[Problems to be solved by the invention]

By the way, if the content of the processing performed by the data processing unit (3) is relatively simple and is completed within the time of one field or one frame, the start information of one field or one frame of the video signal is directly used as the processing start timing signal. Can be used.

However, depending on the processing content of the data processing unit (3), the processing time may exceed one field or one frame, and when the processing time changes depending on the content of the input image, Since it is not known whether the process currently being performed will end, it is difficult to give an instruction to start the next process. After all, in such a case, conventionally, in such a case, a method of sending a processing start timing signal with a sufficiently long interval to the processing unit (3) or generating a processing start timing signal with human intervention is used. However, in any case, there is a drawback that the processing time efficiency is poor and it is not suitable for high speed processing.

In view of this point, the present invention is to propose an information processing apparatus that can efficiently perform image processing in frame units even when the processing time required for image processing in frame units changes. .

[Means for solving problems]

According to the present invention, there is provided an input / output unit (10), a memory unit (20), and a data processing unit (30A, 30B), and the input / output unit (10) and the data processing are performed via the memory unit (20). Division (30A,
30B) is an information processing device that transmits and receives image data to and from the data processing unit (30A, 30B) and performs signal processing on the image data by the data processing unit (30A, 30B). ) Supplies a signal indicating the end of processing to the input / output unit (10) each time image processing in units of frames is completed, and the input / output unit (10), after the signal indicating the end of processing is supplied,
The processing start signal is supplied to the data processing unit (30A, 30B) at the timing when the pulse of the pulse signal of the frame cycle first occurs, and the data processing unit (30A, 30B) performs the signal processing operation in response to the processing start signal. It is designed to start.

[Action]

According to the present invention, the data processing unit (30A, 30B) supplies a signal indicating the end of processing to the input / output unit (10) each time image processing in frame units is completed, and the input / output unit (10) After the signal indicating the end of processing is supplied, the processing start signal is supplied to the data processing unit (30A, 30B) at the timing when the pulse of the pulse signal of the frame cycle occurs for the first time, and the data processing unit (30A, 30B) The signal processing operation is started in response to the processing start signal.

〔Example〕

FIG. 1 shows an embodiment in which the device of the present invention is applied to video image processing, and this example realizes higher speed of data processing.

That is, in this example, the data processing unit is a processor system that mainly calculates pixel values (hereinafter referred to as PIP) (30A) and a processor system that manages data flow management such as address management and processing timing ( Hereinafter referred to as PVP)
(30B) and divide.

In the conventional data processing unit, the processing time that is the sum of the processing times of both is required, whereas if divided in this way, the processing time of the larger one will be sufficient (Japanese Patent Laid-Open No. 58-215813). See the bulletin). Therefore, in the case of this example, high-speed processing that enables video data processing to be performed in real time can be performed.

Further, in the figure, (10) is an input / output unit (hereinafter referred to as IOC), (20) is a memory unit (hereinafter referred to as VIM), which is an input image memory (VIMIN) (20A) and an output image memory (VIA).
MOUT) (20B). Reference numeral (40) is a processor (hereinafter referred to as TC) that controls execution and stop of processing.

The IOC (10) A / D-converts the video signal from the video camera or VTR, writes it as an image image in the input image memory (20A), and outputs the processed image from the output image memory (20B) as described above. Read, D / A convert, and output to a monitor.

In this case, the signal that can be input / output to / from this IOC (10) is NTSC.
It is a video signal in the system or R, G, B system, and the system is designated by TC (40). Further, one pixel is, for example, 8-bit data.

VIM (20) has multiple frame memories, eg 12 7
It consists of a frame memory of 65 x 512 bytes.
In the case of this example, the usage of these 12 frame memories is not fixed, and the input image memory (20A) and the output image memory (20B) are freely assigned according to the processing purpose or the image to be processed. Has been made possible. Also, the memories are used as a set of two, and when one is in the write state, the other can be read from, and the IOC (10) processes the VIM (20) from the outside and the PIP (30A). Also, the processing inside the VIM (20) by the PVP (30B) can be performed in parallel. In this case, the control mode signal indicating whether the frame memories of this VIM (20) are controlled by IOC (10) or PVP (30B) is controlled by IOC (10). Occurred and supplied to VIM (20).

The PIP (30A) and PVP (30B) are basically the same architecture, and are independent processors consisting of a control unit, an arithmetic unit, a memory unit, and an input / output port, each of which has a multiprocessor configuration including a plurality of unit processors, Higher processing speed is mainly achieved by the parallel processing method.

The PIP (30A) has, for example, 60 PIP processors and several sub processors, and processes image data from the VIM (20) or internally generates image data. This PIP (30A)
The clock of is supplied from TC (40).

PVP (30B) has about 30 processors and VIM (2B
Controls the flow of image data inside the VIM (20) such as the allocation and collection of pixel data from 0) to the PIP (30A).

That is, the PVP (30B) generates the address data and control signal to the VIM (20), and outputs these to the VIM (2
0), generate PIP (30A) input / output control signals and other control signals, and supply these to PI.
Supply to P (30A).

The input image memory (20
Not only when processing only the data from one frame in (A) and writing the processed data to the output image memory (20B), but using data that spans multiple frames from multiple frame memories. It may also be processed.

The number of calculation digits is 16 bits as standard in PIP (30A) and PVP (30B), and the calculation processing of image data processing is possible within 1 frame of image data, that is, processing speed capable of real-time processing is possible. It is said that However, there are some processes that require a processing time of one frame or more.

In this case, the image data processing by PIP (30A) and PIP (30B) is performed in synchronization with the frame. For this reason, PVP
The processing start timing signal PS synchronized with the frame is supplied to the (30B) from the IOC (10). This signal PS is normally at high level, and becomes low level at the processing start timing. On the other hand, from the PVP (30B), a signal OK indicating that one process is completed is supplied to the IOC (10). This signal OK is P
This is output when processing is completed from the core processor of this PVP (30B), which controls timing of the processing system among the processors of VP (30B).

That is, FIG. 2 is a flow chart of a program as an example of means for outputting the signal OK from the processor. In step [101], it is programmed that the processing start timing signal PS from the IOC (10) becomes low level. To detect. Then, when it is detected that the signal PS has become low level, this processor runs and issues a timing signal to the other processors by the program, and the VIM
The address is supplied to (20), the image data from the VIM (20) is read, and the processing is performed by the PIP (30A) (step [102]). Then, when the processing is completed, a signal OK is output and the processing is stopped (step [103]), and the next processing start timing signal PS is provided (step [101]).

The signal PS is generated at the IOC (10) as follows.

 The IOC (10) is configured as shown in FIG. 3, for example.

That is, (11) is a PLL circuit for clock formation, from which a clock locked to the phase of, for example, a subcarrier of an input video signal is obtained.

Reference numeral (12) is an interface, which divides and partially delays the clock from the PLL circuit (11) and supplies it to each part in the IOC (10) and VIMIN (20A) and VIMOUT (20B).

Reference numeral (13) is an A / D converter which converts an input video signal into digital image data of, for example, 1 sample of 8 bits by using a sampling clock (for example, 14.32 MHz) from the interface (12).

(14) is an input circuit to which digital image data from the A / D converter (13) is supplied, and from this, VIMIN (2
0A) and written.

In this case, the input circuit (14) has a system (NT
SC or R, G, B) designation signals are supplied. And NTSC
If it is a signal, there are two input image memories (or two
More than one frame memory is used to alternately write data. In the case of R, G, B3 primary color signals, 6 frame memories out of 12 frame memories are used as input image memories, and one primary color signal is alternately written into two frame memories. It is read from the frame memory that does not exist.

Then, as described above, the image data stored in the memory is separated from the IOC (10) and the flow is controlled by the PVP (30B).

In this case, only the valid signal from which the sync signal and the burst signal portion have been removed is supplied to the VIMIN (20A) from the input circuit (14) and written every one frame according to the clock from the interface (12).

Further, in this input circuit (14), the burst signal in the video signal and the clock are compared in phase, and the comparison output is supplied to the PLL circuit (11) as a phase control amount, and this PLL is supplied.
The clock from the circuit (11) is phase locked to the subcarrier in the video signal.

Further, in this input circuit (14), a signal for extracting the burst signal portion, a valid / invalid signal indicating whether the synchronizing signal or the burst signal portion is an image signal portion, a frame start signal FL indicating the first line of each frame, and each field A video ID signal including a vertical blanking signal, a signal indicating the beginning of a line, etc. is generated and used in this input circuit (14) and also supplied to an output circuit (15) described later.

Reference numeral (15) is an output circuit, and the processed video tape is read from the VIMOUT (20B) in units of one frame and supplied to the output circuit (15).

The read data does not include the burst signal as the synchronization signal. Therefore, in this output circuit (15), RO that generates the synchronization signal, burst signal, and vertical blanking signal.
It has a built-in M and sends the data from VIMOUT (20B) to the D / A converter (16) together with these sync signal, burst signal and vertical blanking signal in the case of NTSC signal.

Further, even in the case of the three primary color signals, an external synchronization signal is necessary, and this is also generated by this circuit (15) and supplied to a monitor or the like.

The output circuit (15) also forms a signal for controlling the VIM (20). That is, VIM (20) is I
A dominant mode signal indicating whether the mode is dominated by OC (10) or PVP (30B) is formed, and VIM (2
0). The VIM (20) has multiple frame memories, but only the memory that takes in the input data or reads the output data by this dominant mode signal
Being under the control of the IOC (10). The timing of switching the dominant mode signal is determined based on the signal OK.

The output circuit (15) also generates an address signal to the VIM (20) and a write enable signal for controlling writing and reading, and sends the write enable signal to the memory controlled by the IOC (10) of the VIM (20). The memory controlled by PVP (30B) is supplied with the address and other control signals from this PVP (30B).

Further, the output circuit (15) outputs the processing start timing signal PS to the frame start signal FL from the input circuit (14).
And a processing end signal OK from the PVP (30B).

That is, FIG. 4 shows an example of a means for generating the signal PS, in which the frame start signal FL is 1 at the beginning of each frame.
This signal is a low level signal for the clock period (FIG. 5A). This frame start signal FL is a delay circuit (21)
After being delayed by one clock period at, the signal is supplied to the clear terminal of the D-type flip-flop (22). On the other hand, the signal OK (FIG. 5B), which is at a high level for one clock period after the processing is completed, is supplied to the clock terminal of the D-type flip-flop (22).

The D input of this flip-flop (22) is always at high level.

Therefore, until the signal OK arrives, this flip-flop (22) is always cleared by the frame start signal FL, and its output DF (FIG. 5C) remains high level.

Then, when the signal OK arrives, the output DF of this flip-flop (22) becomes low level.

This output DF is supplied to the OR gate (23). Also,
A frame start signal FL is supplied to the OR gate (23). The output of this OR gate (23) is the signal PS (5th
In FIG. D), when the frame start signal FL arrives while the output DF is at the low level, the output PS becomes the low level for the low level period of the signal FL.

Thus, the processing start timing signal PS synchronized with the frame is obtained only when the signal OK is obtained.

When processing is performed in real time, the signal OK is always obtained at the end of each frame, so the signal PS becomes the same signal as the frame start signal FL.

On the other hand, if the processing time is longer than 1 frame,
PS is not the frame period and is obtained at the beginning of the next frame when the signal OK is output.

Note that the above is a case where all data processing is automatically performed without human intervention, and a case where the next frame at the time when the previous processing is finished is automatically captured and processed.
A manual switch etc. is provided so that the user can process the data of the desired frame, and when the frame to be processed is designated, the signal PS is gated in the designated frame, The signal PS is made available only at the beginning of the designated frame.

〔The invention's effect〕

According to the present invention, it has an input / output unit, a memory unit, and a data processing unit, and transmits / receives image data in frame units between the input / output unit and the data processing unit via the memory unit. An information processing apparatus configured to perform signal processing on image data in a unit, wherein the data processing unit supplies a signal indicating completion of processing to the input / output unit each time image processing in frame units is completed, and The output unit supplies the processing start signal to the data processing unit at the timing when the pulse of the pulse signal of the frame cycle first occurs after the signal indicating the processing end, and the data processing unit responds to the processing start signal. Since the signal processing operation is started by the above, it is not necessary to fixedly determine the start timing of the image processing in frame units with a margin of processing time. Even if the time is changed,
Image processing can be efficiently performed in frame units.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of the device of the present invention, FIG. 2 is a flowchart of the operation of a partial circuit thereof, FIG. 3 is a diagram showing the configuration of an example of a partial circuit thereof, and FIG. FIG. 5 is a timing chart for explaining FIG. 4, and FIG. 6 is a block diagram of an example of a video image processing apparatus. (10) is an input / output unit, (20A) and (20B) are input and output image memories, and (30A) and (30B) are processors for data processing.

Claims (1)

(57) [Claims] 1. An input / output unit, a memory unit, and a data processing unit. Image data is transmitted and received in frame units between the input / output unit and the data processing unit via the memory unit.
An information processing apparatus configured to perform signal processing on the image data in the data processing unit, wherein the data processing unit causes the input / output unit to end processing each time the image processing in frame units is completed. The signal indicating that the input / output unit supplies the processing start signal to the data processing unit at the timing when the pulse of the pulse signal of the frame period first occurs after the signal indicating the end of the processing is supplied, An information processing apparatus, wherein the data processing section is adapted to start the signal processing operation in response to the processing start signal.