JP2508223B2 - MOS type read-only semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS semiconductor memory device, and in particular, data writing is performed by implanting an impurity of a conductivity type different from that of a semiconductor substrate from directly above a gate electrode. The present invention relates to a MOS type read-only semiconductor memory device.

[Prior Art] Among read-only semiconductor memory devices, there is a product group called a mask ROM that masks data obtained from a user and writes the data in the LSI manufacturing process. In this mask ROM, TAT (Turn Around Ti
One of the important issues is the shortening of (me), but in order to achieve that goal, the latest mask ROM manufacturing method tries to shift the writing of ROM data to the later steps of the manufacturing process as much as possible. There is. ROMs that follow this trend
The data writing process is set after the gate electrode is formed,
Ion implantation for writing ROM data is performed by passing through the gate electrode of the selected transistor and depleting the transistor.

This method will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view of a memory element array portion, FIG. 4 (a) is taken along the line AA ′ in FIG. 3, and FIG. 4 (b) is taken along the line B- in FIG. It is sectional drawing of a B'line. As shown in FIG. 3, the gate electrode 405 extends in the horizontal direction at regular intervals, and the element isolation region (field oxide film region) 403 passes in the vertical direction. Then, as shown in FIGS. 4A and 4B, the gate electrode is formed on the P-type semiconductor substrate 401 via the gate insulating film 404.
405 is formed, and on both sides of the gate electrode,
The N-type source / drain diffusion layer 411 is formed, and the enhancement-type MOS transistor is already formed over the entire storage element array region. Each element isolation region 4
A channel stopper region 402 is formed under 03.

Here, the element isolation region 403 is formed by a normal LOCOS oxidation method, and the film thickness of the element isolation region is 500 nm.
~ 700 nm. In addition, the channel stopper region 402 has an impurity concentration that is twice or more higher than that in the case of preventing the so-called parasitic MOS transistor effect in the related art (for example, the concentration of boron is 1.0 × 10 ¹⁷ cm ^{−3 to} 1.0 × 10 ¹⁸ cm ^−3. ) P-type conductivity type region.

Data is written in this semiconductor memory device as follows. A photoresist 406 is applied on the semiconductor substrate 401, the resist in the area where data is written is removed, and the data writing windows 407 and 408 are opened. Then, N
Conductive impurities such as phosphorus (P) are ion-implanted under the N-type source / drain diffusion layer 411 and the gate electrode 405, and the ROM data write layers 409 and 410 are formed there. Therefore, the transistor at the ion-implanted portion is depleted.

[Problems to be Solved by the Invention] The channel stopper region 402 is a region in which impurities are added at a high concentration. The reason for making this region a high impurity concentration in this way is when data is written. In addition, this is to prevent the adjacent ROM data writing layers 409 and 410 from being short-circuited. However, in the conventional device, even if the high-concentration channel stopper region 402 is provided, the ROM
An electrical short circuit or a leak accident was likely to occur between the data writing layers 409 and 410. This is because the impurities for writing ROM data usually have enough energy to pass through the gate electrode 405 having a film thickness of 400 nm to 600 nm, so that the gate electrode 405 does not exist B- in FIG.
In the region along the line B ', the element isolation region (field oxide film region, usually a film thickness of 500 nm to 700 nm) is transmitted, and as shown in FIG. 4 (b), the ROM data writing layer (N-type impurity layer) is formed. This is because 409 and 410 are formed immediately below the element isolation region.

Even if the short-circuit accident does not occur, if the high-concentration channel stopper region 402 is present,
The ROM data writing layers (source / drain regions) 409 and 410 formed deeply come into contact with each other, and a large junction capacitance is provided therebetween, which causes deterioration of device characteristics.

[Means for Solving the Problems] A read-only semiconductor memory device of the present invention is composed of a plurality of MOS transistors arranged in a matrix separated by element isolation regions, and is selected from the plurality of MOS transistors. ROM data is written by ion-implanting an impurity of a conductivity type different from the conductivity type of the substrate under the gate electrode of the formed MOS transistor,
The thickness of the element isolation region or the sum of the thickness of the element isolation region and the thickness of the sidewall spacer formed on the element isolation region and covering the side surface of the gate electrode is sufficiently thicker than the thickness of the gate electrode. .

Example Next, an example of the present invention will be described with reference to the drawings.

FIGS. 1 (a) and 1 (b) show an embodiment of the present invention, which are taken along the lines AA 'and BB' in FIG. 3, respectively.
It is sectional drawing in a line. In FIG. 1, those corresponding to the parts of the conventional example in FIG. 4 are given common numbers in the last two digits, so duplicate description will be omitted.
In this embodiment, the element isolation region 103 is of a trench type, and the depth of the trench, that is, the thickness of the element isolation region is made sufficiently thicker than that of the gate electrode 105.

When writing ROM data to this semiconductor memory device, a photoresist 106 in which ROM data writing windows 107 and 108 are formed is provided on a semiconductor substrate, and using this as a mask, N conductivity type impurities are ion-implanted. Since this ion implantation is performed with an acceleration energy that allows the ions to pass through the gate electrode 105, a deep ROM data writing layer 109 is formed in the semiconductor substrate in which the gate electrode 105 does not exist, as shown in FIG. , 110 are formed. But this RO
Since the depths of the M data writing layers 109 and 110 are almost the same as or slightly larger than the film thickness of the gate electrode 105, the film thickness of the element isolation region 103 is the same as that of the gate electrode 105 as in the present embodiment. If it is sufficiently thicker than the film thickness, the bottom surface of the element isolation region 103 is the ROM data writing layer (N-type impurity layer) 109,
It will be deeper than the bottom of 110. Therefore, in the present invention, the inconvenience such as an electrical short circuit or a leak between the ROM data writing layers, which has been a problem in the conventional example, does not occur. Furthermore, in the present invention, unlike the conventional example, a high-concentration channel stopper region is not necessarily required, and even if a channel stopper is provided, it does not contact the ROM data writing layer, so that the junction capacitance Does not cause deterioration of device characteristics.

Next, another embodiment of the present invention will be described with reference to FIG. 2 (a), (b) and (c) show lines AA ', BB' and C- in FIG. 3, respectively.
It is a C'line sectional view. Further, FIG. 2D is a cross-sectional view of the ROM transistor of this embodiment showing a state before writing ROM data. And in these figures, the first
The parts corresponding to those in the figure are numbered in common with the last two digits.

In this embodiment, the gate electrode is made of polycide in order to reduce the resistance of the gate electrode and enable high-speed reading of data. In this case, the thickness of the gate electrode is 600 nm
~ 800 nm (polycrystalline silicon layer is 300 nm to 400 nm, silicide layer is 300 nm to 400 nm), but it is necessary to use a trench depth to form a sufficiently thick element isolation region with a trench for this thick film gate electrode. It is necessary to form a trench of about 1000 nm to 2000 nm. However, the trench isolation method is
Since the manufacturing process is more complicated than the LOCOS oxidation method, it is advantageous in terms of manufacturing method not to use such a deep groove, especially when such a deep groove is formed. Therefore, in this embodiment, LOCO
In addition to using the S oxidation method, the sidewall spacers used when manufacturing the LDD structure MOS transistor are also used as masks during ion implantation, thereby simplifying the manufacturing method while maintaining a sufficient thickness. I'm getting a mask.

The MOS transistor before writing ROM data used in this embodiment has the structure shown in FIG.
That is, a gate electrode 205 composed of a polycrystalline silicon layer 213 and a silicide layer 214 is formed on a P-type semiconductor substrate 201 via a gate insulating film 204, and a sidewall. An oxide film 215 that serves as a spacer is formed. Further, in the semiconductor substrate 201, a low concentration N type diffusion layer 212 is formed in addition to the N type source / drain regions 211. Thus, in this type of read-only semiconductor memory device, the distance between the gate electrodes is extremely narrow, and the portion of the element isolation region 203 using the LOCOS method is higher than the other portions. , In this part,
As shown in FIG. 2C, the oxide film 215 forming the sidewall spacer remains so as to fill the gap between the gate electrodes 205.

In the memory device of this embodiment, when the ion implantation is performed with an acceleration energy that is high enough to pass through the gate electrode 205, the gate electrode 205 is formed in the element region as shown in FIGS. 2 (a) and 2 (b). Underneath, under the oxide film 215, RO
M data writing layers 209 and 210 are formed. However, as shown in FIG. 2B, since the oxide film 215 exists on the element isolation region 203, the ROM data writing impurities cannot be transmitted directly below the element isolation region 203. Absent.

[Effects of the Invention] As described above, the present invention provides a film thickness of an element isolation region for isolating a memory element or an element isolation region, and a sidewall spacer formed on the element isolation region and covering a side surface of a gate electrode. Since the sum of the film thicknesses of the above is made thicker than the film thickness of the gate electrode constituting the memory element, according to the present invention, the impurity of the conductivity type opposite to the conductivity type of the semiconductor substrate is ion-implanted directly above the gate electrode. As a result, even if data is written, a short circuit or a leak does not occur between adjacent transistors.

Further, since the channel stopper under the element isolation region can be removed, or even if the channel stopper is provided, the channel stopper and the ROM data writing layer do not come into contact with each other, so that the characteristic deterioration can be prevented. .

[Brief description of drawings]

FIG. 3 is a plan view of the memory element array, FIG. 1 (a),
(B) shows the first embodiment of the present invention, and is a sectional view taken along the line AA 'and BB' in FIG. 3, and FIGS. 2 (a), (b) and (c), respectively. 2) shows a second embodiment of the present invention, and is respectively the line AA ', the line BB' in FIG.
A sectional view taken along the line CC ', FIG. 2 (d) is a sectional view of the MOS transistor in the second embodiment, and FIG. 4 (a), (b).
Are conventional examples, and are respectively AA ′ in FIG.
FIG. 6 is a sectional view taken along the line BB ′ of FIG. 101, 201, 401 ... P-type semiconductor substrate, 402 ... Channel stopper region, 103, 203, 403 ... Element isolation region, 104, 20
4, 404 ... Gate insulating film, 105, 205, 405 ... Gate electrode, 106, 206, 406 ... Photoresist, 107, 108, 20
7, 208, 407, 408 ... ROM data writing window, 109, 11
0,209,210,409,410 ... ROM data writing layer, 11
1, 211, 411 ... N-type source / drain diffusion layer, 212 ...
Low-concentration N-type diffusion layer, 213 ... Polycrystalline silicon layer, 214 ...
Silicide layer, 215 ... Oxide film.

Claims (1)

(57) [Claims] 1. A transistor comprising a plurality of MOS transistors which are separated by an element isolation region and are arranged in a matrix, and a transistor selected from the plurality of MOS transistors is of a conductivity type of a substrate from above the gate electrode thereof. In a MOS-type read-only semiconductor memory device in which impurities of different conductivity types are ion-implanted to write data to the transistor, a side wall spacer that covers the side surface of the gate electrode is provided between adjacent gate electrodes on the element isolation region. A MOS type read-only semiconductor memory device, characterized in that the sum of the thickness of the sidewall spacers and the thickness of the element isolation region is thicker than the thickness of the gate electrode.