JP2506151B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2506151B2 JP2506151B2 JP63149050A JP14905088A JP2506151B2 JP 2506151 B2 JP2506151 B2 JP 2506151B2 JP 63149050 A JP63149050 A JP 63149050A JP 14905088 A JP14905088 A JP 14905088A JP 2506151 B2 JP2506151 B2 JP 2506151B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- etching
- semiconductor device
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- ing And Chemical Polishing (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】 ＜産業上の利用分野＞ 本発明は、半導体装置のゲーム金属，配線金属若しく
はオーミック金属として用いられる高融点金属を主成分
とする多層構造の金属膜の加工方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for processing a metal film having a multi-layered structure containing a refractory metal used as a game metal, a wiring metal or an ohmic metal of a semiconductor device as a main component.
＜従来の技術＞ 近年、高融点金属の半導体装置への適用が目立ってき
ている。特に、ゲート金属，配線金属，並びにオーミッ
ク金属を対象とした適用の実用化が著しい。<Prior Art> In recent years, the application of refractory metals to semiconductor devices has become conspicuous. In particular, the application of gate metal, wiring metal, and ohmic metal has been remarkably put into practical use.
高融点金属が半導体プロセスの舞台へ登場する契機と
なったのは、SiLSI分野ではゲート配線の低抵抗化要求
であり、化合物半導体分野ではセルファラインプロセス
の導入によるソース抵抗の低減要求であった。このよう
にどちらの分野の場合も、ゲート配線への高融点金属の
適用から始まった。また、ゲート構造としては、それぞ
れWSi/多結晶Si,W/WSiの２層構造が一般的になってい
る。In the field of SiLSI, there was a demand for lower resistance of gate wiring, and in the field of compound semiconductor, there was a demand for reduction of source resistance by introducing self-alignment process. Thus, in both fields, it started with the application of refractory metals to the gate wiring. As the gate structure, a two-layer structure of WSi / polycrystalline Si, W / WSi is generally used.
オーミック電極についても、Si分野では、Siの析出に
伴なうコンタクト抵抗の増大を解決する１つの方法とし
てTiN/TiSi2によるバイアメタル技術の検討が進められ
ており、化合物の分野でも耐熱性電極の要求に伴ない、
Ｗ系金属膜の検討が行なわれている。As for ohmic electrodes, in the field of Si, the study of via metal technology using TiN / TiSi 2 is under way as one method to solve the increase in contact resistance due to the precipitation of Si. With the request of
A W-based metal film is being studied.
このように高融点金属膜の導入が急速に図られてい
る。導入状況を見ると、プロセス上の必要性やデバイス
特性の向上の為に、高融点金属膜やそれら金属のシリサ
イドやナイトライド膜を多層化をしたものが目立つ。例
えば第３図のような高融点金属のシリサイド膜10上に高
融点金属のシリサイド膜よりも抵抗の低い高融点金属膜
11を積層した２層構造が、高耐熱性と低抵抗の特徴を有
するゲート電極として提案されている（参考：特願昭58
−35342号）。In this way, the introduction of the refractory metal film is being rapidly pursued. Looking at the state of introduction, it is conspicuous that the refractory metal film and the silicide or nitride film of those metals are multi-layered in order to improve the process requirements and device characteristics. For example, a refractory metal film having a lower resistance than the refractory metal silicide film on the refractory metal silicide film 10 as shown in FIG.
A two-layer structure in which 11 layers are stacked has been proposed as a gate electrode having high heat resistance and low resistance (reference: Japanese Patent Application No. 58).
-35342).
このような多層膜のドライ加工を行なう場合問題とな
っているのが、加工断面形状の制御に関するものであ
る。第３図は、W/WSiX（ｘ＝0.5）の２層構造膜を従来
方法を用いて加工したときの断面形状を示したものであ
る。Ｗ系金属のRIE加工には、一般にエッチングガスと
してCF4＋O2が用いられてきたが、このような加工方法
ではＷ膜とWSiX膜とではエッチング速度の差が大きくな
ってしまう。第４図は、WSiXのSi組成比とエッチング速
度との関係を示したものでありSi組成比ｘが増すにつ
れ、WSiXのエッチング速度は遅くなる。エッチング速度
の異なる膜から成る２層膜をRIEすると、上層Ｗ膜11の
横方向エッチングが進行し、第３図に示すようにＷ層11
がオーバーエッチ状態の断面形状となる。A problem in performing dry processing of such a multilayer film relates to control of a processed cross-sectional shape. FIG. 3 shows the cross-sectional shape of a W / WSi X (x = 0.5) two-layer structure film processed by a conventional method. CF 4 + O 2 has been generally used as an etching gas for RIE processing of W-based metals, but such a processing method causes a large difference in etching rate between the W film and the WSi X film. Figure 4 is, as it shows the relationship between the Si composition ratio of WSi X and etching rate Si composition ratio x increases, the etching rate of WSi X is slower. When RIE is performed on a two-layer film composed of films having different etching rates, lateral etching of the upper W film 11 proceeds, and as shown in FIG.
Shows a cross-sectional shape in an over-etched state.
このように、高融点系多層構造金属膜が半導体製造プ
ロセスに導入されてきている今日、パターン転写精度の
高い加工技術を確立することが必要とされている。As described above, with the high melting point multi-layered metal film being introduced into the semiconductor manufacturing process, it is necessary to establish a processing technique with high pattern transfer accuracy.
＜発明が解決しようとする課題＞ 従来から利用されてきたCF4＋O2ガスを用いたRIE加工
技術の場合、第５図にも示したように高融点金属とその
金属のシリサイドやナイトライドとの間では、エッチン
グ速度の差が大きい。このため、高融点系金属の多層膜
の加工を行なった場合、エッチング速度の速い層の横方
向エッチングが進む為、矩形断面形状が得られにくく、
パターン転写精度が低下する。ゲートパターンや配線パ
ターンといった微細パターンの加工では、パターンの転
写精度を向上させる事は重要な検討課題の１つである。<Problems to be Solved by the Invention> In the case of the conventional RIE processing technology using CF 4 + O 2 gas, as shown in FIG. 5, refractory metal and silicide or nitride of the metal are used. There is a large difference in etching rate between the two. For this reason, when a multilayer film of a refractory metal is processed, lateral etching of a layer having a high etching rate proceeds, so that it is difficult to obtain a rectangular cross-sectional shape.
The pattern transfer accuracy is reduced. In the processing of fine patterns such as gate patterns and wiring patterns, improving the pattern transfer accuracy is one of the important issues to be considered.
本発明の目的は、最近導入の著しい高融点系金属の多
層膜の加工を高いパターン転写精度で行なうことを可能
とする製造方法を提供することにある。An object of the present invention is to provide a manufacturing method capable of processing a multilayer film of a refractory metal, which has been remarkably introduced recently, with high pattern transfer accuracy.
＜課題を解決するための手段＞ 本発明は、２種類以上のガスを混合したエッチングガ
スを用いて半導体基板上に形成されたゲート金属、配線
金属、若しくはオーミック金属としてＷ系高融点金属を
主成分とする多層構造の金属膜をドライ加工する半導体
装置の製造方法において、前記エッチングガス成分の混
合比を変えることにより前記多層構造金属薄膜の各層の
エッチング速度を調整し、加工形状を制御することを特
徴とする半導体装置の製造方法である。<Means for Solving the Problems> The present invention mainly uses a W-based refractory metal as a gate metal, a wiring metal, or an ohmic metal formed on a semiconductor substrate using an etching gas in which two or more kinds of gases are mixed. In a method for manufacturing a semiconductor device in which a multi-layered metal film as a component is dry-processed, the etching rate of each layer of the multi-layered metal thin film is adjusted by changing the mixing ratio of the etching gas components to control the processed shape. And a method for manufacturing a semiconductor device.
本発明の基本となる実験結果を第１図に示す。第１図
は、ガス圧10Paの場合について、Ｗのエッチング速度で
正規化したWSi膜とWN膜のエッチング速度比を縦軸に
し、横軸にSF6ガス混合比をとったものである。これよ
り、SF6ガス混合比を50％に設定した場合、Ｗ膜とWSi膜
とWN膜のエッチング速度はほぼ同じ大きさとなることが
分かる。従って、SF6（50％）＋CHF3（50％）の混合ガ
スを使用することによって、例えばW/WSのi2層構造膜の
加工でも、１層目と２層目の膜のエッチング速度が等し
いため、あたかも１層の膜を加工すると同じ状態を実現
でき、横方向へのエッチングが十分に抑制されたパター
ン転写精度の高い加工方法を可能とする。例としてW/WS
iを用いたが、この他にW/WN,WSi/WN,TiN/TiSi,Ta/TaNと
いったように適用可能な組み合わせは多数あり、本特許
請求の範囲を何ら制限するものではない。The experimental results, which are the basis of the present invention, are shown in FIG. FIG. 1 shows the etching rate ratio of the WSi film and the WN film normalized by the etching rate of W as the vertical axis and the horizontal axis as the SF 6 gas mixture ratio in the case of the gas pressure of 10 Pa. From this, it is understood that when the SF 6 gas mixture ratio is set to 50%, the etching rates of the W film, the WSi film, and the WN film are almost the same. Therefore, by using a mixed gas of SF 6 (50%) + CHF 3 (50%), the etching rates of the first and second layers are equal even when processing the i2 layer structure film of W / WS, for example. Therefore, it is possible to realize the same state as if a single-layer film is processed, and a processing method with high pattern transfer accuracy in which lateral etching is sufficiently suppressed becomes possible. W / WS as an example
Although i is used, there are many other applicable combinations such as W / WN, WSi / WN, TiN / TiSi, and Ta / TaN, which do not limit the scope of the claims.
また第１図から、SF6ガスの混合比を50％よりも小さ
くすると、順テーパの断面形状を有する加工が可能とな
り、逆に50％よりも大きくすると、Ｔ型断面形状を有す
る加工が可能となることが分かる。順テーパ加工は、配
線に適用することによって、断線の起こりにくいプロセ
スが実現可能となり、Ｔ型加工は、ゲート配線に適用す
ることによってセルファラインプロセスが実現可能とな
る。Further, from FIG. 1, if the mixing ratio of SF 6 gas is smaller than 50%, machining with a forward tapered cross-sectional shape is possible, and conversely, if it is larger than 50%, machining with a T-shaped cross-sectional shape is possible. It turns out that By applying the forward taper processing to wiring, a process in which disconnection is unlikely to occur can be realized, and by applying the T-shaped processing to gate wiring, a self-alignment process can be realized.
以上のように、本発明はSF6＋CHF3混合ガスの混合比
を変えることによって、多層膜の各層のエッチング速度
比を調整できるため、各工程で要求される断面形状を高
いパターン転写精度で実現可能とするものである。As described above, according to the present invention, since the etching rate ratio of each layer of the multilayer film can be adjusted by changing the mixing ratio of SF 6 + CHF 3 mixed gas, the cross-sectional shape required in each step can be realized with high pattern transfer accuracy. It is possible.
＜作 用＞ ２種類以上のガスを混合したエッチングガスを用いて
半導体基板上に形成されたゲート金属、配線金属、若し
くはオーミック金属としてＷ系高融点金属を主成分とす
る多層構造の金属薄膜をドライ加工する半導体装置の製
造方法において、前記エッチングガス成分の混合比を変
えることにより前記多層構造金属薄膜の各層のエッチン
グ速度を調整し、要求される加工断面形状を実現する。<Operation> A metal thin film having a multi-layer structure containing a W-based refractory metal as a main component as a gate metal, a wiring metal, or an ohmic metal formed on a semiconductor substrate by using an etching gas in which two or more kinds of gases are mixed. In the method of manufacturing a semiconductor device that is dry-processed, the etching rate of each layer of the multi-layered metal thin film is adjusted by changing the mixing ratio of the etching gas components to realize the required processed cross-sectional shape.
＜実施例＞ 以下の図に示す実施例にもとずいて本発明を詳述す
る。尚、これによって本発明は限定を受けるものではな
い。<Example> The present invention will be described in detail based on an example shown in the following drawings. The present invention is not limited to this.
本発明の一実施例を第２図に示す。第２図は高融点金
属ゲートによるセルファラインプロセスを用いたFETへ
の応用である。半絶縁性GaAs基板１上にSiイオン注入
（50KeV,4.5E12cm−２）を行ない、アニール（850℃,20
min）を行なってｎ−GaAs能動層２を形成する（第２図
（ａ））。W4/WSi3膜をRFスパッタを用いて蒸着する
（第２図（ｂ））。Ｗ膜４のスパッタ条件は、ガスAr、
ガス圧5mTorr,電力70Wである。WSi膜３の場合は、ガスA
r,ガス圧7mTorr,電力100W,Siの組成比は0.5である。次
に、ゲートのフォトエッチングを行ない、レジスト５を
マスクに本発明による加工を行なう。エッチングガスに
はSF6＋CHF3（50％）を用い、ガス圧10Pa,印加電力100W
の条件のもと、RIE加工を行なう（第２図（ｃ））。レ
ジスト５剥離後、n+注入用フォトエッチングを行ない、
W4/WSi3ゲート金属並びにレジストをマスクにして、Si
イオン注入（50KeV,2E13cm−２）を行ない、レジスト剥
離後ランプアニールを行なってｎ＋GaAs層７を形成する
（第２図（ｄ））。最後に、オーミック電極としてAuGe
/Ni/Au（700Å/250Å/1000Å）８を蒸着し、420℃でア
ロイを施してオーミックをとる（第２図（ｅ））。以上
の工程を経て、高融点金属ゲートによるセルファライン
プロセスを用いたFETが得られる。An embodiment of the present invention is shown in FIG. Figure 2 shows an application to a FET using the self-aligning process with a refractory metal gate. Si ion implantation (50 KeV, 4.5E12 cm-2) was performed on the semi-insulating GaAs substrate 1 and annealing (850 ° C, 20
min) to form the n-GaAs active layer 2 (FIG. 2 (a)). A W4 / WSi3 film is deposited by RF sputtering (Fig. 2 (b)). The sputtering conditions for the W film 4 are gas Ar,
The gas pressure is 5 mTorr and the electric power is 70 W. In the case of WSi film 3, gas A
r, gas pressure 7 mTorr, electric power 100 W, Si composition ratio is 0.5. Next, the gate is photo-etched, and the processing according to the present invention is performed using the resist 5 as a mask. SF 6 + CHF 3 (50%) is used as etching gas, gas pressure 10Pa, applied power 100W
The RIE process is performed under the condition (Fig. 2 (c)). After removing the resist 5, photo etching for n + implantation is performed,
Si using W4 / WSi3 gate metal and resist as a mask
Ion implantation (50 KeV, 2E13 cm-2) is performed, and after resist stripping, lamp annealing is performed to form an n + GaAs layer 7 (FIG. 2 (d)). Finally, AuGe as ohmic electrode
/ Ni / Au (700 Å / 250 Å / 1000 Å) 8 is vapor-deposited and alloyed at 420 ° C to obtain ohmic resistance (Fig. 2 (e)). Through the above steps, a FET using a self-aligning process with a refractory metal gate can be obtained.
＜発明の効果＞ 本発明を用いて、高融点金属のドライエッチを行なう
と、ガスの混合比だけで容易にエッチング速度の調整を
行えるため、工程が簡略化される。また他のガスとの切
替えがないため安全で安定に処理することができ、産業
界へ大いに貢献することができる。<Effects of the Invention> When dry etching of a refractory metal is performed using the present invention, the etching rate can be easily adjusted only by the gas mixture ratio, so that the process is simplified. Moreover, since there is no changeover to other gas, safe and stable processing can be achieved, which can greatly contribute to the industrial world.
【図面の簡単な説明】 第１図は本発明の基本原理となる実験結果を示す図、第
２図は本発明の実施例を説明する為の工程説明図、第３
図は従来技術を用いてW/WSi2層構造膜を加工した場合の
断面形状の説明図、第４図はWSi膜のエッチング速度のS
i組成比依存性を説明するための実験結果を示す図であ
る。 １……半絶縁性GaAs基板、 ２……ｎ−GaAs能動層、 3,10……WSiX（ｘ＝0.5）膜、 4,11……Ｗ膜、 ５……AZ−1400−27レジスト、 ６……Ｐ−SiN膜、 ７……ｎ＋GaAs層、 ８……AuGe/Ni/Auオーミック電極 ９……半導体基板、 12……フォトレジスト。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an experimental result which is a basic principle of the present invention, FIG. 2 is a process explanatory diagram for explaining an embodiment of the present invention, and FIG.
The figure is an explanatory view of the cross-sectional shape when the W / WSi two-layer structure film is processed using the conventional technique, and FIG. 4 is the etching rate S of the WSi film.
It is a figure which shows the experimental result for demonstrating i composition ratio dependence. 1 ... semi-insulating GaAs substrate, 2 ... n-GaAs active layer, 3,10 ... WSi X (x = 0.5) film, 4,11 ... W film, 5 ... AZ-1400-27 resist, 6 ... P-SiN film, 7 ... n + GaAs layer, 8 ... AuGe / Ni / Au ohmic electrode 9 ... Semiconductor substrate, 12 ... Photoresist.
Claims (1)
スを用いて半導体基板上に形成されたＷ系高融点金属を
主成分とする多層構造の金属薄膜をドライ加工する半導
体装置の製造方法において、 前記エッチングガス成分の混合比を変えることにより前
記多層構造金属薄膜の各層のエッチング速度を調整し、
加工形状を制御することを特徴とする半導体装置の製造
方法。1. A method of manufacturing a semiconductor device, comprising dry-processing a metal thin film having a multi-layered structure containing a W-based refractory metal formed on a semiconductor substrate as a main component, using an etching gas containing a mixture of two or more gases. Adjusting the etching rate of each layer of the multi-layered metal thin film by changing the mixing ratio of the etching gas components,
A method for manufacturing a semiconductor device, comprising controlling a processed shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63149050A JP2506151B2 (en) | 1988-06-15 | 1988-06-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63149050A JP2506151B2 (en) | 1988-06-15 | 1988-06-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH022618A JPH022618A (en) | 1990-01-08 |
| JP2506151B2 true JP2506151B2 (en) | 1996-06-12 |
Family
ID=15466556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63149050A Expired - Fee Related JP2506151B2 (en) | 1988-06-15 | 1988-06-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2506151B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2569754B2 (en) * | 1988-09-10 | 1997-01-08 | 富士通株式会社 | Method for manufacturing compound semiconductor device |
| JPH07235539A (en) * | 1994-02-25 | 1995-09-05 | Sony Corp | Multilayer wiring and dry etching thereof |
| JPH07245293A (en) * | 1994-03-04 | 1995-09-19 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JP3872069B2 (en) * | 2004-04-07 | 2007-01-24 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3216823A1 (en) * | 1982-05-05 | 1983-11-10 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR PRODUCING STRUCTURES OF DOUBLE LAYERS CONSISTING OF METAL SILICIDE AND POLYSILIZIUM ON SUBSTRATES CONTAINING INTEGRATED SEMICONDUCTOR CIRCUITS BY REACTIVE ION NETWORK |
| JPS59181676A (en) * | 1983-03-31 | 1984-10-16 | Fujitsu Ltd | Semiconductor device |
| JPS61168228A (en) * | 1985-01-19 | 1986-07-29 | Sharp Corp | Dry etching method |
| JPS62154628A (en) * | 1985-12-26 | 1987-07-09 | Matsushita Electric Ind Co Ltd | Dry etching method |
| JPS62238382A (en) * | 1986-04-07 | 1987-10-19 | Canon Inc | Dry etching gas and dry etching method |
| JPS6432627A (en) * | 1987-07-29 | 1989-02-02 | Hitachi Ltd | Low-temperature dry etching method |
-
1988
- 1988-06-15 JP JP63149050A patent/JP2506151B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH022618A (en) | 1990-01-08 |
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