JP2504225B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to image processing, and particularly in a facsimile or the like, a portion having a halftone level such as a photograph and a document portion such as a character pattern are adapted to each other. The present invention relates to an image processing apparatus suitable for digitization.

[Prior Art] Conventionally, a dither method has been well known as a method for artificially realizing an image having a halftone level such as a photograph by a binary value of white or black. In this dither method, the threshold value of the image signal is determined by the coordinate information on which the pixel is to be displayed and binarized. Normally, a threshold matrix of a fixed size is repeatedly expressed and used as the threshold information of the entire screen. .

The systematic dithering method is excellent for expressing a halftone image such as a photograph, but when applied to a binary image such as an ordinary document or figure, it has a problem that a contour portion is blurred. To solve the problem, a halftone image portion such as a photograph and a binary image portion such as a document including characters and figures are automatically identified, and only the halftone portion is binarized with a dither threshold. A method of binarizing a character / graphic portion of a document or the like with a fixed threshold is considered.

As an example of such a method, "Binarization processing method of a document in which a binary image and a grayscale image are mixed" (Shinji Tetsutani, Hiroshi Ochi)
The "area separation method for each block" as shown in IEICE Transactions '84 / 7 Vol.J67-B No.7) is known. In this method, it is determined whether each block is a halftone area or a document area based on the difference between the maximum value and the minimum value in a certain block of the image, and the dither threshold binarization processing and the fixed threshold binarization processing are performed. Is being switched.

FIG. 12 is a block diagram of such a conventional image processing apparatus. In particular, the image block size is 4 pixels × 4 pixels, the number of image signal levels is 16 levels, and the difference between the maximum and minimum levels is 8 or less. If there is a halftone block, and if the difference between the maximum value and the minimum value of the level exceeds 8, it is determined as a document block. In the figure, (1) is a block size of horizontal 4 pixels and vertical 4 pixels, so it has a size capable of storing at least 3 lines, and a halftone memory capable of storing each pixel at 16 levels, (2) Is a maximum value / minimum value detection circuit for detecting the maximum value and the minimum value in each block of the image stored in the halftone memory (1),
(3) is a determination circuit for determining whether the block is a halftone block or a document block, based on the difference between the maximum value and the minimum value in the block detected by the maximum value / minimum value detection circuit (2), ) Is a fixed threshold binarization circuit that binarizes the image block from the halftone memory (1) with a fixed threshold,
(5) is a dither threshold binarization circuit that binarizes the image block from the halftone memory (1) with a dither threshold, and (6) is a fixed threshold binarization circuit based on the determination result of the determination circuit (3). (4) and a switch for switching and outputting the outputs of the dither threshold binarization circuit (5), (7) is a binary memory for line-sequentially extracting outputs for four lines, and (8) is 4 pixels ×
It is a signal selection circuit for sequentially sending pixels in a block of 4 pixels to a binarization circuit (4) and a dither threshold binarization circuit (5) with a fixed threshold value.

In such a configuration, the block of the image stored in the halftone memory (1) detects the maximum value and the minimum value in the maximum value / minimum value detection circuit (2), and the determination circuit (3) determines whether the image is a halftone image. To be done. On the other hand, the contents of the halftone memory (1) are given to the fixed threshold binarization circuit (4) and the dither threshold binarization circuit (5) through the signal selection circuit (8) and binarized with the fixed threshold values. The dither threshold is also binarized.
The output of each binarization circuit is selected through the switch (6) judged by the output of the judgment circuit (3) and is temporarily stored in the binary memory (7), and the binarized signals for four lines are sequentially extracted line by line. Be done.

[Problems to be Solved by the Invention] Since the conventional image processing apparatus is configured as described above, it is determined whether each block is a halftone area or a document area after dividing the image area in block units. Therefore, when the background happens to be white at the boundary of blocks and the area moves from here to the document area, there is a possibility that both blocks may be determined to be a halftone area, which causes a problem that the image quality deteriorates.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and sequentially moves a block for area determination according to a pixel of interest to thereby sequentially output a halftone area or a document area. It is an object of the present invention to provide an image processing apparatus capable of determining whether or not it is possible, binarizing an image with higher compatibility, and ensuring high-quality image quality.

[Means for Solving the Problems] In order to solve the above problems, the image processing device of the present invention is an image processing device that binarizes and outputs an image signal having a halftone level, and performs main scanning within a predetermined pixel block. First maximum / minimum value detecting means for detecting maximum / minimum values in a plurality of pixels at the same position in the direction, and first storage for temporarily storing outputs of the first maximum / minimum value detecting means. Storage means, a second maximum value / minimum value detection means for detecting a maximum value and a minimum value by the first storage means output and the first maximum / minimum value detection means, and the second maximum value. Second storage means for temporarily storing the output of the minimum value detection means, and third maximum value for detecting the maximum value and the minimum value by the output of the second storage means and the output of the first maximum value minimum value detection means. The minimum value detecting means and the third maximum value minimum value detecting means are output. A third storage unit for temporarily storing the force, and a plurality of adjacent pixels on the same main scanning line based on the maximum value and the minimum value in the predetermined pixel block which is the output of the third storage unit are binary image areas. One of an output of the plurality of binarizing means based on the output of the determining means, a plurality of binarizing means for binarizing the image signal by different means And a switching means for selecting and outputting the third maximum value / minimum value detection means, the output of the third maximum / minimum value detection means is also input to the second storage means, and the second storage means has the second maximum / minimum value. Selectively storing and outputting the output of the value detecting means and the output of the third maximum / minimum value detecting means, and binarizing a plurality of adjacent pixels on the same main scanning line in a predetermined pixel block all together. It is characterized by.

[Operation] In the above means, the first maximum value / minimum value detection means detects the maximum value and the minimum value in the pixel having the same position in the main scanning direction, and the first storage means causes the maximum value and the minimum value to be detected. Remember the value. Further, the second maximum value minimum value detecting means detects the maximum value and the minimum value from the output of the first maximum value minimum value detecting means and the output of the storage means, and the maximum value is detected by the second storage means. And memorize the minimum value. Then, the third maximum value / minimum value detection means detects the maximum value and the minimum value from the output of the first detection means and the output of the second storage means, and stores them in the third storage means. The output from the third storage means is the maximum value and the minimum value in the predetermined pixel block, and the determination means determines whether the pixel is a binary image area or a halftone image area from the maximum value and the minimum value.

On the other hand, the plurality of binarizing means binarize the pixel signal by a plurality of different means. The switching means selects one of the outputs of the binarizing means based on the output of the judging means and outputs it.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 and 2 are block diagrams of an image processing apparatus according to an embodiment of the present invention, and particularly exemplify a configuration in which the number of levels of image signals is 16 levels (white level = 16, black level = 1). It is a thing. The reference region for the region determination is 3 pixels × 3 pixels centering on the pixel of interest, and the maximum value and the minimum value of these are checked to sequentially determine the region and switch the binarization method. In FIG. 1, (1) is a halftone memory having a size capable of storing at least two lines of image signals from a reference area of 3 pixels × 3 pixels, and storing each pixel at 16 levels, (3 ) Is a determination circuit for determining whether each block is a halftone area or a document area based on the detection result of the maximum value / minimum value detection circuit (2) based on the difference between the maximum value and the minimum value.

FIG. 2 is a detailed configuration diagram of the maximum value / minimum value detection circuit (2) in FIG. 1, and (21) shows the same position of the previous scanning line, the current scanning line and the next scanning line from the halftone memory (1). The first maximum / minimum value detector that inputs one image signal (21a, 21b, 21c) and outputs the maximum value / minimum value (21d), (22) outputs this detector output (21d) as one pixel Registers (23a) for delayed output (22a, 22b) for clock and two pixel clocks
Detects the maximum value minimum value of the output (21d) of the first maximum value minimum value detector (21) and the two outputs (22a, 22b) of the register (22) and outputs it to the determination circuit (3) (23a The second maximum value / minimum value detector, (24) outputs the current scanning line image signal (21b) to 1
The delay circuit delays the pixel clock and outputs (24a) to the binarization circuit (4, 5) as the image signal of interest.

In the configuration of the embodiment, the binarized signal of the image is processed or output on a line-by-line basis. Therefore, the signal selection circuit (8) and the binary memory (7) which are necessary in the conventional configuration of FIG. ) Is unnecessary.

 Next, the operation of this structure will be described.

FIG. 3 is an explanatory diagram showing an example of an image signal seen at an edge portion of a character. FIG. 4 is an explanatory diagram showing an example of a matrix of dither threshold values set in the dither threshold binarization circuit (5). Now, the image signal is V, the threshold is T,
Let R be a binarized display signal, and if V> T, R = 1, V ≦ T
If so, R = 0. FIG. 5 (a) shows the image signal of FIG. 3 binarized by the dither threshold binarization circuit (5) with a dither threshold as shown in FIG. on the other hand,
FIG. 5B shows the image signal of FIG. 3 which has been quantized by the fixed threshold binarization circuit (4) using the threshold of level 7.

In the area determination of the conventional method, the level difference between the maximum value and the minimum value is 7 in the area of 4 pixels × 4 pixels on the left side, and the level difference of 4 pixels × 4 pixels on the right side.
In the pixel area, the level difference between the maximum value and the minimum value is 2, and the determination circuit (3) determines that the pixel area is the halftone area P as shown in FIG. 6 (a). As a result, the switch (6) selected the output of the dither threshold binarization circuit (5) to obtain the display signal R based on the dither threshold as shown in FIG. 7 (a).

On the other hand, in this embodiment, 3
If the difference between the maximum value and the minimum value from the output of the maximum value / minimum value detection circuit (2) is 8 or more in the area of pixels × 3 pixels, the determination circuit (3) determines that it is the document area C, and the difference is 7 or less. If so, it is determined to be the halftone region P, and therefore the region determination is performed in pixel units as shown in FIG. 6 (b). As a result, the switcher (6) switches the output of the fixed threshold binarization circuit (4) and the output of the dither threshold binarization circuit (5) on a pixel-by-pixel basis based on the output of the determination circuit (3), and the seventh A display signal based on the dither threshold and a display signal R based on the fixed threshold as shown in FIG.

The detailed operation of the maximum / minimum value detection circuit (2) is as shown in FIG. In the figure, a ₁ , a ₂ ... are the first scan line
The 1,2 ... th image signals, b ₁ , b ₂ ... are also c ₁ , c ₂ of the current scanning line
Are image signals of the first, second ... Further, M (ijk ...) Shows the maximum and minimum values in the image signals i, j, k.

As is clear from the figure, when the image signal from the image memory (1) is input to the maximum value / minimum value detection circuit (2) for each scanning line, the image signal of interest (24
a) and the detection maximum value / minimum value signal (23a) of the area of 3 pixels × 3 pixels centered on it are output to the binarization circuit (4, 5) and the determination circuit (3), respectively. .

Here, the register (22) is initially set to the maximum value = 1 and the minimum value = 16 at the beginning of the scanning line. At the end of each scanning line, the same signal as that of the last pixel of each line is input to this circuit after the effective image signal.

Since the binary signal obtained in this case has no unevenness of the binary signal in the document area as in the conventional case, the image quality can be improved.

Generally, the halftone level always appears at the edge portion of a character or the like due to the integration effect, but in the configuration of the present invention, the area determination is always made by referring to the pixel signal in the range of 3 pixels × 3 pixels centering on the pixel of interest. Can be performed accurately. It should be noted that the white part of the background and the black part of the character are sufficiently white or black even if they are judged to be halftone, so even if binarized with a fixed threshold or binarized with the dither threshold, it becomes a binarized signal. Has little effect. However, if the edge part is binarized as a document region with a fixed threshold value, a binarized image signal having a much higher quality can be obtained as compared with the case where the edge part is binarized with the dither threshold value as the halftone region.

Although the reference area for area determination is 3 pixels × 3 pixels centered on the pixel of interest in the above embodiment, a wider range may be used as the reference area when the pixel resolution is high.

FIG. 9 shows an example of the maximum value / minimum value detection circuit (2) in such a case. In the present embodiment, one scanning line has three lines.
It is divided into blocks for each pixel, and the binarization method is switched for each pixel block of interest by using the maximum and minimum values in the reference area shown in FIG.

In FIG. 9, the second maximum / minimum value detector (25) is the maximum or minimum value from the outputs (22a) (delayed by one pixel clock) of the first detector (21) and the register (22). This output (25a) is used to detect the value, and the output (25a) is initially stored in the system of the second register (26) and the third maximum / minimum value detector (27) which sequentially calculate the maximum and minimum values. It is configured to be input as. Therefore, in the second register (26), this second detector output (25a) is the first input of the register (26), while this second input serves as a feedback input for the third detection. Output (27a) is input. This second register output (26a) is input to the first input of the third detector (27), and the first maximum / minimum value detector output (21d) is input to the second input. There is. This third detector output (27a) is then sent to the third register (2
It is taken as an input of 8) and taken into this register once every three pixel clocks and sent to the judgment circuit (3) as a detection maximum value minimum value signal (23a). The delay circuit (24) delays the current scanning line signal by four pixel clocks in order to compensate for the delay of the detection signal (23a) in the maximum value / minimum value detection circuit (2), and uses it as a target image signal (24a). There is. FIG. 11 shows the operation of the maximum / minimum value detection circuit (2) in this embodiment. The ▼ mark in the figure indicates the timing at which the (immediately before) third detector output (27a) is fetched by the third register (28). Also the second
The arrow indicates the method of selecting the first and second inputs in the register (26). As is clear from the figure, a pixel block of 3 pixels each (for example, b ₄ , b ₅ , b ₆ ) has 5 pixels × 5 pixels shown in FIG.
3 pixels of the reference pixel region (in this case _{a 3 ~a 7, b 3 ~b} 7, c 3 ~
The maximum / minimum value of c ₇ ) determines the binary / halftone area.

Further, in the above embodiment, the case of setting the criterion of the region determination as to whether the difference between the maximum value and the minimum value is 8 or more is exemplified, but not only the difference between the maximum value and the minimum value, but also the absolute value of the maximum value and the minimum value. It may be possible to determine whether each block is a halftone area or a document area. In this case, for example, if the difference between the maximum value and the minimum value is 8 or more, the document area, and if the difference is less than 7, the maximum value is 3 or less, or if the minimum value is 14 or more, the document area is the maximum value and the minimum value. The area is determined based on the difference between the values and the absolute value of each.

Further, the arrangement of the dither threshold and the fixed threshold in the binarization method for a binary image are not limited to those in this embodiment, and in the latter case, other combinations such as floating slices can be applied. .

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to determine a binary image area such as a document of an image and a halftone image area such as a photograph in a block unit composed of a plurality of pixels on one scanning line. Since it is configured, it is possible to make a more accurate determination, and it is possible to express a high quality image. Further, since the binarized signal is also processed and output in units of one line, there is an effect that the circuit configuration is simple and can be inexpensively constructed.

[Brief description of drawings]

FIG. 1 is a block diagram of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a detailed configuration diagram of the maximum value / minimum value detection circuit shown in FIG. 1, and FIG. FIG. 4 is an explanatory view showing an example of a picture signal that can be seen, FIG. 4 is an explanatory view showing an example of a matrix of a dither threshold, and FIG. 5 (a) shows the picture signal of FIG. 3 with a dither threshold as shown in FIG. FIG. 5 (b) is an explanatory diagram in the case of binary quantization, FIG. 5 (b) is an explanatory diagram in the case of binary quantization of the image signal in FIG. 3 with a fixed threshold, and FIG. 6 (a) is a region determination by a conventional method. FIG. 6 (b) is an explanatory diagram of the determination result when the region determination is performed with the configuration of FIG. 1, and FIG. 7 (a) is a binary conversion result by the conventional method. 7 is an explanatory view of the display signal, FIG. 7 (b) is an explanatory view of the display signal when binarized in the configuration of FIG. 1, and FIG. 8 is a maximum value / minimum value detection circuit of FIG. FIG. 9 is an operation explanatory diagram, FIG. 9 is a diagram showing another embodiment of the maximum value / minimum value detection circuit, FIG. 10 is a diagram showing a reference pixel area used for area determination in this embodiment, FIG. 11 (a), (B) is an operation explanatory view of the maximum value / minimum value detection circuit of the embodiment, and FIG. 12 is a block diagram of a conventional image processing apparatus. In the figure, (3) is a judgment circuit, (4) is a binarization circuit for binary images, (5) is a binarization circuit for halftone images, (6) is a switch, and (21) is a first maximum. A value minimum value detector, (22) a first delay means (register), (23) a second maximum value minimum value detector, (25) a maximum value minimum value detector, and (26) a second. (27) is a maximum value / minimum value detector, and (28) is a third delay means. Further, the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. An image processing apparatus for binarizing and outputting an image signal having a halftone level, wherein a maximum value and a minimum value in a plurality of pixels having the same position in the main scanning direction in a predetermined pixel block are set. First maximum / minimum value detecting means for detecting, first storage means for temporarily storing the output of the first maximum / minimum value detecting means, output of the first storing means and the first maximum value Second maximum value / minimum value detection means for detecting the maximum value and minimum value by the minimum value detection means; second storage means for temporarily storing the output of the second maximum / minimum value detection means; and the second A third maximum value / minimum value detecting means for detecting a maximum value and a minimum value by the storage means output and a first maximum value / minimum value detecting means output; and a third maximum value / minimum value detecting means output. Third storage means for storing and a predetermined output which is the output of the third storage means Of the plurality of pixels adjacent to each other on the same main scanning line based on the maximum value and the minimum value in the pixel block, and the image signal is binarized by different means. A plurality of binarizing means and a switching means for selecting one of the outputs of the plurality of binarizing means based on the output of the judging means and outputting the selected one. The means output is also input to the second storage means, and the second storage means outputs the second maximum value / minimum value detection means output and the third value.
And a maximum value / minimum value output of the maximum value / minimum value detection means are selectively stored and output, and a plurality of pixels adjacent to each other on the same main scanning line in a predetermined pixel block are collectively binarized.