JP2502391B2 - Amplifier for read signal of disk storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for AGC-amplifying a read signal of recorded data in a disk storage device such as a fixed disk device so that the read signal has a constant amplitude.

[Conventional technology]

As is well known, in a disk storage device, the recorded data is a predetermined code or modulation system, such as MFM system or RLL system.
It is magnetically recorded in a track set on the disk surface by an alternating pattern of N and S defined by the method, and is read through a head as a magnetic transducer. The read signal of this recording data is N of the magnetic recording pattern on the disk.
The disk storage device has an analog waveform having a maximum or minimum peak at the phase corresponding to the boundary between S and S switching, and the disk storage device detects the peak position and then converts the analog waveform read signal into a waveform read signal of a predetermined modulation method. The original recorded data is reproduced by demodulating and decoding this.

By the way, the amplitude of the read signal of the above analog waveform is proportional to the speed of the disk with respect to the head, and therefore it changes depending on the radial position of the head on the disk. The accuracy of peak position detection during demodulation is very susceptible to this amplitude change.

For this reason, it has been conventionally practiced to automatically control the amplitude of the read signal of the analog waveform to a constant value by the AGC amplifier circuit before applying the read signal to the demodulator circuit. As is well known, this AGC amplifier circuit is a combination of a gain controllable variable amplifier and an amplification factor control circuit.The amplification factor control circuit receives the output of the variable amplifier and keeps its amplitude constant. The amplification factor control signal is given to the variable amplifier to perform the closed loop control of the amplification factor of the AGC amplifier circuit.

Depending on the disk storage device, an area where no data is recorded may be set in a part of the track in the circumferential direction, and this so-called erase area may be detected and used for timing control of some kind of operation. However, if the AGC is applied too sharply when it suddenly disappears, it may not be possible to detect this erase area. In many cases, so-called two-speed control is used, which switches between high and low depending on whether to lower or lower.

[Problems to be Solved by the Invention]

As described above, the conventional read signal amplification method is the AGC amplification method which controls the amplitude of the read signal to be constant. However, when the data recording density on the disk is increased to increase the storage capacity, the head is There is a problem that the peak detection becomes inaccurate when the read signal is demodulated when it is on the inner diameter side. This is because, in a normal magnetic recording method, the pitch of the NS replacement pattern written on the disc is narrower on the inner diameter side than on the outer diameter side of the disk.

That is, the read signal has an analog waveform in which positive and negative peaks corresponding to the switching point of N and S are continuous, and mutual interference between the positive and negative peaks almost occurs on the outer diameter side where the average pitch of the NS alternating pattern of magnetic recording is wide. However, since the positive and negative peaks adjacent to each other interfere with each other on the inner diameter side where the average pitch is narrow,
This is because the read signal on the inner diameter side is not only smaller in amplitude than that proportional to the radius, but also changes in the waveform of the peak included therein, causing the maximum and minimum points to deviate from their original positions.

The point where the amplitude of the read signal becomes very small on the inner diameter side can be compensated by increasing the control gain even in the conventional amplifier circuit, but it cannot be dealt with the deformation of each peak waveform. To solve this problem, the width of each peak in the read signal can be narrowed, but there is a natural limitation on the characteristics of the head as a magnetic transducer, and improvement in this point is not expected. For this reason, the CDR (Constant Density Recording) method, in which the writing pitch of the magnetic pattern is kept constant regardless of the radial position of the disc, or the disc surface is divided into a plurality of ranges, and ZB is arranged in a uniform manner between the ranges.
The R (Zone Bit Recording) method has been tried.

Although the above-mentioned problem of peak waveform deformation is solved by such a magnetic pattern writing method, it is most advantageous in the current state of the art to always keep the disk rotation speed constant even in such a case. A new problem arises in which the mutual spacing of the peaks, that is, their frequency, changes with the radial position of the disk.

The frequency of this read signal is, of course, high on the outer diameter side and about half or less on the inner diameter side, but the conventional AGC amplifier circuit as described above was originally designed to be used within such a wide frequency range. Since there is no control error due to the frequency dependence of the amplification factor characteristic, if the control gain of the system including the variable amplifier and the amplification factor control circuit is increased to eliminate this, the operation becomes very unstable.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problem and to obtain a read signal amplifying device that has a small control error in AGC amplification and a stable amplification operation even when the frequency of the read signal changes in a considerably wide range. .

[Means for solving the problem]

According to the present invention, the object is to provide the above-mentioned variable amplifier and amplification factor control circuit with a response speed designating means for issuing a response speed command corresponding to the position of the head on the disk surface, and a time constant corresponding to the response speed command. This is achieved by combining with a response speed control circuit that controls the temporal change rate of the amplification factor control signal provided from the amplification factor control circuit to the variable amplifier.

The above-mentioned response speed designating means is usually constituted by software in a processor which is built in a disk storage device and operates or controls the position of the head to sequentially store the current position of the head on the disk surface. It is then advantageous to emit it in the form of digital data. Further, it is advantageous that the response speed control circuit is configured so that the logic response circuit receives the digital response speed command and the output of the response speed control circuit switches the capacitor for setting the time constant of the temporal change of the amplification factor control signal.

[Action]

In the conventional AGC amplifier circuit, the amplitude of the output signal of the variable amplifier is controlled to be constant by simply designating the amplification factor from the amplification factor control circuit to the variable amplifier by the amplification factor control signal. By controlling not only the magnitude of this amplification factor control signal but also its temporal change rate, the control error on the AGC amplification of the read signal is reduced and the amplification operation is performed even when the frequency changes in a wide range. Has been successfully stabilized.

That is, in the present invention, by controlling the temporal change rate of the amplification factor control signal according to the frequency of the read signal, the response speed of the AGC amplifier circuit with respect to the amplitude change of the input signal is optimized according to the frequency of the read signal. . It is customary to detect the frequency for this purpose from the read signal. However, in the present invention, this frequency is determined in advance according to the radial position of the head on the disk, and the frequency is determined in the processor of the disk storage device. Paying attention to the fact that the current position of the head is always stored, the current speed on the disk surface of the head, that is, the response speed command corresponding to the frequency of the read signal, is converted into a digital data form by the response speed designating means in the preceding paragraph. Generated by.

It should be noted that, although the read signal usually contains a plurality of two frequencies, which differ depending on the modulation method, and the appearances of them differ depending on the contents of the stored data, the present invention rather than detecting such a composite frequency. It is much easier and more accurate in control operation to generate the response speed command by the response speed designating means in relation to the current position of the head.

The response speed control circuit of the present invention that receives this response speed command controls the amplification factor control signal given to the variable amplifier from the amplification factor control circuit so that it changes with time with a time constant corresponding to this command value. Controls the response speed to the input signal of the AGC amplifier circuit. Of course, this allows AGC
The response speed of the amplifier circuit is increased when the frequency of the read signal is high and decreased when the frequency of the read signal is low.

It should be noted that the magnitude value of the amplification factor control signal whose temporal change rate is controlled is generated by the amplification factor control circuit so as to keep the analog value of the output signal after amplification constant. The control signal value is usually generated based on the average value of the peak values of the positive and negative peaks included in the output signal of the variable amplifier in order to stabilize the AGC amplification operation. As is well known, since the control gain is very high in the AGC amplifier circuit, if the actual value of the amplitude of the output signal on which the control is based is disturbed by an accidental fluctuation that can occur in the peak value of each peak, This is because there is a danger of oscillation.

However, when the frequency of the read signal, that is, the number of positive and negative peaks in a unit time, changes, the time taken for the above average value changes. Therefore, if the response speed of the AGC amplification system is constant regardless of the frequency, the variable amplifier Since the ratio of the range that is extracted to obtain the actual control value from the changing waveform of the output signal changes depending on the frequency, its influence depends on the frequency of the AGC amplification system. It appears as qualitative. In the present invention, since the response speed of the system is specified and controlled according to the position of the head, that is, the frequency of the read signal, there is almost no control error, and stable amplification operation is achieved even if the control gain in the system is sufficiently increased. The property is improved.

〔Example〕

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. FIG. 1 shows a basic block circuit configuration of a read signal amplifying device according to the present invention and a configuration example of a disk storage device incorporating the same, FIG. 2 shows a read signal waveform example, and FIG. 3 shows a circuit of the present invention device. Specific configuration examples of the parts are shown respectively.

Disk storage device shown in FIG. 1 surrounded by a chain line
A fixed disk device 10 is combined with an attached controller 20 in this example, and is connected to a computer (not shown) via a bus 21. The disk storage device 10 receives a write signal WS of a predetermined modulation method such as MFM from the controller 20 and writes it in the disk 1, and conversely reads it from the disk 1 and uses it as a read signal RS of the same modulation method as the controller 20.
Pass to. It should be noted that only the portion related to the present invention is shown in the disk storage device 10.

In this embodiment, the ZBR magnetic recording method described above is adopted. For this reason, the surface of the disk 1 in which a large number of tracks T are set is divided into three areas Z0 to Z2 in this example, each of which is composed of substantially the same number of track groups. Data is written by the write signal WS having a frequency, but from the outer diameter side area Z0 to the inner diameter side area Z2.
Lower fundamental frequencies, such as regions Z0, Z1 and Z2
Write signals with basic frequencies of 14 MHz, 10 MHz and 6 MHz, respectively
Data is written by WS.

The head 2 is connected to an actuator 3 of a voice coil motor type in this example via an arm 2a, and the actuator 3 can be oscillated by a drive circuit 4 in the S direction in the figure so that the head can be placed on a desired track. ing. The head 2 provided for each disk surface is connected to the read / write circuit 5 via the lead 2b, and the head designated by the head selection command HS is placed in a read or write state in accordance with the read / write command RW.

The analog waveform read signal R0 output from the read output R of the read / write circuit 5 is applied to the variable amplifier 30, and the read signal R1 amplified to a constant amplitude by this is applied to the demodulation circuit 6 including the peak detection circuit. Then, it is converted into a read signal RS of a predetermined modulation method having a digital waveform. The amplification factor control circuit 40 receives the above-mentioned read signal R1 and gives the amplification factor control signal CS to the variable amplifier 30 so as to keep its amplitude constant, and controls the time change rate of this amplification factor control signal CS. In order to do so, a response speed control circuit 60 that constitutes the present invention is provided.

As usual, a processor 7 is provided in the disk storage device 10 for internal control and is connected to the controller 20 via a bus 8 or the like. A drive command DS is given to the drive circuit 4 and a read / write circuit 5 is given to the read / write circuit 5. Give head selection command HS respectively.
The response speed designating means 50 constituting the present invention is incorporated in the processor 7 in the form of software, for example.

The processor 7 puts the head 2 on a desired track so that its current position is usually in the form of a track number i in a storage area.
Since it is always stored in 7a, the response speed designating means 50 uses this stored content to issue a response speed command RD corresponding to it to the response speed control circuit 60 in the form of digital data.
In this embodiment, as described above, the frequency of the write signal WS of the recording data, and hence the frequency of the read signal R0 from which it is read, is different for each of the areas Z0 to Z2 of the disk 1, so the response speed command means 50 stores, for example, Track number i is area Z0-
A value of 0 to 2 may be selected depending on which of Z2 corresponds to the 2-bit response speed command RD.

The response speed control circuit 60 receives the response speed command RD and controls the time change of the amplification factor control signal CS given to the variable amplifier 30 with the time constant τ set corresponding to the value. The waveforms of the read signals R0 and R1 input and output by the variable amplifier 30 that receives the amplification factor control signal CS according to FIG. 2 are shown in the form of envelopes of positive and negative peaks included therein. Here, FIG. 1A shows a variable amplifier.
The waveform of the read signal R0 input by 30 is shown in FIG.
(D) shows the waveform of the read signal R1 output from the variable amplifier 30 when the head is in each of the areas Z0 to Z2.

When the amplitude of the read signal R0 on the input side fluctuates as shown in FIG. 9A, the read signal R1 on the output side is always AGC controlled with the amplitude A being a constant value as shown in FIGS. However, in the circuit of the present invention, the response time until the fluctuation of the amplitude is suppressed is controlled according to the frequency of the read signal R1 as shown by T0 to T2 in the figure. In this example, the time constant τ is switched for each region according to the value of the response speed command RD so that the response time T0 is short in the high frequency region Z0 and the response time T2 is long in the low frequency region Z2.

It is advantageous that the response time T0 to T2 is almost inversely proportional to the frequency of the read signal corresponding to the areas Z0 to Z2, that is, it is substantially proportional to the interval between the positive and negative peaks in the read signal. The basic frequency of the read signal corresponding to the areas Z0 to Z1 is 14 to 9 MHz, and the gain control circuit 40 uses the gain control signal based on the average value of the peak values of about 10 peaks in the read signal, for example. When generating CS, it is preferable to set the time constant τ in the response speed control circuit 60 so that the response times T0 to T2 are about 1 to 2 μS, respectively. In this case, the number of peaks in the read signal included in the response times T0 to T2 is about ten and more in each of FIGS. 2 (b) to (d).

In the device of the present invention, by controlling the response speed of the AGC amplifier circuit according to the frequency of the read signal in this way, it is extracted in order to obtain the actual value in the amplification factor control from the above-mentioned fluctuation waveform of the read signal. By making the range ratio almost constant regardless of the frequency, it is possible to reduce the control error and improve the stability of the AGC operation as compared with the conventional case.

FIG. 3 is a variable amplifier shown as a block in FIG.
30, specific circuit examples of the amplification factor control circuit 40 and the response speed control circuit 60 are shown, and each of them is shown surrounded by a dashed line.

The main body of the variable amplifier 30 is a differential amplifier consisting of a pair of transistors 31 and 32, and a pair of differential signals of the read signal R0 is input to the bases of these transistors, respectively, via load resistors 31a and 31b. A pair of differential signals of the read signal R1 is derived from those collectors connected to the power supply V. The emitters of differential transistors 31 and 32 are interconnected by a coupling resistor 33 in this example, and control transistors 34 and 35 are connected.
It is also connected to the ground point via the emitter resistors 34a and 35a. The amplification factor control signal CS is given to the common connection base of the control transistors 34 and 35, which controls the currents of these control transistors, and controls the amplification factors of the differential transistors 31 and 32 through which this current flows. The emitters of the differential transistors 31 and 32 may be short-circuited to be grounded via a single control transistor and its emitter resistance.

In the illustrated example, the amplification factor control circuit 40 includes a VI conversion circuit 41 and a transistor 42. The VI conversion circuit 41 is composed of, for example, a full-wave rectifier circuit that receives the read signal R1 output from the variable amplifier 30 and converts the read signal R1 into a DC current that represents the amplitude value, and the read signal is generated according to the time constant of the integration operation on the DC output side. The number of positive and negative peaks taking the average value is set. Collector resistor 42a
The transistor 42 having the emitter resistor 42b and the emitter resistor 42b receives the output current of the VI conversion circuit as the base current, and the amplification factor control signal CS is derived from the collector side. When the amplitude of the read signal R1 increases, the output current of the VI conversion circuit 41 increases and
The amplification factor control signal CS from 42 decreases to keep the amplitude of the read signal constant.

The response speed control circuit 60 in this embodiment uses the read signal
When the amplitude of R1 changes and the base current injected into the transistor 42 changes, the speed at which the base potential changes is set by the size of the capacitance connected to the base, thereby the AGC amplification system for the read signal. Is configured to control the response speed of the.

Therefore, in this example, three capacitors C0 to C2 are provided in the response speed control circuit 60, and the above-described response speed command RD
By operating the analog switches 61 and 62 that open and close the capacitors C1 and C2 respectively by the output of the logic circuit 63 that receives
The capacitance value connected to the base of the upper transistor 42 can be set. As a result, when the head is in the aforementioned areas Z0, Z1, Z2, the capacitance values are set to C0, C0 + C1, C0 + C1 + C2, respectively. As will be easily understood, in this embodiment, the capacitance value and the base resistance 42b of the transistor 42 set the above-mentioned time constant τ by the response speed control circuit 60.

The response speed command means 50 constituting the present invention can be constructed by very simple software. For example, in the simplest case, if the size and number of the area Z0 and the like in the disk 1 in FIG. 1 are set appropriately, for example, the upper 2 bits of the track number i stored in the processor 7 is directly used as the response speed command.
It can be output as RD.

The present invention is not limited to the embodiments described above, and the present invention can be implemented in various modes. The above-described specific operation example and the specific circuit configuration in FIG. 3 are merely examples, and appropriate selections and modifications can be made within the scope of the present invention as necessary or necessary.
Further, additional functions such as the above-mentioned two-speed control can be incorporated in the amplification factor control circuit, for example.

〔The invention's effect〕

As described in detail above, in the present invention, the response speed corresponding to the current position of the head is set to the variable amplifier for amplifying the read signal of the data and the amplification factor control circuit which gives the amplification factor control signal so as to keep the output signal constant. The response speed designating means for issuing a command and the response speed control circuit for controlling the temporal change rate of the amplification factor control signal with the time constant according to the response speed command are combined to determine the magnitude of the amplification factor control signal and the amplitude of the read signal. By controlling the rate of change with time according to the frequency, it is possible to reduce the control error during AGC amplification and stabilize the operation even when the frequency of the read signal changes over a wide range. .

In the read signal AGC amplifier of the disk storage device, the control or feedback gain in the system is increased as much as possible to reduce the control error, and the response speed to the amplitude fluctuation of the read signal is set to the optimum value for reading the data. In the conventional high precision AGC amplifier circuit with high feedback gain,
Although it was very difficult to set the response speed when the frequency of the read signal changes in a wide range to the optimum value for reading the data without impairing the stability of the operation, the present invention sets the response speed of the read signal. By controlling according to the frequency, this difficulty can be solved.

The present invention having such a feature is particularly effective when applied to a disk storage device of a new magnetic recording system such as CDR or ZBR, and by overcoming the difficulty in its practical application to demonstrate the true value of the new system, This can contribute to further increase in storage capacity and higher performance of the disk storage device.

As can be seen from the embodiments, the additional parts required for implementing the present invention are very small, and all require very simple software and electronic circuits.

[Brief description of drawings]

The drawings are all related to the present invention, and FIG. 1 is a structural circuit diagram illustrating the configuration of a basic block circuit of a read signal amplifying device according to the present invention and a disk storage device incorporating the same, and FIG. 2 is an amplification circuit according to the present invention. FIG. 3 is a waveform diagram illustrating the waveforms of the read signal before and after, and FIG. 3 is a circuit diagram illustrating the specific configuration of the circuit portion in the device of the present invention. In the figure, 1: disk, 2: head, 2a: arm, 2b: read, 3: head operating actuator, 4: actuator drive circuit, 5: read / write circuit, 6: demodulation circuit, 7: processor,
7a: storage area in processor, 8: bus, 10: disk storage device, 20: controller, 21: bus, 30: variable amplifier, 31,3
2: Differential transistor, 31a, 32a: Collector resistance, 33: Coupling resistance, 34, 35: Control transistor, 34a, 35b: Emitter resistance, 40: Amplification control circuit, 41: VI conversion circuit, 42: Amplification control Signal generating transistor, 42a: collector resistance, 42b: emitter resistance, 50: response speed designating means, 60: response speed control circuit, 61, 62: analog switch, 63: logic circuit, A: read signal amplitude, CS: Amplification factor control signal, C0 to C2: Response speed setting capacitor, DS: Head drive command, HS: Head selection command,
i: Track number, RD: Response speed command, RS: Read signal, RW:
Read / write command, R0: Read signal before amplification, R1: Read signal after amplification, T0 to T2: Response time, τ: Time constant, V: Power supply voltage, WS: Write signal, Z0 to Z2: In-plane Area.

Claims (1)

(57) [Claims] 1. A variable amplifier for amplifying a read signal of recording data on a disk read through a head with an amplification factor according to an amplification factor control signal, and an output signal of the variable amplifier to keep its output signal amplitude constant. An amplification factor control circuit that gives an amplification factor control signal to a variable amplifier so as to keep it, a response speed designating unit that issues a response speed command corresponding to the frequency of the read signal according to the current position on the disk surface of the head, and a response speed command And a response speed control circuit for controlling the temporal change rate of the amplification factor control signal from the amplification factor control circuit according to the time constant corresponding thereto, and a read signal amplification device for a disk storage device.